After a GPU reset happens, the driver creates a coredump file. However,
the user might not be aware of it. Log the file creation the user can
find more information about the device and add the file to bug reports.
This is similar to what the xe driver does.
Reviewed-by: Christian König
Signed-off
Instead of only triggering a wedged event for complete GPU resets,
trigger for all types, like soft resets and ring resets. Regardless of
the reset, it's useful for userspace to know that it happened because
the kernel will reject further submissions from that app.
Signed-off-by: André Almeida
--
This series does some small improvements to GPU reset information collection.
v2: Keep the wedge event in amdgpu_device_gpu_recover() and add and
extra check to avoid triggering two events.
André Almeida (3):
drm/amdgpu: Log the creation of a coredump file
drm/amdgpu: Log after a successf
When a ring reset happens, the kernel log shows only "amdgpu: Starting
ring reset", but when it finishes nothing appears in the
log. Explicitly write in the log that the reset has finished correctly.
Reviewed-by: Christian König
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/amdgpu/amdgp
They are noops on GFX12. There is no suspend/resume all support
in firmware so the function doesn't do anything. KFD already
handles its own queues and they should already be unmapped at this
point so even if this runs, it's not doing anything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/a
Use the IP type to look up the userq functions rather
than hardcoding it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
b/drivers/gpu/dr
Take a reference when we create a queue and drop it
when we destroy the queue. We need to keep the device
active while user queues are active.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --
They are noops on GFX11 for most firmware versions. KFD already
handles its own queues and they should already be unmapped at this
point so even if this runs, it's not doing anything.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 14 +-
1 file changed, 1 in
Applied the series. Thanks!
Alex
On Wed, Feb 19, 2025 at 3:39 PM Harry Wentland wrote:
>
> On 2025-02-19 13:46, Rodrigo Siqueira wrote:
> > Map all of my previously used email addresses to my @igalia.com address.
> >
> > Signed-off-by: Rodrigo Siqueira
>
> Acked-by: Harry Wentland
>
> Harry
>
Applied, thanks!
Alex
On Thu, Feb 20, 2025 at 11:28 AM André Almeida wrote:
>
> After a GPU reset happens, the driver creates a coredump file. However,
> the user might not be aware of it. Log the file creation the user can
> find more information about the device and add the file to bug reports
Remove extraneous tab and newline in dml2_core_dcn4.c that was
reported by the bot
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202502211920.txufwtsj-...@intel.com/
Fixes: 70839da6360 ("drm/amd/display: Add new DCN401 sources")
Signed-off-by: Aurabindo Pillai
---
Applied. Thanks!
On Thu, Feb 20, 2025 at 11:28 AM André Almeida wrote:
>
> When a ring reset happens, the kernel log shows only "amdgpu: Starting
> ring reset", but when it finishes nothing appears in the
> log. Explicitly write in the log that the reset has finished correctly.
>
> Reviewed-by:
On Thu, Feb 20, 2025 at 1:41 AM Wentao Liang wrote:
>
> In r420_cp_errata_init(), the RESYNC information is stored even
> when the Scratch register is not correctly allocated.
>
> Change the return type of r420_cp_errata_init() from void to int
> to propagate errors to the caller. Add error checki
Am 21.02.25 um 16:16 schrieb Alex Deucher:
> On Fri, Feb 21, 2025 at 10:13 AM Pierre-Eric Pelloux-Prayer
> wrote:
>> Otherwise an uninitialized value can be returned if
>> amdgpu_res_cleared returns true for all regions.
>>
>> Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
>>
VCN v5.0.1 also will need register offset normalization. Reuse the logic
from VCN v4.0.3. Also, avoid HDP flush similar to VCN v5.0.1
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 14 --
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.h |
Initialize RRMT enablement status from register.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 3 +++
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h | 5 -
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
b/drivers/g
Similar to JPEG v4.0.3, HDP flush shouldn't be performed by JPEG engine.
Keep it empty.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h | 1 +
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 1 +
3 files changed, 3 insertions(+),
Initialize RRMT status from register.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 ++
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
b/drivers/gpu/d
Incrementing the gpu_reset counter needs to be
in the is_guilty block. Alos move the fence
error before the reset to keep the original ordering.
Fixes: f447ba2bbd48 ("drm/amdgpu: Update amdgpu_job_timedout to check if the
ring is guilty")
Cc: Jesse Zhang
Signed-off-by: Alex Deucher
---
driver
From: Navid Assadian
[Why]
For subsampled YUV output formats, more pixels can get fetched and be
used for scaling.
[How]
Add the adjustment to the calculated recout, so the viewport covers the
corresponding pixels on the source plane.
Signed-off-by: Navid Assadian
Reviewed-by: Samson Tam
---
From: Samson Tam
[Why]
Some of unit tests use large scaling ratio such that when we
calculate optimal number of taps, max_taps is negative.
Then in recent change, we changed max_taps to uint instead
of int so now max_taps wraps and is positive. This change
changed the behaviour from returnin
From: Nicholas Kazlauskas
[Why]
DCN36 should inherit the same policy as DCN35 for DML2.
[How]
Add it to the list of checks in translation helper.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 +
1 file chan
From: Samson Tam
[Why]
IDENTITY_RATIO check uses 2 bits for integer, which only allows
checking downscale ratios up to 3. But we support up to 6x
downscale
[How]
Update IDENTITY_RATIO to check 3 bits for integer
Add ASSERT to catch if we downscale more than 6x
Signed-off-by: Samson Tam
Revi
From: Alex Hung
[WHAT & HOW]
Fix the incorrect value of the cursor_buffer_size.
Signed-off-by: Alex Hung
Reviewed-by: Zaeem Mohamed
---
.../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/disp
From: Tom Chung
This reverts commit 9b908d788090911d339a217c015e0022e8020b75.
We planning to disable the PSR-SU and fallback to PSR1 for
all eDP panels not only for specific eDP panel temporarily.
Reviewed-by: Sun peng Li
Signed-off-by: Tom Chung
Signed-off-by: Roman Li
---
.../drm/amd/disp
[AMD Official Use Only - AMD Internal Distribution Only]
Acked-by: Alex Deucher
From: Aurabindo Pillai
Sent: Friday, February 21, 2025 2:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Wentland, Harry
; Li, Sun peng (Leo) ; Pillai,
Aurabindo
Chaitanya's email is no longer valid.
Signed-off-by: Alex Deucher
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0845a8521e929..b37fd9fd5d551 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1031,7 +1031,6 @@ T:git
https://gitlab.freedes
From: Alex Hung
[WHAT & HOW]
Fix the incorrect value of the cursor_buffer_size.
Signed-off-by: Alex Hung
Reviewed-by: Zaeem Mohamed
---
.../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/disp
On 2025-02-21 11:42, Simon Ser wrote:
> On Friday, February 21st, 2025 at 17:18, Harry Wentland
> wrote:
>
>> I did a brief survey of other enum properties and noticed
>> that this isn't well documented for others, such as the Content
>> Protection connector property, or the COLOR_RANGE and C
From: Tom Chung
[Why]
PSR-SU may cause some glitching randomly on several panels.
[How]
Temporarily disable the PSR-SU and fallback to PSR1 for
all eDP panels.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3388
Cc: Mario Limonciello
Cc: Alex Deucher
Cc: sta...@vger.kernel.org
Reviewe
Some OEMs support custom brightness curves where the ATIF method includes
a collection of data points where the input signal is mapped out to
percentage of luminance. This series shuffles around some code to add in
the ability to do that mapping in amdgpu_dm when brightness is set.
Mario Limonciel
On Friday, February 21st, 2025 at 17:18, Harry Wentland
wrote:
> I did a brief survey of other enum properties and noticed
> that this isn't well documented for others, such as the Content
> Protection connector property, or the COLOR_RANGE and COLOR_ENCODING
> plane properties.
Isn't the Conte
The ATIF method on some systems will provide a backlight curve. Pass
this curve into amdgpu_dm add it to the structures.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 20 +++
drivers/g
As new members are introduced to the structure copying the entire
structure will help avoid missing them.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.
Upgrading the kernel may cause some systems that were previously not using
a firmware specified brightness curve to use one.
In the event of problems with this curve (for example an interpolation
error) add a new dcdebugmask value that can be used to turn it off. Also
add an info message to show
Making a copy of the backlight caps structure between uses is unnecessary.
Refer to pointers to the same structure when using it.
Signed-off-by: Mario Limonciello
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 ---
1 file changed, 21 insertions(+), 29 deletions(-)
diff -
From: Samson Tam
[Why & How]
Passing uint into uchar function param. Pass uint instead
Signed-off-by: Samson Tam
Reviewed-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c | 2 +-
drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h | 4 ++--
2 files changed, 3 insertion
From: Peichen Huang
[WHY]
replace dio encoder access to work with new dio encoder
assignment.
[HOW}
1. before validation, access dio encoder by get_temp_dio_link_enc()
2. after validation, access dio encoder through pipe_ctx->link_res
Reviewed-by: Wenjing Liu
Reviewed-by: Meenakshikumar Somasu
On Friday, February 21st, 2025 at 19:41, Harry Wentland
wrote:
> > Other people have argued that strings make it easier for user-space to
> > start using a new KMS property without deploying new kernel uAPI headers.
>
> I don't understand this argument. You would either need to define the
> str
Reviewed-by: Alex Hung
On 2/15/25 14:15, Melissa Wen wrote:
When switching to drm_edid, we slightly changed how to get edid by
removing the possibility of getting them from dc_link when in aux
transaction mode. As MST doesn't initialize the connector with
`drm_connector_init_with_ddc()`, restor
Applied. Thanks!
Alex
On Fri, Feb 21, 2025 at 3:48 PM Alex Hung wrote:
>
> Reviewed-by: Alex Hung
>
> On 2/15/25 14:15, Melissa Wen wrote:
> > When switching to drm_edid, we slightly changed how to get edid by
> > removing the possibility of getting them from dc_link when in aux
> > transactio
Applied. Thanks!
Alex
On Mon, Feb 17, 2025 at 5:48 AM Colin Ian King wrote:
>
> There is a spelling mistake in max_oustanding_when_urgent_expected,
> fix it.
>
> Signed-off-by: Colin Ian King
> ---
> .../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
> .../dc/dml2/dml21/s
From: Yilin Chen
[why]
some board designs have eDP0 connected to DP1, need a way to enable
support_edp0_on_dp1 flag, otherwise edp related features cannot work
[how]
do a dmi check during dm initialization to identify systems that
require support_edp0_on_dp1. Optimize quirk table with callback
f
On Fri, Feb 21, 2025 at 10:13 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> Otherwise an uninitialized value can be returned if
> amdgpu_res_cleared returns true for all regions.
>
> Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
> Signed-off-by: Pierre-Eric Pelloux-Prayer
Acked-
On 2025-02-21 10:09, Aurabindo Pillai wrote:
> Remove extraneous tab and newline in dml2_core_dcn4.c that was
> reported by the bot
>
> Reported-by: kernel test robot
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202502211920.txufwtsj-...@intel.com/
> Fixes: 70839da6360 ("drm/amd/display: Ad
Deprecate KFD XGMI peer info calls in favour of calling directly from
simplified XGMI peer info functions.
v2: generalize bandwidth interface to return range in one call
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 42
drivers/gpu/drm/amd/amdgpu/
Chaitanya is no longer with AMD, and the responsibility has been
taken over by Austin.
Signed-off-by: Aurabindo Pillai
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c8b35ca294a0..d167946f88e5 100644
--- a/MAINTAINERS
+++ b/MAI
On 2025-02-21 14:25, Aurabindo Pillai wrote:
> Chaitanya is no longer with AMD, and the responsibility has been
> taken over by Austin.
>
> Signed-off-by: Aurabindo Pillai
Reviewed-by: Harry Wentland
Harry
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
On 2025-02-13 13:21, Leo Li wrote:
>
>
>
> On 2024-12-19 23:33, Alex Hung wrote:
>> This adds support for a 3D LUT.
>>
>> The color pipeline now consists of the following colorops:
>> 1. 1D curve colorop
>> 2. Multiplier
>> 3. 3x4 CTM
>> 4. 1D curve colorop
>> 5. 1D LUT
>> 6. 3D LUT
>> 7. 1D
On 2025-02-21 12:26, Alex Deucher wrote:
> Chaitanya's email is no longer valid.
>
> Signed-off-by: Alex Deucher
Reviewed-by: Harry Wentland
Harry
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0845a8521e929..b37fd9fd5d551 10
Hi Dave, Simona,
New stuff for 6.15.
The following changes since commit 1abb2648698bf10783d2236a6b4a7ca5e8021699:
drm/amdgpu: avoid buffer overflow attach in smu_sys_set_pp_table()
(2025-02-12 19:47:15 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/lin
On Fri, Feb 21, 2025 at 10:13 AM Pierre-Eric Pelloux-Prayer
wrote:
>
> Otherwise an uninitialized value can be returned if
> amdgpu_res_cleared returns true for all regions.
>
> Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
Possibly closes: https://gitlab.freedesktop.org/drm
On 2/21/2025 11:47 AM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> - Introduce a new function `sdma_v4_4_2_init_sysfs_reset_mask` to initialize
> the sysfs reset mask for SDMA.
> - Move the initialization of the sysfs reset mask to the `late_init` stage to
> ensure that the
Otherwise an uninitialized value can be returned if
amdgpu_res_cleared returns true for all regions.
Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
Signed-off-by: Pierre-Eric Pelloux-Prayer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1
Do a bit of house keeping in gpu_scheduler.h by grouping the API by type
of object it operates on.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
include/drm/gpu_scheduler.h | 60 -
1 file c
Now that we have a header file for internal scheduler interfaces we can
move some more prototypes into it. By doing that we eliminate the chance
of drivers trying to use something which was not intended to be used.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matth
Replace a copy of DRM scheduler's to_drm_sched_job with a copy of a newly
added drm_sched_entity_queue_pop.
This allows breaking the hidden dependency that queue_node has to be the
first element in struct drm_sched_job.
A comment is also added with a reference to the mailing list discussion
expla
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Leo Liu
> -Original Message-
> From: Sundararaju, Sathishkumar
> Sent: February 20, 2025 1:37 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Leo ; Sundararaju, Sathishkumar
>
> Subject: [PATCH 3/3]
We can re-order some struct members and take u32 credits outside of the
pointer sandwich and also for the last_dependency member we can get away
with an unsigned int since for dependency we use xa_limit_32b.
Pahole report before:
/* size: 160, cachelines: 3, members: 14 */
/* sum m
Lets add some helpers for peeking and popping from the job queue which allows us
to re-order the fields in struct drm_sched_job and remove one hole.
As in the process we have added a header file for scheduler internal prototypes,
lets also use it more and cleanup the "exported" header a bit.
v2:
Helper is for scheduler internal use so lets hide it from DRM drivers
completely.
At the same time we change the method of checking whethere there is
anything in the queue from peeking to looking at the node count.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matt
display performance level when set not supported
Signed-off-by: Mangesh Gadre
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 5 -
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/d
Implement the GFX12 KCQ pipe reset, and disable the GFX12
kernel compute queue until the CPFW fully supports it.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 90 +-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/a
Idea is to add helpers for peeking and popping jobs from entities with
the goal of decoupling the hidden assumption in the code that queue_node
is the first element in struct drm_sched_job.
That assumption usually comes in the form of:
while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Kamal, Asad
Sent: Friday, February 21, 2025 20:19
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
Cc: Zhang, Hawking ; Ma, Le ; Zhang,
Morris ; Kamal
Implement the GFX12 kgq pipe reset, and temporarily disable
the GFX12 pipe reset untill the CPFW fully support it.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 68 +-
1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Implement the GFX11 compute pipe reset. As the GFX11 CPFW
still hasn't fully supported pipe reset yet, therefore
disable the KCQ pipe reset temporarily.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 135 -
1 file changed, 133 insertions(+), 2 del
Implement the kernel graphics queue pipe reset,and the driver
will fallback to pipe reset when the queue reset fails. However,
the ME FW hasn't fully supported pipe reset yet so disable the
KGQ pipe reset temporarily.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2
On 2/17/2025 8:05 PM, Alex Deucher wrote:
On Mon, Feb 17, 2025 at 9:18 AM SRINIVASAN SHANMUGAM
wrote:
On 2/17/2025 7:44 PM, Alex Deucher wrote:
On Sat, Feb 15, 2025 at 3:02 AM SRINIVASAN SHANMUGAM
wrote:
On 2/14/2025 11:05 PM, Alex Deucher wrote:
Re-send the mes message on resume to make
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Lazar, Lijo
Sent: Friday, February 21, 2025 4:13 PM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kim, Jonathan
; Zhu, Jiadong ; Huang, Tim
; Prosyak, Vitaly
Subject: Re:
On 2/21/2025 4:15 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> - Added `sdma_v4_4_2_update_reset_mask` function to update the reset mask.
> - update the sysfs reset mask to the `late_init` stage to ensure that the SMU
> initialization
> and capability setup are compl
nux/kernel/git/daeinki/drm-exynos.git
exynos-drm-next
patch link:
https://lore.kernel.org/r/20250220064050.686-1-vulab%40iscas.ac.cn
patch subject: [PATCH] drm/radeon: Add error handlings for r420 cp errata
initiation
config: i386-buildonly-randconfig-005-20250221
(https://download.01.o
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: Xie, Patrick
> Sent: Friday, February 21, 2025 11:19 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Xie, Patrick
> Subject: [PATCH 2/3] drm/amdgpu: Refine bad page adding
>
[AMD Official Use Only - AMD Internal Distribution Only]
The series is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Xie, Patrick
> Sent: Friday, February 21, 2025 11:19 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Xie, Patrick
> Subject: [PATCH 3
From: "jesse.zh...@amd.com"
- Added `sdma_v4_4_2_update_reset_mask` function to update the reset mask.
- update the sysfs reset mask to the `late_init` stage to ensure that the SMU
initialization
and capability setup are completed before checking the SDMA reset
capability.
- For IP versio
From: Yilin Chen
[why]
some board designs have eDP0 connected to DP1, need a way to enable
support_edp0_on_dp1 flag, otherwise edp related features cannot work
[how]
do a dmi check during dm initialization to identify systems that
require support_edp0_on_dp1. Optimize quirk table with callback
f
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Gadre, Mangesh
Sent: Friday, February 21, 2025 9:52 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Cc: Gadre, Mangesh ; Lazar, Lijo
Subject: [PATCH] drm/
This DC patchset brings improvements in multiple areas. In summary, we have:
- Disable PSR-SU on eDP panels
- Fix HPD after GPU reset
- Fixes on dcn4x init, DML2 state policy on DCN36
- Various minor logic fixes
Cc: Daniel Wheeler
Alex Hung (1):
drm/amd/display: update incorrect cursor b
From: Tom Chung
This reverts commit 9b908d788090911d339a217c015e0022e8020b75.
We planning to disable the PSR-SU and fallback to PSR1 for
all eDP panels not only for specific eDP panel temporarily.
Reviewed-by: Sun peng Li
Signed-off-by: Tom Chung
Signed-off-by: Roman Li
---
.../drm/amd/disp
This DC patchset brings improvements in multiple areas. In summary, we have:
- Disable PSR-SU on eDP panels
- Fix HPD after GPU reset
- Fixes on dcn4x init, DML2 state policy on DCN36
- Various minor logic fixes
Cc: Daniel Wheeler
Alex Hung (1):
drm/amd/display: update incorrect cursor b
From: Alex Hung
[WHAT & HOW]
Fix the incorrect value of the cursor_buffer_size.
Signed-off-by: Alex Hung
Reviewed-by: Zaeem Mohamed
---
.../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/drivers/gpu/drm/amd/disp
From: Peichen Huang
[WHY]
replace dio encoder access to work with new dio encoder
assignment.
[HOW}
1. before validation, access dio encoder by get_temp_dio_link_enc()
2. after validation, access dio encoder through pipe_ctx->link_res
Reviewed-by: Wenjing Liu
Reviewed-by: Meenakshikumar Somasu
From: "Patel, Swapnil"
[why & how]
Refactor existing code related to DCN4x for better code sharing with
other modules
Reviewed-by: Charlene Liu
Signed-off-by: Swapnil Patel
Signed-off-by: Zaeem Mohamed
---
.../amd/display/dc/dccg/dcn20/dcn20_dccg.h| 94
.../amd/display/dc/dccg/
From: Navid Assadian
[Why]
In order to avoid component conflicts, spl namespace is needed.
[How]
Adding SPL namespace to the public API os that each user of SPL can have
their own namespace.
Signed-off-by: Navid Assadian
Reviewed-by: Samson Tam
---
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.
From: Mike Katsnelson
[Why]
Transitioning from low to high resolutions at high refresh rates caused grey
corruption.
During the transition state, there is a period where plane size is based on low
resultion
state and ODM slices are based on high resoultion state, causing the entire
plane to be
From: Taimur Hassan
Signed-off-by: Taimur Hassan
Signed-off-by: Zaeem Mohamed
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_
From: Samson Tam
[Why]
Some of unit tests use large scaling ratio such that when we
calculate optimal number of taps, max_taps is negative.
Then in recent change, we changed max_taps to uint instead
of int so now max_taps wraps and is positive. This change
changed the behaviour from returnin
From: Navid Assadian
[Why]
For subsampled YUV output formats, more pixels can get fetched and be
used for scaling.
[How]
Add the adjustment to the calculated recout, so the viewport covers the
corresponding pixels on the source plane.
Signed-off-by: Navid Assadian
Reviewed-by: Samson Tam
---
From: Michael Strauss
[WHY]
Previously the 128b/132b LTTPR support DPCD field was used to decide if
FIXED_VS training sequence required a rate toggle before initiating LT.
When running DP2.1 4.9.x.x compliance tests, emulated LTTPRs can report
no-128b/132b support which is then forwarded by the
From: Yihan Zhu
[WHY]
If max_downscale_src_width check fails, we exit early from TAP calculation and
left a NULL
value to the scaling data structure to cause the zero divide in the DML
validation.
[HOW]
Call set default TAP calculation before early exit in
get_optimal_number_of_taps due to
ma
From: Taimur Hassan
Signed-off-by: Taimur Hassan
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f76884fe86e3..f646f537a3dc
From: Samson Tam
[Why & How]
Passing uint into uchar function param. Pass uint instead
Signed-off-by: Samson Tam
Reviewed-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c | 2 +-
drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h | 4 ++--
2 files changed, 3 insertion
From: Aurabindo Pillai
With HostVM enabled, DCN31 fails to pass validation for 3x4k60. Some Linux
userspace does not downgrade one of the monitors to 4k30, and the result
is that the monitor does not light up. Disable it until the bandwidth
calculation failure is resolved.
Reviewed-by: Sun peng
From: Krunoslav Kovac
[Why]
Removes unused header
Reviewed-by: Samson Tam
Signed-off-by: Krunoslav Kovac
Signed-off-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c
b/drivers/gp
This DC patchset brings iprovements in multiple areas. In summary, we have:
- Disable PSR-SU on eDP panels
- Fix HPD after GPU reset
- Fixes on dcn4x init, DML2 state policy on DCN36
- Various minor logic fixes
Cc: Daniel Wheeler
Alex Hung (1):
drm/amd/display: update incorrect cursor bu
From: Nicholas Kazlauskas
[Why]
DCN36 should inherit the same policy as DCN35 for DML2.
[How]
Add it to the list of checks in translation helper.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Zaeem Mohamed
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 +
1 file chan
From: "Ostrowski, Rafal"
[Why]
We must implement an ACPI re-timer programming interface and notify
ACPI driver whenever a PHY transition is about to take place.
Because some trace lengths on certain platforms are very long,
then a re-timer may need to be programmed whenever a PHY transition
take
From: Samson Tam
[Why]
IDENTITY_RATIO check uses 2 bits for integer, which only allows
checking downscale ratios up to 3. But we support up to 6x
downscale
[How]
Update IDENTITY_RATIO to check 3 bits for integer
Add ASSERT to catch if we downscale more than 6x
Signed-off-by: Samson Tam
Revi
From: "Assadian, Navid"
The mismatch type comparison/assignment may cause data loss. Since the
values are always non-negative, it is safe to use unsigned variables to
resolve the mismatch.
Signed-off-by: Navid Assadian
Reviewed-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/sspl/dc_sp
From: "Assadian, Navid"
The mismatch type comparison/assignment may cause data loss. Since the
values are always non-negative, it is safe to use unsigned variables to
resolve the mismatch.
Signed-off-by: Navid Assadian
Reviewed-by: Joshua Aberback
---
drivers/gpu/drm/amd/display/dc/sspl/dc_sp
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