Thanks a lot for the patch!
Small commit title nit, sorry for spotting this earlier: this commit
adds BT2020 *limited* range - full range was already supported, see the
changes in amdgpu_dm.c and dpp.h.
On 14.02.25 16:00, roman...@amd.com wrote:
From: Ilya Bakoulin
[Why/How]
Need to add su
On 12.02.2025 17:11, Alex Deucher wrote:
From: "chr[]"
resume and irq handler happily races in set_power_state()
* amdgpu_legacy_dpm_compute_clocks() needs lock
* protect irq work handler
* fix dpm_enabled usage
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2524
Fixes: 3712e7a49459
Hi Roman,
> not handled properly when full range quantization is used
I wasn't aware that there was something wrong with the full range
handling and it's also not clear from the [How] section what that was -
can you shortly elaborate on that? Apart from that it looks good to me,
thanks!
On
Thanks a lot for the patch!
Small commit title nit, sorry for spotting this earlier: this commit
adds BT2020 *limited* range - full range was already supported, see the
changes in amdgpu_dm.c and dpp.h.
On 14.02.25 16:00, roman...@amd.com wrote:
From: Ilya Bakoulin
[Why/How]
Need to add su
Hello Xiaogang Chen,
Commit 8544374c0f82 ("drm/amdkfd: Have kfd driver use same PASID
values from graphic driver") from Jan 13, 2025 (linux-next), leads to
the following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:1694
kfd_process_device_init_vm()
On 2/12/2025 9:41 PM, Alex Deucher wrote:
> From: "chr[]"
>
> resume and irq handler happily races in set_power_state()
>
> * amdgpu_legacy_dpm_compute_clocks() needs lock
> * protect irq work handler
> * fix dpm_enabled usage
>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2524
On 2/17/2025 3:26 PM, Lazar, Lijo wrote:
>
>
> On 2/12/2025 9:41 PM, Alex Deucher wrote:
>> From: "chr[]"
>>
>> resume and irq handler happily races in set_power_state()
>>
>> * amdgpu_legacy_dpm_compute_clocks() needs lock
>> * protect irq work handler
>> * fix dpm_enabled usage
>>
>> Closes
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Kamal, Asad
Sent: Friday, February 14, 2025 15:28
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
Cc: Zhang, Hawking ; Ma, Le ; Zhang,
Morris ; Kamal, Asad ; De
Am 16.02.25 um 03:43 schrieb Srinivasan Shanmugam:
> RLCG Register Access is a way for virtual functions to safely access GPU
> registers in a virtualized environment., including TLB flushes and
> register reads. When multiple threads or VFs try to access the same
> registers simultaneously, it can
On Sat, Feb 15, 2025 at 3:02 AM SRINIVASAN SHANMUGAM
wrote:
>
>
> On 2/14/2025 11:05 PM, Alex Deucher wrote:
>
> Re-send the mes message on resume to make sure the
> mes state is up to date.
>
> Fixes: 8521e3c5f058 ("drm/amd/amdgpu: limit single process inside MES")
> Signed-off-by: Alex Deucher
There is a spelling mistake in max_oustanding_when_urgent_expected,
fix it.
Signed-off-by: Colin Ian King
---
.../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++---
.../dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h| 2 +-
2 files changed, 4 insertions(+), 4 deletions(
On 2/17/2025 10:00, Alex Deucher wrote:
On Mon, Feb 17, 2025 at 10:45 AM Alex Deucher wrote:
On Mon, Feb 17, 2025 at 10:38 AM Christian König
wrote:
Am 17.02.25 um 16:10 schrieb Alex Deucher:
There was a quirk added to add a workaround for a Sapphire
RX 5600 XT Pulse. However, the quirk o
On Mon, Feb 17, 2025 at 10:45 AM Alex Deucher wrote:
>
> On Mon, Feb 17, 2025 at 10:38 AM Christian König
> wrote:
> >
> > Am 17.02.25 um 16:10 schrieb Alex Deucher:
> > > There was a quirk added to add a workaround for a Sapphire
> > > RX 5600 XT Pulse. However, the quirk only checks the vendor
Am 17.02.25 um 16:10 schrieb Alex Deucher:
> There was a quirk added to add a workaround for a Sapphire
> RX 5600 XT Pulse. However, the quirk only checks the vendor
> ids and not the subsystem ids. The quirk really should
> have checked the subsystem vendor and device ids as now
> this quirk get
On Mon, Feb 17, 2025 at 9:18 AM SRINIVASAN SHANMUGAM
wrote:
>
>
> On 2/17/2025 7:44 PM, Alex Deucher wrote:
> > On Sat, Feb 15, 2025 at 3:02 AM SRINIVASAN SHANMUGAM
> > wrote:
> >>
> >> On 2/14/2025 11:05 PM, Alex Deucher wrote:
> >>
> >> Re-send the mes message on resume to make sure the
> >> me
There was a quirk added to add a workaround for a Sapphire
RX 5600 XT Pulse. However, the quirk only checks the vendor
ids and not the subsystem ids. The quirk really should
have checked the subsystem vendor and device ids as now
this quirk gets applied to all RX 5600 and it seems to
cause proble
From: "chr[]"
resume and irq handler happily races in set_power_state()
* amdgpu_legacy_dpm_compute_clocks() needs lock
* protect irq work handler
* fix dpm_enabled usage
v2: fix clang build, integrate Lijo's comments (Alex)
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2524
Fixes: 3
On 2/17/2025 7:44 PM, Alex Deucher wrote:
On Sat, Feb 15, 2025 at 3:02 AM SRINIVASAN SHANMUGAM
wrote:
On 2/14/2025 11:05 PM, Alex Deucher wrote:
Re-send the mes message on resume to make sure the
mes state is up to date.
Fixes: 8521e3c5f058 ("drm/amd/amdgpu: limit single process inside MES
Add core reset control registers for JPEG4_0_3
Signed-off-by: Sathishkumar S
Acked-by: Christian König
Reviewed-by: Leo Liu
---
.../include/asic_reg/vcn/vcn_4_0_3_offset.h | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_
From: Mario Limonciello
Scoped guards will release the mutex when they go out of scope.
Adjust the code to use these instead.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers
From: Mario Limonciello
Scoped guards will release the mutex when they go out of scope.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/
On 2/13/2025 6:33 PM, Lijo Lazar wrote:
> If firmware supported NPS modes are available through CAP register, use
> those values for supported NPS modes.
>
> Signed-off-by: Lijo Lazar
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 36 +++
> 1 file changed, 26 insertion
From: Mario Limonciello
amdgpu_dm_irq_resume_early() and amdgpu_dm_irq_resume_late() don't
have any error flows. Change the return type from integer to void.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 7 ++-
drivers/gpu/drm/amd/display/amdg
On 2/18/2025 8:36 AM, Sathishkumar S wrote:
> Add ring reset function callback for JPEG4_0_3 to
> recover from job timeouts without a full gpu reset.
>
> V2:
> - sched->ready flag shouldn't be modified by HW backend (Christian)
>
> V3:
> - Dont modifying sched/job-submission state from HW ba
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Thursday, February 13, 2025 21:03
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Lin, Amber
Subject: [PATCH] drm
Add core reset control registers for JPEG4_0_3
Signed-off-by: Sathishkumar S
Acked-by: Christian König
Reviewed-by: Leo Liu
---
.../include/asic_reg/vcn/vcn_4_0_3_offset.h | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_
From: Mario Limonciello
The displays currently don't get turned off until after other IP blocks
have been suspended. However turning off the displays first gives a
visible response that the system is on it's way down.
Turn off displays in a prepare_suspend() callback instead.
Signed-off-by: Ma
Add ring reset function callback for JPEG4_0_3 to
recover from job timeouts without a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by HW backend (Christian)
V3:
- Dont modifying sched/job-submission state from HW backend (Christian)
- Implement per-core reset sequence
V4:
-
From: Mario Limonciello
By using a _free() macro multiple duplicated snippets of code to free
the sink can be dropped. The sink will be released when leaving scope.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ---
1 file changed, 4 in
From: Mario Limonciello
All cases except a failure to create a copy of the current context will
call dc_state_release() on the copied context.
Use a _free() macro to free the context and then adjust the error handling
flow to drop the unnecessary use of goto statements.
Signed-off-by: Mario Lim
From: Mario Limonciello
drm_err() is helpful to show which device had the error. Adjust to
using this instead for error messages.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drive
From: Mario Limonciello
amdgpu_dm_commit_zero_streams() returns a DC error code that isn't
checked. Add an explicit check to this and fail dm_suspend() if it
is not DC_OK.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++-
1 file changed, 7 ins
From: Mario Limonciello
I was looking at amdgpu_dm for some issues and just noticed some cases
that could use cleanups for scoped cleanups and error messaging.
Mario Limonciello (13):
drm/amd/display: Change amdgpu_dm_irq_suspend() to void
drm/amd/display: Drop `ret` variable from dm_suspend
From: Mario Limonciello
drm_dbg() is helpful to show which device had the debug statement.
Adjust to using this instead for debug messages.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Mario Limonciello
drm_err() will show which device has the error.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/dr
From: Mario Limonciello
amdgpu_dm_irq_suspend() doesn't have any error flows and always
returns zero.
Change the function to void.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 3 +--
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h | 2 +-
From: Mario Limonciello
A scoped guard will release the mutex when it goes out of scope.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdg
From: Mario Limonciello
The `ret` variable in dm_suspend() doesn't get set and is just used
to return 0. Drop the needless declaration.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/
From: Mario Limonciello
Using a _free(kfree) macro drops the need for a goto statement
as it will be freed when it goes out of scope.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git
On 2/13/2025 11:17 AM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This commit introduces a caller parameter to the amdgpu_sdma_reset_instance
> function to differentiate
> between reset requests originating from the KGD and KFD.
> This change ensures proper synchronization b
On 2/17/2025 8:56 PM, Alex Deucher wrote:
> From: "chr[]"
>
> resume and irq handler happily races in set_power_state()
>
> * amdgpu_legacy_dpm_compute_clocks() needs lock
> * protect irq work handler
> * fix dpm_enabled usage
>
> v2: fix clang build, integrate Lijo's comments (Alex)
>
> Cl
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Lijo,
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, February 18, 2025 11:36 AM
To: Zhang, Jesse(Jie) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix
; Kim, Jonathan ; Zhu, Jiadong
Subject: Re: [
On Mon, Feb 17, 2025 at 10:38 AM Christian König
wrote:
>
> Am 17.02.25 um 16:10 schrieb Alex Deucher:
> > There was a quirk added to add a workaround for a Sapphire
> > RX 5600 XT Pulse. However, the quirk only checks the vendor
> > ids and not the subsystem ids. The quirk really should
> > hav
Add ring reset function callback for JPEG4_0_3 to
recover from job timeouts without a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by HW backend (Christian)
V3:
- Dont modifying sched/job-submission state from HW backend (Christian)
- Implement per-core reset sequence
Signed-
[AMD Official Use Only - AMD Internal Distribution Only]
Ping on this series?
Jesse
-Original Message-
From: jesse.zh...@amd.com
Sent: Thursday, February 13, 2025 1:47 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Kuehling, Felix
; Kim, Jonathan ; Zhu, Jiadong
; Zhang,
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