It is possible for some waves in a workgroup to finish their save
sequence before the group leader has had time to capture the workgroup
barrier state. When this happens, having those waves exit do impact the
barrier state. As a consequence, the state captured by the group leader
is invalid, and
Hi,
The goal of this work is to find a nice way to allow amdgpu to perform
async page flips in the overlay plane as well, not only on the primary
one. Currently, when using the atomic uAPI, this is the only type of
plane allowed to do async flips, and every driver accepts it.
This patchset re-use
Add register list and enable devcoredump for JPEG5_0_1
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 65 +++-
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.h | 61 ++
2 files changed, 124 insertions(+), 2 deletions(-)
diff --git a/
This looks to be the same issue as this one:
https://gitlab.freedesktop.org/drm/amd/-/issues/3861
Please follow along on the bug report.
Thanks,
Alex
On Tue, Jan 28, 2025 at 12:06 PM Alex Deucher wrote:
>
> Another potential better patch to try.
>
> Alex
>
> On Tue, Jan 28, 2025 at 10:07 AM Ale
On 1/28/2025 5:06 PM, Sundararaju, Sathishkumar wrote:
> Hi Lijo,
>
>
> On 1/28/2025 3:04 PM, Lazar, Lijo wrote:
>>
>> On 1/28/2025 2:39 PM, Sathishkumar S wrote:
>>> Add devcoredump helper functions that can be reused for all jpeg
>>> versions.
>>>
>>> Signed-off-by: Sathishkumar S
>>> ---
>
amdgpu can handle async flips on overlay planes, so allow it for atomic
async checks.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdg
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: Lazar, Lijo
Sent: Tuesday, January 28, 2025 1:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad ; Ma,
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
> Add devcoredump helper functions that can be reused for all jpeg versions.
>
> Signed-off-by: Sathishkumar S
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 59
> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 7 +++
> 2 f
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
> Add register list and enable devcoredump for JPEG4_0_3
>
> Signed-off-by: Sathishkumar S
> ---
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 58
> 1 file changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgp
Hi Lijo,
On 1/28/2025 3:04 PM, Lazar, Lijo wrote:
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
Add devcoredump helper functions that can be reused for all jpeg versions.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 59
drivers/gpu/d
On Tue, 28 Jan 2025 11:37:53 +0200
Raag Jadav wrote:
> On Mon, Jan 27, 2025 at 12:23:28PM +0200, Pekka Paalanen wrote:
> > On Wed, 22 Jan 2025 07:22:25 +0200
> > Raag Jadav wrote:
> >
> > > On Tue, Jan 21, 2025 at 02:14:56AM +0100, Xaver Hugl wrote:
> > > > > +It is the responsibility of th
This patch-series enables jpeg devcoredump support
Sathishkumar S (9):
drm/amdgpu: Add a func for core specific reg offset
drm/amdgpu: Add helper funcs for jpeg devcoredump
drm/amdgpu: Enable devcoredump for JPEG4_0_3
drm/amdgpu: Enable devcoredump for JPEG5_0_1
drm/amdgpu: Enable devcor
Add an inline function to calculate core specific register offsets for
JPEG v4.0.3 and reuse it, makes code more readable and easier to align.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 54 +++-
1 file changed, 24 insertions(+), 30 deletions(
Add register list and enable devcoredump for JPEG4_0_3
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 58
1 file changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
ind
Add devcoredump helper functions that can be reused for all jpeg versions.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 59
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 7 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/
Hi Lijo,
On 1/28/2025 3:16 PM, Lazar, Lijo wrote:
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
Add register list and enable devcoredump for JPEG4_0_3
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 58
1 file changed, 58 insertions(+)
Currently, DRM atomic uAPI allows only primary planes to be flipped
asynchronously. However, each driver might be able to perform async
flips in other different plane types. To enable drivers to set their own
restrictions on which type of plane they can or cannot flip, use the
existing atomic_async
Add register list and enable devcoredump for JPEG4_0_0
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 40 +-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg
Add register list and enable devcoredump for JPEG2_0_0
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 7
Add register list and enable devcoredump for JPEG4_0_5
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
b/drivers/gpu/drm/amd/amdgpu/jp
Add register list and enable devcoredump for JPEG3_0_0
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 4
Add register list and enable devcoredump for JPEG2_5_0
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 41 ++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 1
From: Dillon Varone
[WHY & HOW]
- Fix indexing phantom planes for mcache programming in the wrapper
- Fix phantom mcache allocations to align with HW guidance
- Fix mcache assignment for chroma plane for multi-planar formats
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by:
[WHAT & HOW]
hpo_stream_to_link_encoder_mapping has size MAX_HPO_DP2_ENCODERS(=4),
but location can have size up to 6. As a result, it is necessary to
check location against MAX_HPO_DP2_ENCODERS.
Similiarly, disp_cfg_stream_location can be used as an array index which
should be 0..5, so the ASSERT
From: Martin Tsai
[WHY]
Some panels may not handle idle pattern properly during PSR entry.
[HOW]
Add a condition to allow multiple options on power down
sequence during PSR1 entry.
Reviewed-by: Anthony Koo
Signed-off-by: Martin Tsai
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/d
From: Brandon Syu
This reverts commit de612738e9771bd66aeb20044486c457c512f684.
Reason to revert: screen flashes or gray screen appeared half of the
screen after resume from S4/S5.
Reviewed-by: Charlene Liu
Signed-off-by: Brandon Syu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN3.2 and DCN4
* Code factoring for SPL module
* Various bug fixes
Cc: Daniel Wheeler
Ahmed, Muhammad (1):
drm/amd/display: Enable odm 4:1 when debug key is set
Alex Hung (1):
drm/amd/display: Fi
From: Lo-an Chen
[WHY]
When the system powers up eDP with external monitors in seamless boot
sequence, stutter get enabled before TTU and HUBP registers being
programmed, which resulting in underflow.
[HOW]
Enable TTU in hubp_init.
Change the sequence that do not perpare_bandwidth and optimize_b
** resend the patchset because only 5 of 10 patches were sent successully **
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Fixes on DCN3.2 and DCN4
* Code factoring for SPL module
* Various bug fixes
Ahmed, Muhammad (1):
drm/amd/display: Enable odm 4:1 wh
From: Dillon Varone
[WHY & HOW]
- Fix indexing phantom planes for mcache programming in the wrapper
- Fix phantom mcache allocations to align with HW guidance
- Fix mcache assignment for chroma plane for multi-planar formats
Reviewed-by: Austin Zheng
Signed-off-by: Dillon Varone
Signed-off-by:
[WHAT & HOW]
hpo_stream_to_link_encoder_mapping has size MAX_HPO_DP2_ENCODERS(=4),
but location can have size up to 6. As a result, it is necessary to
check location against MAX_HPO_DP2_ENCODERS.
Similiarly, disp_cfg_stream_location can be used as an array index which
should be 0..5, so the ASSERT
From: Martin Tsai
[WHY]
Some panels may not handle idle pattern properly during PSR entry.
[HOW]
Add a condition to allow multiple options on power down
sequence during PSR1 entry.
Reviewed-by: Anthony Koo
Signed-off-by: Martin Tsai
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/d
From: Lo-an Chen
[WHY]
When the system powers up eDP with external monitors in seamless boot
sequence, stutter get enabled before TTU and HUBP registers being
programmed, which resulting in underflow.
[HOW]
Enable TTU in hubp_init.
Change the sequence that do not perpare_bandwidth and optimize_b
From: Brandon Syu
This reverts commit de612738e9771bd66aeb20044486c457c512f684.
Reason to revert: screen flashes or gray screen appeared half of the
screen after resume from S4/S5.
Reviewed-by: Charlene Liu
Signed-off-by: Brandon Syu
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/
From: Muhammad Ahmed
[WHAT]
odm 4to1 is enabled when debug key is set.
Reviewed-by: Charlene Liu
Reviewed-by: Alvin Lee
Signed-off-by: Muhammad Ahmed
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dr
From: Dmytro
Remove the static qualifier to make it available for code sharing
with other components.
Reviewed-by: Charlene Liu
Signed-off-by: Dmytro
Signed-off-by: Charlene Liu
Signed-off-by: Alex Hung
---
.../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 24 +--
.../amd/display/dc/d
From: Samson Tam
[WHY & HOW]
- Move SPL from dc/spl to dc/sspl
- Update build files and header paths
- Remove dc/spl files
Reviewed-by: George Zhang
Signed-off-by: Samson Tam
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/Makefile | 2 +-
drivers/gpu/drm/am
From: Aric Cyr
[WHY]
When SubVP is active the HW cursor size is limited to 64x64, and
anything larger will force composition which is bad for gaming on
DCN3.2 if the game uses a larger cursor.
[HOW]
If HW cursor is requested, typically by a fullscreen game, do not
enable SubVP so that up to 256x
From: Taimur Hassan
- Move SPL to a new path
- Request HW cursor on DCN3.2 with SubVP
- Allow reuse of of DCN4x code
- Enable odm 4:1 when debug key is set
- Fix seamless boot sequence
- Support multiple options during psr entry.
- Revert "Exit idle optimizations before attempt to access PHY"
- F
On Tue, Jan 28, 2025 at 03:29:27PM +0100, Philipp Stanner wrote:
> drm_sched_init() has a great many parameters and upcoming new
> functionality for the scheduler might add even more. Generally, the
> great number of parameters reduces readability and has already caused
> one missnaming in:
>
> co
On 1/28/2025 9:01 PM, Alex Deucher wrote:
> On Tue, Jan 28, 2025 at 1:42 AM Lijo Lazar wrote:
>>
>> IP tables with version <=2 may use harvest bit. For version 3 and above,
>> harvest bit is not applicable, instead uses harvest table. Fix the
>> logic accordingly.
>>
>> Signed-off-by: Lijo Laza
On 2025-01-27 19:41, Melissa Wen wrote:
> This restores the original behavior that gets min/max freq from EDID and
> only set DP/eDP connector as freesync capable if "sink device is capable
> of rendering incoming video stream without MSA timing parameters", i.e.,
> `allow_invalid_MSA_timing_par
Can you try the attached patch (with no other patches applied)? I
think it should fix the issue.
Alex
On Sat, Jan 25, 2025 at 1:38 PM Marco Moock wrote:
>
> Am 24.01.2025 um 16:40:37 Uhr schrieb Alex Deucher:
>
> > On Fri, Jan 24, 2025 at 9:17 AM Marco Moock wrote:
> > >
> > > Am 20.01.2025 um
Another potential better patch to try.
Alex
On Tue, Jan 28, 2025 at 10:07 AM Alex Deucher wrote:
>
> Can you try the attached patch (with no other patches applied)? I
> think it should fix the issue.
>
> Alex
>
> On Sat, Jan 25, 2025 at 1:38 PM Marco Moock wrote:
> >
> > Am 24.01.2025 um 16:40
On 1/28/2025 7:55 PM, Sundararaju, Sathishkumar wrote:
On 1/28/2025 5:29 PM, Lazar, Lijo wrote:
On 1/28/2025 5:06 PM, Sundararaju, Sathishkumar wrote:
Hi Lijo,
On 1/28/2025 3:04 PM, Lazar, Lijo wrote:
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
Add devcoredump helper functions that
Applied. Thanks!
Alex
On Tue, Jan 28, 2025 at 10:03 AM Harry Wentland wrote:
>
>
>
> On 2025-01-27 19:41, Melissa Wen wrote:
> > This restores the original behavior that gets min/max freq from EDID and
> > only set DP/eDP connector as freesync capable if "sink device is capable
> > of rendering
On Tue, Jan 28, 2025 at 1:42 AM Lijo Lazar wrote:
>
> IP tables with version <=2 may use harvest bit. For version 3 and above,
> harvest bit is not applicable, instead uses harvest table. Fix the
> logic accordingly.
>
> Signed-off-by: Lijo Lazar
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discove
On 1/28/2025 5:29 PM, Lazar, Lijo wrote:
On 1/28/2025 5:06 PM, Sundararaju, Sathishkumar wrote:
Hi Lijo,
On 1/28/2025 3:04 PM, Lazar, Lijo wrote:
On 1/28/2025 2:39 PM, Sathishkumar S wrote:
Add devcoredump helper functions that can be reused for all jpeg
versions.
Signed-off-by: Sathis
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("drm/nouveau: Improve variable name in
nouveau_sched_init
On Mon, Jan 27, 2025 at 12:23:28PM +0200, Pekka Paalanen wrote:
> On Wed, 22 Jan 2025 07:22:25 +0200
> Raag Jadav wrote:
>
> > On Tue, Jan 21, 2025 at 02:14:56AM +0100, Xaver Hugl wrote:
> > > > +It is the responsibility of the consumer to make sure that the device
> > > > or
> > > > +its resour
On Tue, Jan 28, 2025 at 03:29:27PM +0100, Philipp Stanner wrote:
> drm_sched_init() has a great many parameters and upcoming new
> functionality for the scheduler might add even more. Generally, the
> great number of parameters reduces readability and has already caused
> one missnaming in:
>
> co
On 1/28/2025 13:16, Lancelot SIX wrote:
It is possible for some waves in a workgroup to finish their save
sequence before the group leader has had time to capture the workgroup
barrier state. When this happens, having those waves exit do impact the
barrier state. As a consequence, the state cap
52 matches
Mail list logo
