> 2025年1月14日 06:27，Mario Limonciello 写道：
>
> On 1/12/2025 19:42, Jiang Liu wrote:
>> Make the device state machine work in stack like way to better support
>> suspend/resume by following changes:
>> 1. amdgpu_driver_load_kms()
>> amdgpu_device_init()
>> amdgpu_device_ip_early
> 2025年1月11日 02:57，Mario Limonciello 写道：
>
> On 1/9/2025 20:08, Jiang Liu wrote:
>> Clear adev->in_suspend flag when fails to suspend, otherwise it will
>> cause too much warnings like:
>> [ 1802.212027] [ cut here ]
>> [ 1802.212028] WARNING: CPU: 97 PID: 11282 at
>>
On 1/12/2025 19:19, Gerry Liu wrote:
2025年1月10日 01:10，Mario Limonciello 写道：
General note - don't use HTML for mailing list communication.
I'm not sure if Apple Mail lets you switch this around.
If not, you might try using Thunderbird instead. You can pick to reply in plain text or
HTML b
From: Josip Pavic
[Why]
Knowing the destination of OTG's vertical interrupt 2 is useful for
debugging, but it is not currently included in the OTG state readback
logic
[How]
Read the OTG interrupt destination register to get the vertical interrupt
2 destination on ASICs that have this register w
From: Yan Li
[WHY]
The source device outputs a full RGB signal, but TV may
be set to use limited RGB. The mismatch in color
range leads to a degradation in image quality.
Display driver should have the ability to switch
between the full and limited RGB to match TV's settings.
[HOW]
Add support o
From: Ian Chen
Add SDP programming for UHB link as well.
Reviewed-by: Wenjing Liu
Signed-off-by: Ian Chen
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dc
From: Dillon Varone
[WHY&HOW]
Address was not previously populated which can result in incorrect
clock frequencies being read on boot.
Reviewed-by: Alvin Lee
Signed-off-by: Dillon Varone
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 ++
drive
From: Aric Cyr
This version brings along following fixes:
- Reverse the visual confirm recouts
- Exclude clkoffset and ips setting for dcn351 specific
- Fix cursor programming problems
- Increase block_sequence array size
- Use Nominal vBlank to determine vstartup if Provided
- Fix clock frequen
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
- Reverse the visual confirm recouts
- Exclude clkoffset and ips setting for dcn351 specific
- Fix cursor programming problems
- Increase block_sequence array size
- Use Nominal vBlank to determine vstartup if Provi
From: Joshua Aberback
[Why]
It's possible to generate more than 50 steps in hwss_build_fast_sequence,
for example with a 6-pipe asic where all pipes are in one MPC chain. This
overflows the block_sequence buffer and corrupts block_sequence_steps,
causing a crash.
[How]
Expand block_sequence to 1
From: Peterson Guo
[WHY]
When checking if a pipe can disable cursor to prevent duplicate cursors,
having visual confirm on will prevent disabling cursors on planes which
cover the bottom of the screen.
[HOW]
When checking if a plane can disable visual confirm, the pipe first
reverses these calcu
From: Aric Cyr
[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.
[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if ther
From: Aric Cyr
[Why]
When HUBP is power gated, the SW state can get out of sync with the
hardware state causing cursor to not be programmed correctly.
[How]
Similar to DPP, add a HUBP reset function which is called wherever
HUBP is initialized or powergated. This function will clear the cursor
From: Austin Zheng
[Why/How]
vBlank used to determine the max vStartup is based on the smallest between
the vblank provided by the timing and vblank in ip_caps.
Extra vblank time is not considered if the vblank provided by the timing ends
up being higher than what's defined by the ip_caps
Use 1
From: Charlene Liu
Exclude clock offset and IPS setting for dcn351 specific only.
Reviewed-by: Syed Hassan
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Charlene Liu
Signed-off-by: Wayne Lin
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 4 ++--
1 file changed, 2 inser
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Tuesday, January 14, 2025 01:08
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu: cache gpu pcie link width
Ping on this
[AMD Official Use Only - AMD Internal Distribution Only]
Ping ...
-Original Message-
From: jesse.zh...@amd.com
Sent: Friday, January 10, 2025 1:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Huang, Tim ; Zhu, Jiadong
; Zhang, Jesse(Jie) ; Zhang,
J
Commit c6a837088bed ("drm/amd/display: Fetch the EDID from _DDC if
available for eDP") added function dm_helpers_probe_acpi_edid, which
fetches the EDID from the BIOS by calling acpi_video_get_edid.
acpi_video_get_edid returns a pointer to the EDID, but this pointer does
not originate from kmalloc
From: "Dr. David Alan Gilbert"
kfd_device_by_pci_dev(), kfd_get_pasid_limit() and kfd_set_pasid_limit()
have been unused since 2023's
commit c99a2e7ae291 ("drm/amdkfd: drop IOMMUv2 support")
Remove them.
Signed-off-by: Dr. David Alan Gilbert
---
drivers/gpu/drm/amd/amdkfd/kfd_pasid.c| 24
Reviewed-by: Simon Ser
This patch should probably come after all patches introducing the
properties referenced in the docs, e.g. NEXT and COLOR_PIPELINE.
Probably after "[13/45] drm/colorop: Introduce
DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE"?
> +/**
> + * DOC: overview
> + *
> + * A colorop represents a single color operati
Reviewed-by: Simon Ser
Reviewed-by: Simon Ser
On Fri, 10 Jan 2025, "Emil J Tywoniak" wrote:
> What's up gamers,
>
> hope this is the right place to report this oops which possibly is due
> to amdgpu interaction. The community guidelines link for this list
> (https://01.org/linuxgraphics/community) doesn't work. Feel free to
> redirect me if n
This commit enables the cleaner shader feature for GFX12.0 and GFX12.0.1
GPUs. The cleaner shader is important for clearing GPU resources such as
Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and
Scalar General Purpose Registers (SGPRs) between workloads.
- This feature ensures
Ping on this series?
Alex
On Tue, Jan 7, 2025 at 11:17 AM Alex Deucher wrote:
>
> Get the PCIe link with of the device itself (or it's
> integrated upstream bridge) and cache that.
>
> v2: fix typo
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3820
> Signed-off-by: Alex Deucher
> --
On Mon, Jan 13, 2025 at 4:59 PM Mario Limonciello
wrote:
>
> On 1/13/2025 08:19, Mario Limonciello wrote:
> > On 1/11/2025 12:59, Chris Bainbridge wrote:
> >> Commit c6a837088bed ("drm/amd/display: Fetch the EDID from _DDC if
> >> available for eDP") added function dm_helpers_probe_acpi_edid, whic
On 1/12/2025 19:42, Jiang Liu wrote:
Make the device state machine work in stack like way to better support
suspend/resume by following changes:
1. amdgpu_driver_load_kms()
amdgpu_device_init()
amdgpu_device_ip_early_init()
ip_blocks[i].early_init(
On 1/12/2025 19:42, Jiang Liu wrote:
Walk IP blocks in reverse order in function amdgpu_device_ip_fini_early
and amdgpu_device_smu_fini_early, to keep consistence with other finish
functions.
Signed-off-by: Jiang Liu
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_devi
On 1/12/2025 8:02 PM, Deng, Emily wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Chen, Xiaogang
Sent: Saturday, January 11, 2025 2:13 AM
To: Yang, Philip ; Deng, Emily ;
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v4] drm/amdkfd: Fix pa
> +int
> +drm_atomic_add_affected_colorops(struct drm_atomic_state *state,
> + struct drm_plane *plane)
> +{
> + struct drm_colorop *colorop;
> + struct drm_colorop_state *colorop_state;
> +
> + WARN_ON(!drm_atomic_get_new_plane_state(state, plane));
> +
> +
Two nits below, regardless:
Reviewed-by: Simon Ser
> +static int drm_colorop_create_data_prop(struct drm_device *dev, struct
> drm_colorop *colorop)
> +{
> + struct drm_property *prop;
> +
> + /* data */
> + prop = drm_property_create(dev, DRM_MODE_PROP_ATOMIC |
> DRM_MODE_PROP_BLO
> v4:
> - Don't block setting of COLOR_RANGE and COLOR_ENCODING
>when client cap is set
Can you remind me why these should not be blocked?
We should also add doc comments in the color_range and color_encoding fields,
to document that drivers should ignore these fields when the cap is set.
On 1/11/2025 12:59, Chris Bainbridge wrote:
Commit c6a837088bed ("drm/amd/display: Fetch the EDID from _DDC if
available for eDP") added function dm_helpers_probe_acpi_edid, which
fetches the EDID from the BIOS by calling acpi_video_get_edid.
acpi_video_get_edid returns a pointer to the EDID, but
Hi,
On 11-Jan-25 7:59 PM, Chris Bainbridge wrote:
> Commit c6a837088bed ("drm/amd/display: Fetch the EDID from _DDC if
> available for eDP") added function dm_helpers_probe_acpi_edid, which
> fetches the EDID from the BIOS by calling acpi_video_get_edid.
> acpi_video_get_edid returns a pointer to
On 1/13/2025 08:19, Mario Limonciello wrote:
On 1/11/2025 12:59, Chris Bainbridge wrote:
Commit c6a837088bed ("drm/amd/display: Fetch the EDID from _DDC if
available for eDP") added function dm_helpers_probe_acpi_edid, which
fetches the EDID from the BIOS by calling acpi_video_get_edid.
acpi_vid
On 2025-01-11 02:03, Tiezhu Yang wrote:
> On 01/11/2025 05:45 AM, Harry Wentland wrote:
>> On 2025-01-06 03:57, Tiezhu Yang wrote:
>>> As far as I can tell, with the current existing macro definitions, there
>>> is no better way to do the minimal and proper changes to stop the control
>>> flow i
The following page fault was observed during the exit moment of the
HIP test process. In this particular error case, the HIP test
(./MemcpyPerformance -h) does not require the AQL queue. As a result,
the process_context_addr was not assigned when the KFD process was
released, ultimately leading to
There is a comilation error after merging:
commit id : 7de7cafeb474d1454b1744c9a51eac4c8a6ed29a
Signed-off-by: Saleemkhan Jamadar
Reviewed-by: Arvind Yadav
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/am
On Fri, Jan 10, 2025 at 10:40 PM Lazar, Lijo wrote:
>
>
>
> On 1/10/2025 8:33 PM, Alex Deucher wrote:
> > On Thu, Jan 9, 2025 at 10:30 PM Lazar, Lijo wrote:
> >>
> >>
> >>
> >> On 1/9/2025 10:36 PM, Alex Deucher wrote:
> >>> On Thu, Jan 9, 2025 at 12:59 AM Lazar, Lijo wrote:
>
>
>
Reviewed-by: Simon Ser
> +void drm_colorop_set_next_property(struct drm_colorop *colorop, struct
> drm_colorop *next)
> +{
> + if (!colorop->next_property)
> + return;
Why is this early return necessary? Shouldn't this field be always
populated?
Even if that's not the case, I don't think silently ignor
> +static void drm_atomic_colorop_print_state(struct drm_printer *p,
> + const struct drm_colorop_state *state)
> +{
> + struct drm_colorop *colorop = state->colorop;
> +
> + drm_printf(p, "colorop[%u]:\n", colorop->base.id);
> + drm_printf(p, "\ttype=%s\n", drm_get_colorop_
Applied. Thanks!
Alex
On Sun, Jan 12, 2025 at 9:39 AM wrote:
>
> From: "Dr. David Alan Gilbert"
>
> kfd_device_by_pci_dev(), kfd_get_pasid_limit() and kfd_set_pasid_limit()
> have been unused since 2023's
> commit c99a2e7ae291 ("drm/amdkfd: drop IOMMUv2 support")
>
> Remove them.
>
> Signed-of
On Mon, Jan 13, 2025 at 12:32 PM Srinivasan Shanmugam
wrote:
>
> This commit enables the cleaner shader feature for GFX12.0 and GFX12.0.1
> GPUs. The cleaner shader is important for clearing GPU resources such as
> Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and
> Scalar Gene
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