On Sun, 01 Dec 2024, Dmitry Baryshkov wrote:
> Reading access to connector->eld can happen at the same time the
> drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
> order to protect connector->eld from concurrent access.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Jani
[Public]
> From: Tvrtko Ursulin
> Sent: Tuesday, December 3, 2024 9:42
> On 28/11/2024 18:54, Yunxiang Li wrote:
> > Before, every time fdinfo is queried we try to lock all the BOs in the
> > VM and calculate memory usage from scratch. This works okay if the
> > fdinfo is rarely read and the VMs
Am 03.12.24 um 15:24 schrieb Oleksandr Natalenko:
On středa 13. listopadu 2024 14:48:38, středoevropský standardní čas Tvrtko
Ursulin wrote:
From: Tvrtko Ursulin
As commit 746ae46c1113 ("drm/sched: Mark scheduler work queues with
WQ_MEM_RECLAIM")
points out, ever since
a6149f039369 ("drm/sch
[Public]
> From: Tvrtko Ursulin
> Sent: Tuesday, December 3, 2024 10:16
> On 03/12/2024 15:03, Li, Yunxiang (Teddy) wrote:
> > [Public]
> >
> >> From: Tvrtko Ursulin
> >> Sent: Tuesday, December 3, 2024 9:42
> >> On 28/11/2024 18:54, Yunxiang Li wrote:
> >>> Before, every time fdinfo is queried
On 11/28/2024 2:17 PM, Felix Kuehling wrote:
On 2024-11-25 10:39, Xiaogang.Chen wrote:
From: Xiaogang Chen
Current kfd driver has its own PASID value for a kfd process and uses
it to
locate vm at interrupt handler or mapping between kfd process and vm.
That
design is not working when a p
Am 03.12.24 um 06:00 schrieb Raag Jadav:
On Mon, Dec 02, 2024 at 10:07:59AM +0200, Raag Jadav wrote:
On Fri, Nov 29, 2024 at 10:40:14AM -0300, André Almeida wrote:
Hi Raag,
Em 28/11/2024 12:37, Raag Jadav escreveu:
Introduce device wedged event, which notifies userspace of 'wedged'
(hanged/un
On Mon, Dec 02, 2024 at 07:27:45PM -0800, Abhinav Kumar wrote:
>
>
> On 11/30/2024 3:55 PM, Dmitry Baryshkov wrote:
> > Reading access to connector->eld can happen at the same time the
> > drm_edid_to_eld() updates the data. Take the newly added eld_mutex in
> > order to protect connector->eld fr
[Public]
From: amd-gfx on behalf of Andrew
Martin
Sent: Monday, December 2, 2024 7:45:55 a.m.
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix ; Tudor, Alexandru
; Martin, Andrew ; Martin,
Andrew
Subject: [PATCH v2] drm/amdkfd: Dereference null return
Pull out some duplicated dereference chains into variables, and in some
cases grab struct device pointer directly from amdgpu_device instead of
via drm_device.
Signed-off-by: Yunxiang Li
Reviewed-by: Mukul Joshi
---
v3: no change
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 29 --
When using MES creating a pdd will require talking to the GPU to setup
the relevant context. The code here forgot to wake up the GPU in case it
was in suspend, this causes KVM to EFAULT for passthrough GPU for
example. This issue can be masked if the GPU was woken up by other
things (e.g. opening t
On Mon, Dec 02, 2024 at 10:07:59AM +0200, Raag Jadav wrote:
> On Fri, Nov 29, 2024 at 10:40:14AM -0300, André Almeida wrote:
> > Hi Raag,
> >
> > Em 28/11/2024 12:37, Raag Jadav escreveu:
> > > Introduce device wedged event, which notifies userspace of 'wedged'
> > > (hanged/unusable) state of the
From: Le Ma
add sdma444 basic support
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 2 ++
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 ++
3 files chang
From: Alex Sierra
Same as IH 4.4.2.
Signed-off-by: Alex Sierra
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
in
On Tue, Dec 3, 2024 at 1:14 PM Mario Limonciello
wrote:
>
> Some of the firmware that is loaded by amdgpu is not actually required.
> For example the ISP firmware on some SoCs is optional, and if it's not
> present the ISP IP block just won't be initialized.
>
> The firmware loader core however wi
On 12/3/2024 15:34, Alex Deucher wrote:
On Tue, Dec 3, 2024 at 1:14 PM Mario Limonciello
wrote:
Some of the firmware that is loaded by amdgpu is not actually required.
For example the ISP firmware on some SoCs is optional, and if it's not
present the ISP IP block just won't be initialized.
Th
From: Karthi Kandasamy
[Why]
Expose DCN401 HUBP functions for use across other platforms.
[Description]
This change aims to make the DCN401 HUBP functions accessible for
enabling their use in future platform developments.
Reviewed-by: Alvin Lee
Signed-off-by: Karthi Kandasamy
Signed-off-by: A
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fix some regressions related to IPS2 and PSR Panel Replay
* Bug fixes in DML
* DMCUB debug improvements
* Other refactors and improvements across multiple components
Cc: Daniel Wheeler
___
From: Joshua Aberback
[Why]
We want to avoid unnecessary asserts, one of which is hit in
dcn31_panel_construct when booting on a DCN32 asic that has an eDP
connector on a different DIG than A or B. The DIG-based mapping only
applies when edp0_on_dp1 is supported, therefore the check for valid
eng
From: Austin Zheng
[Why/How]
Mismatch between mode support and mode programming occurs.
Mode support would calculate higher row vblank than mode programming.
As a result, mode programming fails and hardware isn't properly programmed.
Reviewed-by: Dillon Varone
Signed-off-by: Austin Zheng
Signe
From: Samson Tam
[Why & How]
Add check for invalid pixel format, remove unused pixel formats
and clean up some names
Reviewed-by: Navid Assadian
Signed-off-by: Samson Tam
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/dc_spl_translate.c | 9 ++-
drivers/gpu/drm/amd/display/d
From: Harry VanZyllDeJong
[HOW&WHY]
Stores DMUB support for enablement of Varibright over VABC in DCN32
Reviewed-by: Aric Cyr
Reviewed-by: Iswara Nagulendran
Signed-off-by: Harry VanZyllDeJong
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 +
From: Ausef Yousof
[WHY]
Right now in dml2 mode validation we are calculating UBF parameters for
prefetch calculation for single and dual DPP scenarios. Data structure
to store such values are just 1D arrays, the single DPP values are
overwritten by the dualDPP values, and we end up using dualDPP
From: Wayne Lin
[Why]
Variables relates to secure display are spreading out within struct
amdgpu_display_manager.
[How]
Encapsulate relevant variables into struct secure_display_context and
adjust relevant affected codes.
Reviewed-by: HaoPing Liu
Signed-off-by: Wayne Lin
Signed-off-by: Aurabi
From: Leo Li
[Why]
Previously, the debugfs did a simple dump of the tracebuffer region.
Because the tracebuffer is a ring, it meant that the entries printed may
not be in chronological order if the ring rolled over. This makes
parsing the tracelog cumbersome.
[How]
Since dmcub provides the cur
From: Peterson
[WHY]
When using upscaling on certain gpus, some incorrect scaling
calculations would be made causing hangs.
[HOW]
This was fixed by using the resource_build_scaling_params function on these
gpus.
Reviewed-by: Dillon Varone
Reviewed-by: Alvin Lee
Signed-off-by: Peterson Guo
Si
From: Zhongwei
[Why/How]
The force_ffu_mode flag could be initialized at other place.
Reviewed-by: Robin Chen
Signed-off-by: Zhongwei
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/driver
From: Wayne Lin
[Why]
For mst streams under same topology, stream->link->link_enc_hw_inst are the
same and
hence can't distinguish the crc window setting.
[How]
Firstly adjust dc_stream_forward_crc_window to accept assignment of phy_id.
Follow up
another patch to determine the phy_id at dm lay
From: Nicholas Kazlauskas
This reverts commit 4ac57a450da3.
In some test environments causes reporting failures for S0i3/S4.
It shouldn't actually block entry provided there's no race with the
last state being updated, but currently suspecting there's an IPS2
check that's no longer being met.
From: Taimur Hassan
Signed-off-by: Taimur Hassan
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 154 --
1 file changed, 103 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/d
From: Aric Cyr
* Fix some regressions related to IPS2 and PSR Panel Replay
* Bug fixes in DML
* DMCUB debug improvements
* Other refactors and improvements across multiple components
Signed-off-by: Aric Cyr
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file
From: Gabe Teeger
This reverts commit 69e9ce2a572b
Due to a replay regression.
Fixes: 69e9ce2a572b ("drm/amd/display: Revised for Replay Pseudo vblank
control")
Reviewed-by: Dennis Chan
Signed-off-by: Gabe Teeger
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc_types.h
From: Charlene Liu
[why]
hw register offset delta
Signed-off-by: Charlene Liu
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 2 +-
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 5 +-
.../display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c | 140 +++
From: Wayne Lin
[Why]
Under mst scenario, mst streams are from the same link_enc_hw_inst.
As the result, can't utilize that as the phy index for distinguising
different stream sinks.
[How]
Sort the connectors by:
link_enc_hw_instance->mst tree depth->mst RAD
After sorting the phy index assignme
From: Nicholas Kazlauskas
[Why]
The synthetic policy overrides the policy we already ran to formulate
this in dcn35_clk_mgr and causes some levels to be dropped along with
FCLK being lower than what can actually being supported per state.
[How]
Just copy in_states to out_states, the synthetic po
On 11/15/2024 00:09, Mario Limonciello wrote:
When a DMUB load failure occurs the amdgpu driver is left in a pretty
bad state because the display core thinks everything is fine.
This explodes once the core tries to do a register read which stalls.
Instead of papering over these errors return er
From: Chris Park
[Why]
DMColor inaccurately updates color space, bias and scale
destructively in dc_plane_state. This can be resolved by
accurately populating the infos on dc_plane_info where then
translation to plane state can happen as a whole surface update sequence.
[How]
Remove dc_plane_st
The SVM DMA device map direction should be set the same as
the DMA unmap setting, otherwise the DMA core will report
the following warning.
Before finialize this solution, there're some discussion on
the DMA mapping type(stream-based or coherent) in this KFD
migration case, followed by https://lor
Set the default workload type to bootup type on smu v13.0.7.
This is because of the constraint on smu v13.0.7.
Gfx activity has an even higher set point on 3D fullscreen
mode than the one on bootup mode. This causes the 3D fullscreen
mode's performance is worse than the bootup mode's performance
fo
On 12/4/2024 12:33 PM, Kenneth Feng wrote:
> Set the default workload type to bootup type on smu v13.0.7.
> This is because of the constraint on smu v13.0.7.
> Gfx activity has an even higher set point on 3D fullscreen
> mode than the one on bootup mode. This causes the 3D fullscreen
> mode's per
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Sima, Christian,
I would like to rediscuss about p2p in guest VM, can you please take a look.
Thanks.
Best regards,
Julia
From: Zhang, Julia
Sent: Friday, November 29, 2024 3:52 PM
To: Koenig, Christian ; Zhang, Julia
; Gurchetan Si
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: Kenneth Feng
Sent: Wednesday, December 4, 2024 3:04 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) ; Feng, Kenneth
Subject: [PATCH] drm/amd/pm: set
+enum amdgpu_ucode_required {
+ AMDGPU_UCODE_NOT_REQUIRED,
+ AMDGPU_UCODE_REQUIRED,
Couldn't this be handled in another API instead of having to flag every
load? By default, every ucode is required and if optional may be skipped
with amdgpu_ucode_request_optional() API?
I guess
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, December 4, 2024 9:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad
Subject: [PATC
Some boards use longer File Ids.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h
index bc58dca18035..9
From: Xiaogang Chen
Current kfd driver has its own PASID value for a kfd process and uses it to
locate vm at interrupt handler or mapping between kfd process and vm. That
design is not working when a physical gpu device has multiple spatial
partitions, ex: adev in CPX mode. This patch has kfd dri
> diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
> index
> d17c473c1ef292875475bf3bdf62d07241c13882..d713a6445a6267145a7014f308d
> f3bb25b8c3287 100644
> --- a/include/linux/sysfs.h
> +++ b/include/linux/sysfs.h
> @@ -305,8 +305,12 @@ struct bin_attribute {
> struct address_space
Some of the firmware that is loaded by amdgpu is not actually required.
For example the ISP firmware on some SoCs is optional, and if it's not
present the ISP IP block just won't be initialized.
The firmware loader core however will show a warning when this happens
like this:
```
Direct firmware l
On 12/3/2024 11:44 PM, Mario Limonciello wrote:
> Some of the firmware that is loaded by amdgpu is not actually required.
> For example the ISP firmware on some SoCs is optional, and if it's not
> present the ISP IP block just won't be initialized.
>
> The firmware loader core however will show
I have an ASUS Zenbook S 16 (UM5606WA) and I noticed that the display
brightness control stopped working after upgrading to kernel
v6.13-rc1.
After reverting the changes from the following commits, brightness
control started working again:
- 7875afafba84817b791be6d2282b836695146060
- 38077562e05
On 2024-12-03 11:06:16-0500, James Bottomley wrote:
> > diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
> > index
> > d17c473c1ef292875475bf3bdf62d07241c13882..d713a6445a6267145a7014f308d
> > f3bb25b8c3287 100644
> > --- a/include/linux/sysfs.h
> > +++ b/include/linux/sysfs.h
> > @@ -305
On 12/4/2024 10:44 AM, Mario Limonciello wrote:
>
>>> +enum amdgpu_ucode_required {
>>> + AMDGPU_UCODE_NOT_REQUIRED,
>>> + AMDGPU_UCODE_REQUIRED,
>>
>> Couldn't this be handled in another API instead of having to flag every
>> load? By default, every ucode is required and if optional may
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