Hi Jiqian,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.12-rc6 next-20241105]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
Am 05.11.24 um 03:33 schrieb Prike Liang:
The SVM DMA device unmap direction should be same as
the DMA map process.
At least of hand that looks like it's only papering over a major problem.
Why are DMA ranges for SVM mapped with a direction in the first place?
That is usually not something we
Add sysfs node to show supported NPS mode for the
partition configuration selected using xcp_config
v2: Hide node if dynamic nps switch not supported
v3: Fix removal of files in case of error
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 48 ++
Am 05.11.24 um 07:05 schrieb Jiqian Chen:
VPCI of Xen doesn't support resizable bar. When discrete GPU is used on
PVH dom0 which using the VPCI, amdgpu fails to probe, so we need to
disable this capability for PVH dom0.
What do you mean VPCI doesn't support resizeable BAR?
This is mandatory to
On 31/10/2024 19:04, Alex Deucher wrote:
This builds on the patches from Lu and Jocelyn to fill in
panic support for all DCE/DCN variants and code pathes.
v2: refactor to provide cleaner history and share more
code to provide a more consistent experience across
DC and non-DC.
I wasn't able to
Am Mo., 28. Okt. 2024 um 16:18 Uhr schrieb Matias N. Goldberg
:
>
> SENDING AGAIN because it was sent with HTML formatting, which screwed up the
> email.
>
>
> Hi!
>
> This is my first patch ever to DRM/amdgpu (technically I didn't write the
> patch, I just kept rebasing it over 4 years, and did
On Tue, Nov 5, 2024 at 8:59 AM Jocelyn Falempe wrote:
>
> On 31/10/2024 19:04, Alex Deucher wrote:
> > This builds on the patches from Lu and Jocelyn to fill in
> > panic support for all DCE/DCN variants and code pathes.
> >
> > v2: refactor to provide cleaner history and share more
> > code to pr
Pull this out of Jocelyn's patch and make it generic.
Signed-off-by: Alex Deucher
Cc: Lu Yao
Cc: Jocelyn Falempe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 80 +
drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 5 ++
2 files changed, 85 insertions(+)
diff --git a/driv
This builds on the patches from Lu and Jocelyn to fill in
panic support for all DCE/DCN variants and code pathes.
v2: refactor to provide cleaner history and share more
code to provide a more consistent experience across
DC and non-DC.
v3: resend with the missing first patch
Alex Deucher (4):
This adds clear_tiling callbacks to the hubp structure that
will be used for drm panic support to clear the tiling on
a display. hubp3 support from Jocelyn's original patch
and the rest from me.
Signed-off-by: Alex Deucher
Cc: Lu Yao
Cc: Jocelyn Falempe
---
.../drm/amd/display/dc/hubp/dcn10/d
Add support for the drm_panic module, which displays a pretty user
friendly message on the screen when a Linux kernel panic occurs.
Adapt Lu Yao's code to use common helpers derived from
Jocelyn's patch. This extends the non-DC code to enable
access to non-CPU accessible VRAM and adds support for
This adds clear_tiling callbacks to the mi structure that
will be used for drm panic support to clear the tiling on
a display. Mem input (mi) is used on DCE based display
IPs.
Signed-off-by: Alex Deucher
Cc: Lu Yao
Cc: Jocelyn Falempe
---
.../drm/amd/display/dc/dce/dce_mem_input.c| 34 +++
From: Jocelyn Falempe
Add support for the drm_panic module, which displays a pretty user
friendly message on the screen when a Linux kernel panic occurs.
It doesn't work yet on laptop panels, maybe due to PSR.
Adapted from Jocelyn's original patch to add DC drm_panic
support.
Signed-off-by: Jo
The SRIOV PF/VF Data exchange is extended by 64KB for VF RAS Telemetry data.
Add Host RAS Telemetry enable capabilities bitfields.
Add a new VF msg REQ_RAS_ERROR_COUNT, the host response data will be populated
in the RAS Telemetry region.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/a
On Tue, Nov 5, 2024 at 4:39 AM Chong Li wrote:
>
> The currect code use the address "adev->mes.read_val_ptr" to
> store the value read from register via mes.
> So when multiple threads read register,
> multiple threads have to share the one address,
> and overwrite the value each other.
>
> Assign
If VF RAS Capability support is enabled, guest is able to
retrieve the real RAS support from the host.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 53
drivers/gpu/drm/amd/amdgpu/amdgpu_
Enable RAS late init if VF RAS Telemetry is supported.
When enabled, the VF can use this interface to query total
RAS error counts from the host.
The VF FB access may abruptly end due to a fatal error,
therefore the VF must cache and sanitize the input.
The Host allows 15 Telemetry messages eve
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c| 16 ++--
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h| 2 ++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Kamal, Asad
Sent: Tuesday, November 5, 2024 20:34
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo ; Zhang,
Hawking
Cc: Ma, Le ; Zhang, Morris ; Kamal, Asad
;
On Sun, Nov 03, 2024 at 05:03:31PM +, Thomas Weißschuh wrote:
> Several drivers need to dynamically calculate the size of an binary
> attribute. Currently this is done by assigning attr->size from the
> is_bin_visible() callback.
s/an binary/a binary/
> This has drawbacks:
> * It is not docum
On Sun, Nov 03, 2024 at 05:03:29PM +, Thomas Weißschuh wrote:
> struct bin_attribute contains a bunch of pointer members, which when
> overwritten by accident or malice can lead to system instability and
> security problems.
> Moving the definitions of struct bin_attribute to read-only memory
>
Am 05.11.24 um 03:48 schrieb Chong Li:
The currect code use the address "adev->mes.read_val_ptr" to
store the value read from register via mes.
So when multiple threads read register,
multiple threads have to share the one address,
and overwrite the value each other.
Assign an address by "amdgpu
On 11/5/2024 4:43 AM, Felix Kuehling wrote:
> On 2024-10-31 22:15, Zhu Lingshan wrote:
>> On 10/31/2024 11:27 PM, Felix Kuehling wrote:
>>> On 2024-10-31 6:47, Zhu Lingshan wrote:
The header usr/linux/kfd_ioctl.h is a duplicate of uapi/linux/kfd_ioctl.h.
>>> I don't see usr/linux/kfd_ioctl.h.
On Tue, 29. Oct 18:12, Fedor Pchelkin wrote:
> On Tue, 29. Oct 10:20, Sasha Levin wrote:
> > On Tue, Oct 29, 2024 at 04:31:40PM +0300, Fedor Pchelkin wrote:
> > > BTW, a question to the stable-team: what Git magic (3-way-merge?) let the
> > > duplicate patch be applied successfully? The patch conte
On Mon, Nov 04, 2024 at 05:55:28PM +0300, Fedor Pchelkin wrote:
> On Tue, 29. Oct 18:12, Fedor Pchelkin wrote:
> > On Tue, 29. Oct 10:20, Sasha Levin wrote:
> > > On Tue, Oct 29, 2024 at 04:31:40PM +0300, Fedor Pchelkin wrote:
> > > > BTW, a question to the stable-team: what Git magic (3-way-merge?
Am 05.11.24 um 10:24 schrieb Chong Li:
The currect code use the address "adev->mes.read_val_ptr" to
store the value read from register via mes.
So when multiple threads read register,
multiple threads have to share the one address,
and overwrite the value each other.
Assign an address by "amdgpu
> That's not a problem, incompatible options can just be rejected in atomic
> tests.
I was thinking from a user perspective. It'd be easier for user-space config
apps to present only the valid options, rather than offering all possible
combinations only to reject them after the user selected an
On Sun, Nov 03, 2024 at 05:03:34PM +, Thomas Weißschuh wrote:
> The is_bin_visible() callbacks should not modify the struct
> bin_attribute passed as argument.
> Enforce this by marking the argument as const.
>
> As there are not many callback implementers perform this change
> throughout the
Hi Jiqian,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.12-rc6 next-20241105]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
On 2024-11-05 06:04, Christian König wrote:
Am 05.11.24 um 03:33 schrieb Prike Liang:
The SVM DMA device unmap direction should be same as
the DMA map process.
At least of hand that looks like it's only papering over a major problem.
Why are DMA ranges for SVM mapped with a direction in the f
[AMD Official Use Only - AMD Internal Distribution Only]
Hi, Christian.
the variable "addr_offset" need to initialize as 0,
since when function "amdgpu_device_wb_get" failed,
if "addr_offset" is not 0, function "amdgpu_device_wb_free" will free the wb.
I will do not initialize the variable "read
The currect code use the address "adev->mes.read_val_ptr" to
store the value read from register via mes.
So when multiple threads read register,
multiple threads have to share the one address,
and overwrite the value each other.
Assign an address by "amdgpu_device_wb_get" to store register value.
[AMD Official Use Only - AMD Internal Distribution Only]
Series is Reviewed-by: Le Ma
> -Original Message-
> From: Lazar, Lijo
> Sent: Tuesday, November 5, 2024 3:08 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Koenig, Christian ;
> Ma, Le
> Subj
On Mon Nov 4, 2024 at 12:52 PM PST, André Almeida wrote:
> Hi Christopher,
>
> Em 03/11/2024 03:36, Christopher Snowhill escreveu:
> > On Fri Nov 1, 2024 at 11:23 AM PDT, André Almeida wrote:
> >> Currently, DRM atomic uAPI allows only primary planes to be flipped
> >> asynchronously. However, each
On 11/5/2024 2:13 AM, Felix Kuehling wrote:
>
> On 2024-10-31 22:15, Zhu Lingshan wrote:
>> On 10/31/2024 11:27 PM, Felix Kuehling wrote:
>>> On 2024-10-31 6:47, Zhu Lingshan wrote:
The header usr/linux/kfd_ioctl.h is a duplicate of uapi/linux/kfd_ioctl.h.
>>> I don't see usr/linux/kfd_ioc
On Tue, 5 Nov 2024 at 10:15, Christopher Snowhill wrote:
>
> On Mon Nov 4, 2024 at 12:52 PM PST, André Almeida wrote:
> > Hi Christopher,
> >
> > Em 03/11/2024 03:36, Christopher Snowhill escreveu:
> > > On Fri Nov 1, 2024 at 11:23 AM PDT, André Almeida wrote:
> > >> Currently, DRM atomic uAPI all
Add sysfs node to show supported NPS mode for the
partition configuration selected using xcp_config
v2: Hide node if dynamic nps switch not supported
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 41 +
1 file changed, 41
On 11/5/2024 4:22 PM, Asad Kamal wrote:
> Add sysfs node to show supported NPS mode for the
> partition configuration selected using xcp_config
>
> v2: Hide node if dynamic nps switch not supported
>
> Signed-off-by: Asad Kamal
> Reviewed-by: Lijo Lazar
> ---
> drivers/gpu/drm/amd/amdgpu/am
GFX 12 does not require a page size cap for the trap handler because
it does not require a CWSR work around like GFX 11 did.
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
b/drive
[Public]
Instead of removing the check entirely, I think it should be changed to:
BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) > KFD_CWSR_TMA_OFFSET);
Like the pre-GFX11 cases. A cwsr trap handler too large will overwrite the
TMA area.
Regards,
David B.
> -Original Message-
> From: Kim, J
[Public]
Reviewed-by: David Belanger
> -Original Message-
> From: Kim, Jonathan
> Sent: Tuesday, November 5, 2024 1:46 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Belanger, David ; Kim, Jonathan
>
> Subject: [PATCH] drm/amdkfd: remove gfx 12 trap handler page size cap
>
> GFX 12 does
From: Tom Chung
[Why]
In certain use case such as KDE login screen, there will be no atomic
commit while do the frame update.
If the Panel Replay enabled, it will cause the screen not updated and
looks like system hang.
[How]
Delay few atomic commits before enabled the Panel Replay just like PSR
From: Austin Zheng
Number of taps is incorrectly being set when integer scaling is enabled.
Taps required when src_rect != dst_rect previously not considered.
Perform the calculations when integer scaling is enabled.
Set taps to 1 if the scaling ratio is 1:1.
Reviewed-by: Samson Tam
Signed-off-
From: JinZe Xu
[Why]
If driver allocated region6 size is not same as the size in firmware,
dmcub won't enable region6.
[How]
Use region6 size in dmcub_fw_meta instead of a constant value.
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: JinZe Xu
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/d
From: Tom Chung
Panel Replay feature may also use the same variable with PSR.
Change the variable name and make it not specify for PSR.
Reviewed-by: Leo Li
Signed-off-by: Tom Chung
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +--
.../gp
From: Emily Nie
[Why]
IGT displays Dmesg warnings which are likely false
[How]
Disabling p-state checks leading to this warning for DCN31 and DCN314
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Emily Nie
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23
From: Rodrigo Siqueira
This commit removes a legacy debug_defaults_diags struct.
Reviewed-by: Leo Li
Signed-off-by: Rodrigo Siqueira
Signed-off-by: Hamza Mahfooz
---
.../amd/display/dc/resource/dcn10/dcn10_resource.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/
From: Revalla Hari Krishna
[Why]
String literals must be assigned to const char pointers.
[How]
By adding const keyword to fix compilation errors.
Reviewed-by: Lohita Mudimela
Signed-off-by: Revalla Hari Krishna
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_
From: Meenakshikumar Somasundaram
[Why]
Need a flag to force MST blocked discovery for certain branch devices.
[How]
Added a flag to force MST blocked discovery in struct dc_panel_patch.
Reviewed-by: PeiChen Huang
Reviewed-by: Wenjing Liu
Signed-off-by: Meenakshikumar Somasundaram
Signed-off
From: Dillon Varone
If the nominal VBlank is too small, optimizing for stutter can cause
the prefetch bandwidth to increase drasticaly, resulting in higher
clock and power requirements. Only optimize if it is >3x the stutter
latency.
Cc: sta...@vger.kernel.org
Reviewed-by: Austin Zheng
Signed-o
Cc: Daniel Wheeler
Aric Cyr (1):
drm/amd/display: 3.2.309
Aurabindo Pillai (1):
drm/amd/display: Read DP tunneling support only for DPIA endpoints
Austin Zheng (1):
drm/amd/display: Update SPL Taps Required For Integer Scaling
Dillon Varone (1):
drm/amd/display: Require minimum VBlank
From: Leon Huang
[Why]
HPD error status does not cover Replay desync error status
while executing autotests and CTS tests.
[How]
Refactor the checking flow, reporting the HPD error based on
different eDP feature.
Reviewed-by: Robin Chen
Signed-off-by: Leon Huang
Signed-off-by: Hamza Mahfooz
From: Yihan Zhu
[Why]
No check on head pipe during the dml to dc hw mapping will allow illegal
pipe usage. This will result in a wrong pipe topology to cause mpcc tree
totally mess up then cause a display hang.
[How]
Avoid to use the pipe is head in all check and avoid ODM slice during
preferred
From: Aric Cyr
This version brings along the following:
- DML2 fixes
- DP fixes
- DPMS fix
- HPD fixes
- Misc cleanup
- ODM fix
- Replay fix
- SPL fix
Reviewed-by: Leo Li
Signed-off-by: Aric Cyr
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
.../amd/
From: Rodrigo Siqueira
At some point, the IEEE ID identification for the replay check in the
AMD EDID was added. However, this check causes the following
out-of-bounds issues when using KASAN:
[ 27.804016] BUG: KASAN: slab-out-of-bounds in
amdgpu_dm_update_freesync_caps+0xefa/0x17a0 [amdgpu]
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 +
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c| 16 ++--
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h| 2 ++
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
GFX 12 does not require a page size cap for the trap handler because
it does not require a CWSR work around like GFX 11 did.
v2: set default cap
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/
On 11/5/24 7:02 AM, Zicheng Qu wrote:
Hi all,
I am submitting two patches to correct power gating configurations in
the AMD display driver.
1. Patch 1/2 (Fixes: 46825fcfbe16): Corrects DOMAIN10_PG_CONFIG to use
DOMAIN10_POWER_FORCEON.
2. Patch 2/2 (Fixes: 46825fcfbe16): Corrects DOMAIN11_PG_
Enable RAS late init if VF RAS Telemetry is supported.
When enabled, the VF can use this interface to query total
RAS error counts from the host.
The VF FB access may abruptly end due to a fatal error,
therefore the VF must cache and sanitize the input.
The Host allows 15 Telemetry messages eve
The SRIOV PF/VF Data exchange is extended by 64KB for VF RAS Telemetry data.
Add Host RAS Telemetry enable capabilities bitfields.
Add a new VF msg REQ_RAS_ERROR_COUNT, the host response data will be populated
in the RAS Telemetry region.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/a
If VF RAS Capability support is enabled, guest is able to
retrieve the real RAS support from the host.
Signed-off-by: Victor Skvortsov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 53
drivers/gpu/drm/amd/amdgpu/amdgpu_
From: Fudongwang
Garbage will show due to dig is on. So blank stream needed.
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Fudongwang
Signed-off-by: Hamza Mahfooz
---
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c| 10 ++
1 file changed, 6 insert
From: Ryan Seto
[Why]
In the case where a dml allocation fails for any reason, the
current state's dml contexts would no longer be valid. Then
subsequent calls dc_state_copy_internal would shallow copy
invalid memory and if the new state was released, a double
free would occur.
[How]
Reset dml p
From: Aurabindo Pillai
Unconditionally reading DP tunneling support results in extraneous
errors messages on certain devices. Fix this by guarding the DPCD read
for DP tunneling support for USB4 DPIA endpoints.
Reviewed-by: Meenakshikumar Somasundaram
Signed-off-by: Aurabindo Pillai
Signed-off
On 05/11/2024 15:06, Alex Deucher wrote:
This builds on the patches from Lu and Jocelyn to fill in
panic support for all DCE/DCN variants and code pathes.
v2: refactor to provide cleaner history and share more
code to provide a more consistent experience across
DC and non-DC.
v3: resend with th
ping
On 10/28/2024 3:43 PM, Xiaogang.Chen wrote:
From: Xiaogang Chen
kfd process kref count(process->ref) is initialized to 1 by kref_init. After
it is created not need to increase its kref. Instad add kfd process kref at kfd
process mmu notifier allocation since we already decrease the kref a
On 2024-10-28 16:43, Xiaogang.Chen wrote:
From: Xiaogang Chen
kfd process kref count(process->ref) is initialized to 1 by kref_init. After
it is created not need to increase its kref. Instad add kfd process kref at kfd
process mmu notifier allocation since we already decrease the kref at
free
On 2024/11/5 21:42, Christian König wrote:
> Am 05.11.24 um 07:05 schrieb Jiqian Chen:
>> VPCI of Xen doesn't support resizable bar. When discrete GPU is used on
>> PVH dom0 which using the VPCI, amdgpu fails to probe, so we need to
>> disable this capability for PVH dom0.
>
> What do you mean VPC
On 2024-10-28 17:40, Xiaogang.Chen wrote:
From: Xiaogang Chen
To allow user better understand the cause triggering runlist oversubscription.
No function change.
Signed-off-by: Xiaogang Chen xiaogang.c...@amd.com
---
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 55 ++-
1
Raise an info message in kernel log if PCIe root complex
determines that a AMD GPU device D cannot have P2P
communication with another AMD GPU device D
Signed-off-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/
The patch below does not apply to the v6.1-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
The patch below does not apply to the v5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
The patch below does not apply to the v5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
The patch below does not apply to the v6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
The patch below does not apply to the v6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
This commit corrects the descriptors for the
vcn_v4_0/v4_0_3/v4_0_5/v5_0_0 _set_clockgating_state and
vcn_v4_0/v4_0_3/v4_0_5/v5_0_0 _set_powergating_state functions in the
amdgpu driver.
The parameter descriptors in the comments were mismatched with the
actual function parameters. The non-existent
The patch below does not apply to the v5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
The patch below does not apply to the v4.19-stable tree.
If someone wants it applied there, or to any other stable or longterm
tree, then please email the backport, including the original git commit
id to .
Thanks,
Sasha
-- original commit in Linus's tree --
>From
This commit adds the missing kdoc parameter descriptor for 'inst' in the
smu_dpm_set_power_gate function.
The 'inst' parameter, which specifies the instance of the IP block to
power gate/ungate.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.c:359: warning: Functi
This commit adds the cleaner shader microcode for GFX10.3.0 GPUs. The
cleaner shader is a piece of GPU code that is used to clear or
initialize certain GPU resources, such as Local Data Share (LDS), Vector
General Purpose Registers (VGPRs), and Scalar General Purpose Registers
(SGPRs).
Clearing th
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Wang, Yang(Kevin)
> Sent: Wednesday, November 6, 2024 2:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Zhou1, Tao
> ; Chai, Thomas
> Subject: [PATCH] drm/amdgpu
From: Gang Ba
amdgpu_amdkfd_alloc_gtt_mem currently allocates USWC memory.
It uses write-combining for CPU access, which is slow for reading.
Add a new parameter to amdgpu_amdkfd_alloc_gtt_mem to allocate
normal GTT memory.
Signed-off-by: Gang Ba
Reviewed-by: Felix Kuehling
Signed-off-by: Vict
On Tue Nov 5, 2024 at 2:51 AM PST, Dmitry Baryshkov wrote:
> On Tue, 5 Nov 2024 at 10:15, Christopher Snowhill wrote:
> >
> > On Mon Nov 4, 2024 at 12:52 PM PST, André Almeida wrote:
> > > Hi Christopher,
> > >
> > > Em 03/11/2024 03:36, Christopher Snowhill escreveu:
> > > > On Fri Nov 1, 2024 at
From: Monk Liu
As cache GTT buffer is snooped, this way the coherence between CPU write
and GPU fetch is guaranteed, but original code uses WC + unsnooped for
HIQ PQ(ring buffer) which introduces coherency issues:
MEC fetches a stall data from PQ and leads to MEC hang.
Signed-off-by: Monk Liu
-
fix ACA bank count boundary check error.
Fixes: f5e4cc8461c4 ("drm/amdgpu: implement RAS ACA driver framework")
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c
b/dri
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