Re: [PATCH v9 00/53] fix CONFIG_DRM_USE_DYNAMIC_DEBUG=y

On Mon, Jul 15, 2024 at 4:05 AM Łukasz Bartosik wrote: > > On Sat, Jul 13, 2024 at 11:45 PM wrote: > > > > On Fri, Jul 12, 2024 at 9:44 AM Łukasz Bartosik wrote: > > > > > > On Wed, Jul 3, 2024 at 12:14 AM wrote: > > > > > > > > On Tue, Jul 2, 2024 at 4:01 PM Luis Chamberlain > > > > wrote: >

[PATCH 1/3] drm/amdgpu: Add empty HDP flush function to JPEG v4.0.3

From: Lijo Lazar JPEG v4.0.3 doesn't support HDP flush when RRMT is enabled. Instead, mmsch fw will do the flush. This change is necessary for JPEG v4.0.3, no need for backward compatibility Signed-off-by: Lijo Lazar Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 +

[PATCH 3/3] drm/amdgpu/vcn: Use offsets local to VCN/JPEG in VF

For VCN/JPEG 4.0.3, use only the local addressing scheme. - Mask bit higher than AID0 range - Remove gmc v9 mmhub vmid replacement, since the bit will be masked later in register write/wait Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 5 --- drivers/gpu/drm/amd/amdg

[PATCH 2/3] drm/amdgpu: Add empty HDP flush function to VCN v4.0.3

From: Lijo Lazar VCN 4.0.3 does not HDP flush with RRMT enabled. Instead, mmsch will do the HDP flush. This change is necessary for VCN v4.0.3, no need for backward compatibility Signed-off-by: Lijo Lazar Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 1 fi

Re: [PATCH 3/3] drm/amdgpu/vcn: Use offsets local to VCN/JPEG in VF

On 7/16/2024 1:29 PM, Jane Jian wrote: > For VCN/JPEG 4.0.3, use only the local addressing scheme. > > - Mask bit higher than AID0 range > - Remove gmc v9 mmhub vmid replacement, since the bit will be masked later in > register write/wait > > Signed-off-by: Jane Jian > --- > drivers/gpu/drm

[PATCH 3/3] drm/amdgpu/vcn: Use offsets local to VCN/JPEG in VF

For VCN/JPEG 4.0.3, use only the local addressing scheme. - Mask bit higher than AID0 range v2 remain the case for mmhub use master XCC Signed-off-by: Jane Jian --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 19 -- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 46 ++--

[PATCH 2/2] drm/amdgpu: Add address alignment support to DCC buffers

Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nea

[PATCH 1/2] drm/buddy: Add start address support to trim function

- Add a new start parameter in trim function to specify exact address from where to start the trimming. This would help us in situations like if drivers would like to do address alignment for specific requirements. - Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this flag to disab

Re: [PATCH] drm/buddy: Add start address support to trim function

Hi Matthew, On 7/10/2024 6:20 PM, Matthew Auld wrote: On 10/07/2024 07:03, Paneer Selvam, Arunpravin wrote: Thanks Alex. Hi Matthew, Any comments? Do we not pass the required address alignment when allocating the pages in the first place? If address alignment is really useful, we can add th

Re: [PATCH] drm/buddy: Add start address support to trim function

On 16/07/2024 10:50, Paneer Selvam, Arunpravin wrote: Hi Matthew, On 7/10/2024 6:20 PM, Matthew Auld wrote: On 10/07/2024 07:03, Paneer Selvam, Arunpravin wrote: Thanks Alex. Hi Matthew, Any comments? Do we not pass the required address alignment when allocating the pages in the first plac

[PATCH v1 0/5] devcoredump for sdma v5.0 and sdma 6.0

*** BLURB HERE *** Sunil Khatri (5): drm/amdgpu: Add sdma_v6_0 ip dump for devcoredump drm/amdgpu: add print support for sdma_v_6_0 ip_dump drm/amdgpu: fix the extra space between two functions drm/amdgpu: Add sdma_v5_0 ip dump for devcoredump drm/amdgpu: add print support for sdma_v_5_0

[PATCH v1 1/5] drm/amdgpu: Add sdma_v6_0 ip dump for devcoredump

Add ip dump for sdma_v6_0 for devcoredump for all instances of sdma. Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 90 ++ 1 file changed, 90 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6

[PATCH v1 2/5] drm/amdgpu: add print support for sdma_v_6_0 ip_dump

Add print support for ip dump for sdma_v_6_0 in devcoredump. Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 1

[PATCH v1 4/5] drm/amdgpu: Add sdma_v5_0 ip dump for devcoredump

Add ip dump for sdma_v5_0 for devcoredump for all instances of sdma. Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 82 ++ 1 file changed, 82 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5

[PATCH v1 5/5] drm/amdgpu: add print support for sdma_v_5_0 ip_dump

Add support for ip dump for sdma_v_5_0 in devcoredump. Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index cb324a9

[PATCH v1 3/5] drm/amdgpu: fix the extra space between two functions

fix extra line space between two functions. Signed-off-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 630b03f2ce3d..66bb85955fa4 100644 --- a/dr

Re: [PATCH v1 5/5] drm/amdgpu: add print support for sdma_v_5_0 ip_dump

Series is: Reviewed-by: Alex Deucher On Tue, Jul 16, 2024 at 7:20 AM Sunil Khatri wrote: > > Add support for ip dump for sdma_v_5_0 in devcoredump. > > Signed-off-by: Sunil Khatri > --- > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 22 ++ > 1 file changed, 22 insertions(+) > >

Re: [PATCH 6/6] Documentation/amdgpu: Fix duplicate declaration

Series is: Acked-by: Alex Deucher On Mon, Jul 15, 2024 at 10:50 PM Rodrigo Siqueira wrote: > > Address the below kernel doc warning: > > Documentation/gpu/amdgpu/display/display-manager:134: > drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:3: WARNING: Duplicate C > declaration, also defined at gpu/

[PATCH AUTOSEL 6.9 11/22] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

[PATCH AUTOSEL 6.9 12/22] drm/amd/display: Add refresh rate range check

From: Tom Chung [ Upstream commit 74ad26b36d303ac233eccadc5c3a8d7ee4709f31 ] [Why] We only enable the VRR while monitor usable refresh rate range is greater than 10 Hz. But we did not check the range in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. [How] Add a refresh rate range check before set the f

[PATCH AUTOSEL 6.9 13/22] drm/amd/display: Account for cursor prefetch BW in DML1 mode support

From: Alvin Lee [ Upstream commit 074b3a886713f69d98d30bb348b1e4cb3ce52b22 ] [Description] We need to ensure to take into account cursor prefetch BW in mode support or we may pass ModeQuery but fail an actual flip which will cause a hang. Flip may fail because the cursor_pre_bw is populated duri

[PATCH AUTOSEL 6.9 14/22] drm/amd/display: Fix refresh rate range for some panel

From: Tom Chung [ Upstream commit 9ef1548aeaa8858e7aee2152bf95cc71cdcd6dff ] [Why] Some of the panels does not have the refresh rate range info in base EDID and only have the refresh rate range info in DisplayID block. It will cause the max/min freesync refresh rate set to 0. [How] Try to parse

[PATCH AUTOSEL 6.9 15/22] drm/amd/display: Update efficiency bandwidth for dcn351

From: Fangzhi Zuo [ Upstream commit 7ae37db29a8bc4d3d116a409308dd98fc3a0b1b3 ] Fix 4k240 underflow on dcn351 Acked-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dml2/dml2_

[PATCH AUTOSEL 6.9 17/22] drm/radeon: check bo_va->bo is non-NULL before using it

From: Pierre-Eric Pelloux-Prayer [ Upstream commit 6fb15dcbcf4f212930350eaee174bb60ed40a536 ] The call to radeon_vm_clear_freed might clear bo_va->bo, so we have to check it before dereferencing it. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Signed-off-by: Alex Deucher

[PATCH AUTOSEL 6.9 16/22] drm/amd/display: Fix array-index-out-of-bounds in dml2/FCLKChangeSupport

From: Roman Li [ Upstream commit 0ad4b4a2f6357c45fbe444ead1a929a0b4017d03 ] [Why] Potential out of bounds access in dml2_calculate_rq_and_dlg_params() because the value of out_lowest_state_idx used as an index for FCLKChangeSupport array can be greater than 1. [How] Currently dml2 core specifie

[PATCH AUTOSEL 6.6 10/18] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

[PATCH AUTOSEL 6.6 11/18] drm/amd/display: Add refresh rate range check

From: Tom Chung [ Upstream commit 74ad26b36d303ac233eccadc5c3a8d7ee4709f31 ] [Why] We only enable the VRR while monitor usable refresh rate range is greater than 10 Hz. But we did not check the range in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. [How] Add a refresh rate range check before set the f

[PATCH AUTOSEL 6.6 12/18] drm/amd/display: Account for cursor prefetch BW in DML1 mode support

From: Alvin Lee [ Upstream commit 074b3a886713f69d98d30bb348b1e4cb3ce52b22 ] [Description] We need to ensure to take into account cursor prefetch BW in mode support or we may pass ModeQuery but fail an actual flip which will cause a hang. Flip may fail because the cursor_pre_bw is populated duri

[PATCH AUTOSEL 6.6 13/18] drm/amd/display: Fix refresh rate range for some panel

From: Tom Chung [ Upstream commit 9ef1548aeaa8858e7aee2152bf95cc71cdcd6dff ] [Why] Some of the panels does not have the refresh rate range info in base EDID and only have the refresh rate range info in DisplayID block. It will cause the max/min freesync refresh rate set to 0. [How] Try to parse

[PATCH AUTOSEL 6.6 14/18] drm/radeon: check bo_va->bo is non-NULL before using it

From: Pierre-Eric Pelloux-Prayer [ Upstream commit 6fb15dcbcf4f212930350eaee174bb60ed40a536 ] The call to radeon_vm_clear_freed might clear bo_va->bo, so we have to check it before dereferencing it. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Signed-off-by: Alex Deucher

[PATCH AUTOSEL 6.1 09/15] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

[PATCH AUTOSEL 6.1 10/15] drm/amd/display: Account for cursor prefetch BW in DML1 mode support

From: Alvin Lee [ Upstream commit 074b3a886713f69d98d30bb348b1e4cb3ce52b22 ] [Description] We need to ensure to take into account cursor prefetch BW in mode support or we may pass ModeQuery but fail an actual flip which will cause a hang. Flip may fail because the cursor_pre_bw is populated duri

[PATCH AUTOSEL 6.1 11/15] drm/radeon: check bo_va->bo is non-NULL before using it

From: Pierre-Eric Pelloux-Prayer [ Upstream commit 6fb15dcbcf4f212930350eaee174bb60ed40a536 ] The call to radeon_vm_clear_freed might clear bo_va->bo, so we have to check it before dereferencing it. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Signed-off-by: Alex Deucher

[PATCH AUTOSEL 5.15 6/9] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

[PATCH AUTOSEL 5.15 7/9] drm/radeon: check bo_va->bo is non-NULL before using it

From: Pierre-Eric Pelloux-Prayer [ Upstream commit 6fb15dcbcf4f212930350eaee174bb60ed40a536 ] The call to radeon_vm_clear_freed might clear bo_va->bo, so we have to check it before dereferencing it. Signed-off-by: Pierre-Eric Pelloux-Prayer Acked-by: Alex Deucher Signed-off-by: Alex Deucher

[PATCH AUTOSEL 5.10 6/7] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

[PATCH AUTOSEL 5.4 6/7] drm/amd/display: Reset freesync config before update new state

From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config befor

Re: [PATCH AUTOSEL 6.9 11/22] drm/amd/display: Reset freesync config before update new state

Hi Sasha, On 7/16/24 10:24, Sasha Levin wrote: From: Tom Chung [ Upstream commit 6b8487cdf9fc7bae707519ac5b5daeca18d1e85b ] [Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state

[PATCH] drm/amd/display: Add null check for dm_state in create_validate_stream_for_sink

This commit adds a null check for the dm_state variable in the create_validate_stream_for_sink function. Previously, dm_state was being checked for nullity at line 7194, but then it was being dereferenced without any nullity check at line 7200. This could potentially lead to a null pointer derefere

[PATCH v5 1/2] drm/buddy: Add start address support to trim function

- Add a new start parameter in trim function to specify exact address from where to start the trimming. This would help us in situations like if drivers would like to do address alignment for specific requirements. - Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this flag to disab

[PATCH v5 2/2] drm/amdgpu: Add address alignment support to DCC buffers

Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nea

[PATCH] drm/amd/display: Add null check for set_output_gamma in dcn30_set_output_transfer_func

This commit adds a null check for the set_output_gamma function pointer in the dcn30_set_output_transfer_func function. Previously, set_output_gamma was being checked for nullity at line 386, but then it was being dereferenced without any nullity check at line 401. This could potentially lead to a

Re: [PATCH] drm/amd/display: Add null check for dm_state in create_validate_stream_for_sink

On 7/16/24 11:08, Srinivasan Shanmugam wrote: This commit adds a null check for the dm_state variable in the create_validate_stream_for_sink function. Previously, dm_state was being checked for nullity at line 7194, but then it was being dereferenced without any nullity check at line 7200. This c

[PATCH] drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell

We seem to have a case where SDMA will sometimes miss a doorbell if GFX is entering the powergating state when the doorbell comes in. To workaround this, we can update the wptr via MMIO, however, this is only safe because we disallow gfxoff in begin_ring() for SDMA 5.2 and then allow it again in en

Re: DisplayPort: handling of HPD events / link training

Hi Am 27.02.24 um 23:40 schrieb Dmitry Baryshkov: Hello, We are currently looking at checking and/or possibly redesigning the way the MSM DRM driver handles the HPD events and link training. After a quick glance at the drivers implementing DP support, I noticed following main approaches: - Per

Re: DisplayPort: handling of HPD events / link training

On Tue, 16 Jul 2024 at 18:58, Thomas Zimmermann wrote: > > Hi > > Am 27.02.24 um 23:40 schrieb Dmitry Baryshkov: > > Hello, > > > > We are currently looking at checking and/or possibly redesigning the > > way the MSM DRM driver handles the HPD events and link training. > > > > After a quick glance

Re: DisplayPort: handling of HPD events / link training

Hi Am 16.07.24 um 18:35 schrieb Dmitry Baryshkov: On Tue, 16 Jul 2024 at 18:58, Thomas Zimmermann wrote: Hi Am 27.02.24 um 23:40 schrieb Dmitry Baryshkov: Hello, We are currently looking at checking and/or possibly redesigning the way the MSM DRM driver handles the HPD events and link train

Re: 6.10/bisected/regression - commits bc87d666c05 and 6d4279cb99ac cause appearing green flashing bar on top of screen on Radeon 6900XT and 120Hz

Does the attached partial revert fix it? Alex On Wed, Jul 10, 2024 at 3:03 AM Mikhail Gavrilov wrote: > > On Wed, Jul 10, 2024 at 12:01 PM Mikhail Gavrilov > wrote: > > > > On Tue, Jul 9, 2024 at 7:48 PM Rodrigo Siqueira Jordao > > wrote: > > > Hi, > > > > > > I also tried it with 6900XT. I go

Re: DisplayPort: handling of HPD events / link training

On Tue, Jul 16, 2024 at 06:48:12PM GMT, Thomas Zimmermann wrote: > Hi > > Am 16.07.24 um 18:35 schrieb Dmitry Baryshkov: > > On Tue, 16 Jul 2024 at 18:58, Thomas Zimmermann wrote: > > > Hi > > > > > > Am 27.02.24 um 23:40 schrieb Dmitry Baryshkov: > > > > Hello, > > > > > > > > We are currently

[PATCH] drm/amd/display: fix corruption with high refresh rates on DCN 3.0

This reverts commit bc87d666c05a13e6d4ae1ddce41fc43d2567b9a2 and the register changes from commit 6d4279cb99ac4f51d10409501d29969f687ac8dc. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3478 Cc: mikhail.v.gavri...@gmail.com Cc: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/

Re: [PATCH] drm/amd/display: fix corruption with high refresh rates on DCN 3.0

On 7/16/24 11:33 AM, Alex Deucher wrote: This reverts commit bc87d666c05a13e6d4ae1ddce41fc43d2567b9a2 and the register changes from commit 6d4279cb99ac4f51d10409501d29969f687ac8dc. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3478 Cc: mikhail.v.gavri...@gmail.com Cc: Rodrigo Siquei

Re: [PATCH] drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell

On 16.07.24 17:54, Alex Deucher wrote: We seem to have a case where SDMA will sometimes miss a doorbell if GFX is entering the powergating state when the doorbell comes in. To workaround this, we can update the wptr via MMIO, however, this is only safe because we disallow gfxoff in begin_ring() f

Re: [PATCH] drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell

On Tue, Jul 16, 2024 at 2:30 PM Friedrich Vock wrote: > > On 16.07.24 17:54, Alex Deucher wrote: > > We seem to have a case where SDMA will sometimes miss a doorbell > > if GFX is entering the powergating state when the doorbell comes in. > > To workaround this, we can update the wptr via MMIO, ho

[PATCH v2] drm/amd/display: Add null check for dm_state in create_validate_stream_for_sink

This commit adds a null check for the dm_state variable in the create_validate_stream_for_sink function. Previously, dm_state was being checked for nullity at line 7194, but then it was being dereferenced without any nullity check at line 7200. This could potentially lead to a null pointer derefere

Re: [PATCH v5 2/2] drm/amdgpu: Add address alignment support to DCC buffers

AMDGPU_GEM_CREATE_GFX12_DCC is set on 90% of all memory allocations, and almost all of them are not displayable. Shouldn't we use a different way to indicate that we need a non-power-of-two alignment, such as looking at the alignment field directly? Marek On Tue, Jul 16, 2024, 11:45 Arunpravin Pa

Re: 6.10/bisected/regression - commits bc87d666c05 and 6d4279cb99ac cause appearing green flashing bar on top of screen on Radeon 6900XT and 120Hz

On Tue, Jul 16, 2024 at 10:10 PM Alex Deucher wrote: > > Does the attached partial revert fix it? > > Alex > Yes, thanks. Tested-by: Mikhail Gavrilov -- Best Regards, Mike Gavrilov.