Got it.
I had some mental block about passing designated intializers as macro args.
it just worked, I needed to eyeball the .i file just to be sure.
thanks.
I have a fixup patch.
whats the best thing to do with it, squash it in for later ? send in
reply here ?
On Wed, Jul 3, 2024 at 5:52 AM Ville
Thanks a lot for your help Thomas.
On Wed, Jul 3, 2024 at 4:52 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 30.06.24 um 18:59 schrieb Wu Hoi Pok:
> > .load and drm_dev_alloc are deprecated. These patch series aims to
> > remove them.
> >
> > v3: Both v1 and v2 sucks. v3 improves greatly on readabili
Am 03.07.24 um 21:36 schrieb Alex Deucher:
Switch to fist last for consistency.
Signed-off-by: Alex Deucher
Cc: Xinhui Pan
Ah, that's probably my fault. I copy&pasted that from a mail.
Reviewed-by: Christian König
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Am 03.07.24 um 21:36 schrieb Alex Deucher:
Evan is no longer maintaining powerplay and swsmu.
Add Kenneth Feng as his replacement.
Signed-off-by: Alex Deucher
Cc: Kenneth Feng
Acked-by: Christian König
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
- Add a new start parameter in trim function to specify exact
address from where to start the trimming. This would help us
in situations like if drivers would like to do address alignment
for specific requirements.
- Add a new flag DRM_BUDDY_TRIM_DISABLE. Drivers can use this
flag to disab
Add address alignment support to the DCC VRAM buffers.
v2:
- adjust size based on the max_texture_channel_caches values
only for GFX12 DCC buffers.
- used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only
for DCC buffers.
- roundup non power of two DCC buffer adjusted size to nea
Am 04.07.24 um 10:30 schrieb Arunpravin Paneer Selvam:
Add address alignment support to the DCC VRAM buffers.
v2:
- adjust size based on the max_texture_channel_caches values
only for GFX12 DCC buffers.
- used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only
for DCC buffers.
Am 03.07.24 um 19:49 schrieb Sunil Khatri:
We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.
Enable ring1 allows software to redirect
high interrupts to ring1 from default IH
ring.
Signed-off-by: Sunil Khatri
Reviewed-by: Christian
Uprev IGT to the latest version, which includes a fix for the
writeback tests issue on MSM devices. Enable debugging for
igt-runner to log output such as 'Begin test' and 'End test'.
This will help identify which test causes system freeze or hangs.
Update xfails and add metadata header for each fla
On Thu, Jul 04, 2024 at 02:52:02PM GMT, Vignesh Raman wrote:
> Uprev IGT to the latest version, which includes a fix for the
> writeback tests issue on MSM devices. Enable debugging for
> igt-runner to log output such as 'Begin test' and 'End test'.
> This will help identify which test causes syste
DPG mode is enabled for vcn and jpeg on VCN v4_0_5
Signed-off-by: Saleemkhan Jamadar
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6cc86d13f32a..d30ad7d5
[AMD Official Use Only - AMD Internal Distribution Only]
This patch is,
Reviewed-by: Tim Huang mailto:tim.hu...@amd.com>>
Tim
From: amd-gfx on behalf of Saleemkhan
Jamadar
Sent: Thursday, July 4, 2024 6:14:36 PM
To: amd-gfx@lists.freedesktop.org ; Jamadar,
Sa
Am 04.07.24 um 06:58 schrieb Hoi Pok Wu:
Thanks a lot for your help Thomas.
On Wed, Jul 3, 2024 at 4:52 AM Thomas Zimmermann wrote:
Hi
Am 30.06.24 um 18:59 schrieb Wu Hoi Pok:
.load and drm_dev_alloc are deprecated. These patch series aims to
remove them.
v3: Both v1 and v2 sucks. v3 improv
Am 04.07.24 um 07:52 schrieb Yang Wang:
remove redundant semicolons in RAS_EVENT_LOG to avoid
code format check warning.
Fixes: 951c09c88fca ("drm/amdgpu: fix compiler 'side-effect' check issue for
RAS_EVENT_LOG()")
Signed-off-by: Yang Wang
Ah, yes one of the most common mistakes of all tim
Le 03/07/2024 à 16:10, Christian König a écrit :
Am 03.07.24 um 14:48 schrieb Pierre-Eric Pelloux-Prayer:
Le 02/07/2024 à 15:35, Christian König a écrit :
Am 02.07.24 um 15:23 schrieb Pierre-Eric Pelloux-Prayer:
Before this commit, only submits with both a BO_HANDLES chunk and a
'bo_list_ha
Add "Series" to MI200 and MI300 to clarify that they represent the
series of cards, and to more closely match the product information
materials. This also matches other entries in this list
Also correct a typo in the MI300 codename (Vangaram->Vanjaram)
Signed-off-by: Kent Russell
---
Documentat
to avoid reading wrong WPTR from doorbell in sriov vf, set
CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_MODE to 1 to read WPTR from MQD.
Signed-off-by: Zhigang Luo
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +++
2 files changed, 6 inse
Currently the DRM DSC functions are selected by the
DRM_DISPLAY_DP_HELPER Kconfig symbol. This is not optimal, since the DSI
code (both panel and host drivers) end up selecting the seemingly
irrelevant DP helpers. Split the DSC code to be guarded by the separate
DRM_DISPLAY_DSC_HELPER Kconfig symbo
Hi Joao,
First of all, thanks for your patch. Follows some of my comments:
> On 6/13/24 10:05 AM, Joao Paulo Pereira da Silva wrote:
You can drop the dc part in the commit title. Also, the title should
highlight that you are decoupling one part of the code in a single place
to avoid duplicati
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