Hi
Am 21.06.24 um 16:15 schrieb Wu Hoi Pok:
This is "drm/radeon: remove load callback" v2, the only changes
were made are adding "ddev->dev_private = rdev;", right after
the allocation of "struct radeon_device". Patch v2 2-7 mostly
describes simple "rdev->ddev" to "rdev_to_drm(rdev)" to suit
Pat
Hi,
On 6/23/24 10:20 PM, Mario Limonciello wrote:
> On 6/23/2024 03:51, Thomas Weißschuh wrote:
>> Panels using a PWM-controlled backlight source without an do not have a
>> standard way to communicate their valid PWM ranges.
>> On x86 the ranges are read from ACPI through driver-specific tables.
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a generic quirk infrastructure for backlight configuration to
override the settings provided by the firmware.
Also add amdgpu as a user of that infrastruct
resource_get_otg_master_for_stream() could return NULL, we
should check the return value of 'otg_master' before it is
used in resource_log_pipe_for_stream().
Signed-off-by: Ma Ke
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/g
Not all platforms provide correct PWM backlight capabilities through ATIF.
Use the generic drm backlight quirk infrastructure to override the
capabilities where necessary.
Signed-off-by: Thomas Weißschuh
---
drivers/gpu/drm/amd/amdgpu/Kconfig| 1 +
drivers/gpu/drm/amd/display/am
To avoid reports of NULL_RETURN warning, we should add
otg_master NULL check.
Signed-off-by: Ma Ke
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/dc
The function are defined in the amdgpu_dm.c file, but not called
anywhere, so delete the unused function.
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:371:20: warning:
unused function 'reverse_planes_order'.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug
Use existing swap() function rather than duplicating its implementation.
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1171:103-104:
WARNING opportunity for swap().
./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1231:99-100:
WARNIN
The value of "min_input_signal" returned from ATIF on a Framework AMD 13
is "12". This leads to a fairly bright minimum display backlight.
Add a quirk to override that the minimum backlight PWM to "0" which
leads to a much lower minimum brightness, which is still visible.
Tested on a Framework AM
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACPI through driver-specific tables.
The built-in ranges are not necessarily correct, or may grow stale if an
older device can be retrofitted w
Use of macro ARRAY_SIZE to calculate array size minimizes
the redundant code and improves code reusability.
./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:164:45-46: WARNING: Use
ARRAY_SIZE.
./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:183:47-48: WARNING: Use
ARRAY_SIZE.
./driver
On 6/21/2024 1:45 PM, Jane Jian wrote:
> [WHY]
> sriov has the higher bit violation when flushing tlb
>
> [HOW]
> normalize the registers to keep lower 16-bit(dword aligned) to aviod higher
> bit violation
> RLCG will mask xcd out and always assume it's accessing its own xcd
>
> [TODO]
> late
This reverts commit 358c258a816baed4c6997b59c2117578a1360498.
Jerome actually pointed out why that stuff doesn't work in 2016:
https://lists.freedesktop.org/archives/dri-devel/2016-March/103062.html
Unfortunately the revert somehow got lost.
Signed-off-by: Christian König
Fixes: 358c258a816baed
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
[TODO]
later will add the normalization in sriovw/rreg after fixing bugs
Am 24.06.24 um 08:58 schrieb Danijel Slivka:
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so th
Am 24.06.24 um 11:13 schrieb Jane Jian:
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
[TODO]
later will add the norma
Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
On 6/24/2024 12:01 PM, Vignesh Chander wrote:
correctly handle the case when trylock fails when gpu is
about to be reset by dropping the request instead of using mmio
Signed-off-by: Vignesh Chander
Reviewed-by: Lijo Lazar
Thanks,
Lijo
---
drive
On 6/24/2024 3:08 PM, Christian König wrote:
> Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
>>
>> On 6/24/2024 12:01 PM, Vignesh Chander wrote:
>>> correctly handle the case when trylock fails when gpu is
>>> about to be reset by dropping the request instead of using mmio
>>>
>>> Signed-off-by: Vig
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christian,
The reason that why I moved around amdgpu_asic_funcs because the new function
that I declared in amdgpu_asic_funcs used the enum amd_hw_ip_block_type,
therefore I move it after the definition of the amd_hw_ip_block_type.
Tha
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear
[AMD Official Use Only - AMD Internal Distribution Only]
>-Original Message-
>From: Christian König
>Sent: Monday, June 24, 2024 11:31 AM
>To: Slivka, Danijel ; amd-gfx@lists.freedesktop.org;
>Prica, Nikola
>Subject: Re: [PATCH] drm/amdgpu: clear RB_OVERFLOW bit if detected when
>enablin
On Sun, 23 Jun 2024 at 14:22, Joshua Ashton wrote:
> Maybe that wasn't you or whatever, but your last patch that did this got
> some CVE assigned to it that didn't really make any sense, given this is
> just a null deref that'd end up as an oops?
>
> It can only happen if the kzalloc in drm_mode_
I have no idea how to enable quadbuffer stereo (hdmi-3d) on linux for intel and
amdgpu.
I tried using Option Stereo 12 with this result
(WW) AMDGPU(0): Option "Stereo" is not used
Hoping for solutions for both cards (intel arc,renoir)
thanks
--
#xorg
Am 24.06.24 um 11:52 schrieb Lazar, Lijo:
On 6/24/2024 3:08 PM, Christian König wrote:
Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
On 6/24/2024 12:01 PM, Vignesh Chander wrote:
correctly handle the case when trylock fails when gpu is
about to be reset by dropping the request instead of using mm
Am 24.06.24 um 11:56 schrieb Jian, Jane:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christian,
The reason that why I moved around amdgpu_asic_funcs because the new function
that I declared in amdgpu_asic_funcs used the enum amd_hw_ip_block_type,
therefore I move it after the d
Am 24.06.24 um 12:06 schrieb Danijel Slivka:
Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.
How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so th
On 6/24/2024 5:19 PM, Christian König wrote:
> Am 24.06.24 um 11:52 schrieb Lazar, Lijo:
>>
>> On 6/24/2024 3:08 PM, Christian König wrote:
>>> Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
On 6/24/2024 12:01 PM, Vignesh Chander wrote:
> correctly handle the case when trylock fails when gpu
Am 24.06.24 um 11:13 schrieb Jane Jian:
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
[TODO]
later will add the norma
Am 24.06.24 um 13:57 schrieb Lazar, Lijo:
On 6/24/2024 5:19 PM, Christian König wrote:
Am 24.06.24 um 11:52 schrieb Lazar, Lijo:
On 6/24/2024 3:08 PM, Christian König wrote:
Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
On 6/24/2024 12:01 PM, Vignesh Chander wrote:
correctly handle the case when
On 6/24/2024 5:31 PM, Christian König wrote:
> Am 24.06.24 um 13:57 schrieb Lazar, Lijo:
>> On 6/24/2024 5:19 PM, Christian König wrote:
>>> Am 24.06.24 um 11:52 schrieb Lazar, Lijo:
On 6/24/2024 3:08 PM, Christian König wrote:
> Am 24.06.24 um 08:34 schrieb Lazar, Lijo:
>> On 6/24/
On Mon, Jun 24, 2024 at 5:17 AM Christian König
wrote:
>
> This reverts commit 358c258a816baed4c6997b59c2117578a1360498.
>
> Jerome actually pointed out why that stuff doesn't work in 2016:
> https://lists.freedesktop.org/archives/dri-devel/2016-March/103062.html
>
> Unfortunately the revert someh
Am 24.06.24 um 14:24 schrieb Lazar, Lijo:
On 6/24/2024 5:31 PM, Christian König wrote:
Am 24.06.24 um 13:57 schrieb Lazar, Lijo:
On 6/24/2024 5:19 PM, Christian König wrote:
Am 24.06.24 um 11:52 schrieb Lazar, Lijo:
On 6/24/2024 3:08 PM, Christian König wrote:
Am 24.06.24 um 08:34 schrieb La
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Christian,
I want to explain here that:
1. add the normalization func in the asic file: this was modified according to
previous Lijo's comments, he thought it would be more convenient if further
asics need that way as well.
2. currently
Leftover copy pasta from original code.
Signed-off-by: Alex Deucher
Cc: harry.wentl...@amd.com
---
drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 11 ++-
drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 10 ++
drivers/gpu/drm/amd/display/dc/dcn314/Makefile | 11 ++-
dri
On 6/24/24 09:58, Alex Deucher wrote:
Leftover copy pasta from original code.
Signed-off-by: Alex Deucher
Cc: harry.wentl...@amd.com
Reviewed-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 11 ++-
drivers/gpu/drm/amd/display/dc/dcn31/Makefile | 10 ++
Before, every time fdinfo is queried we try to lock all the BOs in the
VM and calculate memory usage from scratch. This works okay if the
fdinfo is rarely read and the VMs don't have a ton of BOs. If either of
these conditions is not true, we get a massive performance hit.
In this new revision, we
Since on modern systems all of vram can be made visible anyways, to
simplify the new implementation, drops tracking how much memory is
visible for now. If this is still needed we can add it back on top of
the new implementation.
Signed-off-by: Yunxiang Li
---
v2: split into two patchs for clarity
[Public]
I'm not happy with the new helper names, and not quite satisfied with the
function arguments either. But it's what I got right now, would appreciate it
if anyone got better ideas.
Teddy
Applied. Thanks!
On Sun, Jun 23, 2024 at 11:37 PM Jiapeng Chong
wrote:
>
> Use of macro ARRAY_SIZE to calculate array size minimizes
> the redundant code and improves code reusability.
>
> ./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:164:45-46: WARNING: Use
> ARRAY_SIZE.
> ./drivers/gp
[AMD Official Use Only - AMD Internal Distribution Only]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the
On Mon, Jun 24, 2024 at 4:07 AM Jiapeng Chong
wrote:
>
> The function are defined in the amdgpu_dm.c file, but not called
> anywhere, so delete the unused function.
>
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:371:20: warning:
> unused function 'reverse_planes_order'.
>
> Repor
Applied. Thanks!
Alex
On Sun, Jun 23, 2024 at 10:22 PM Jiapeng Chong
wrote:
>
> Use existing swap() function rather than duplicating its implementation.
>
> ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1171:103-104:
> WARNING opportunity for swap().
> ./driver
On 2024-06-21 13:28, Xiaogang.Chen
wrote:
From: Xiaogang Chen
When user adds new vm range that has overlapping with existing svm pranges
current kfd clones new prange and remove existing pranges including all data
associate with it. It is not necessary. We
From: Sonny Jiang
Add DPG support for JPEG 5.0
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 31 +
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 159 ---
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.h | 6 +
drivers/gpu/drm/amd/amdgpu/soc24.c
Well as far as I know under SRIOV most of the registers accesses go
through the KIQ.
When the KIQ is limited in it's accessibility to only the local XCD then
we need to handle that in the KIQ code and *not* in every user of
register reads and writes.
So please drop that approach and implemen
On 6/23/2024 15:55, Hans de Goede wrote:
Hi,
On 6/23/24 10:20 PM, Mario Limonciello wrote:
On 6/23/2024 03:51, Thomas Weißschuh wrote:
Panels using a PWM-controlled backlight source without an do not have a
standard way to communicate their valid PWM ranges.
On x86 the ranges are read from ACP
On 6/24/2024 11:17 AM, Philip Yang wrote:
On 2024-06-21 13:28, Xiaogang.Chen wrote:
From: Xiaogang Chen
When user adds new vm range that has overlapping with existing svm pranges
current kfd clones new prange and remove existing pranges including all data
associate with it. It is not necess
These have been announced so add them to the table.
Link:
https://www.amd.com/en/products/processors/laptop/ryzen/300-series/amd-ryzen-ai-9-hx-370.html
Signed-off-by: Mario Limonciello
---
Documentation/gpu/amdgpu/apu-asic-info-table.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/Docum
These have been announced so add them to the table.
Link:
https://www.amd.com/en/products/processors/desktops/ryzen/9000-series/amd-ryzen-9-9950x.html
Signed-off-by: Mario Limonciello
---
Documentation/gpu/amdgpu/apu-asic-info-table.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/Docume
[Public]
Quadbuffer stereo is not supported on Linux.
Alex
From: amd-gfx On Behalf Of adblover
Sent: Monday, June 24, 2024 6:53 AM
To: intel-...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Subject: quadbuffer stereo
I have no idea how to enable quadbuffer stereo (hdmi-3d) on linux for
On Sun, 23 Jun 2024 07:11:24 +0800 kernel test robot wrote:
> tree/branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> branch HEAD: f76698bd9a8ca01d3581236082d786e9a6b72bb7 Add linux-next
> specific files for 20240621
>
> Error/Warning reports:
>
> https://
On Mon, Jun 24, 2024 at 3:22 PM Mario Limonciello
wrote:
>
> These have been announced so add them to the table.
>
> Link:
> https://www.amd.com/en/products/processors/laptop/ryzen/300-series/amd-ryzen-ai-9-hx-370.html
> Signed-off-by: Mario Limonciello
Series is:
Acked-by: Alex Deucher
> ---
52 matches
Mail list logo
