Instead of manually passing around 'struct edid *' and its size,
use 'struct drm_edid', which encapsulates a validated combination of
both.
As the drm_edid_ can handle NULL gracefully, the explicit checks can be
dropped.
Also save a few characters by transforming '&array[0]' to the equivalent
'ar
Hello Hawking Zhang,
Commit 3d879e81f0f9 ("drm/amdgpu: add init support for GFX11 (v2)")
from Apr 13, 2022 (linux-next), leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:4503 gfx_v11_0_hw_init()
error: we previously assumed 'adev->gfx.im
I only build the kernel once. I could try but I think you couldn't
expect much from my side.
BTW I installed 6.10-rc4 this morning from Ubuntu mainline
(https://kernel.ubuntu.com/mainline/v6.10-rc4/amd64/) and I couldn't
replicate the video crash problem. Yunchen could you try 6.10-rc4 and
see if
On Sat, 2024-06-15 at 17:50 +0200, Thorsten Leemhuis wrote:
> [reply made easier by moving something in the quote]
>
> On 12.06.24 18:55, Wang Yunchen wrote:
> > On Wed, 2024-06-12 at 15:14 +0200, Linux regression tracking (Thorsten
> > Leemhuis) wrote:
> > > On 06.06.24 05:06, Winston Ma wrote:
>
On 2024-06-16 11:12:03+, Thomas Weißschuh wrote:
> Instead of manually passing around 'struct edid *' and its size,
> use 'struct drm_edid', which encapsulates a validated combination of
> both.
>
> As the drm_edid_ can handle NULL gracefully, the explicit checks can be
> dropped.
>
> Also sa
[reply made easier by moving something in the quote]
On 12.06.24 18:55, Wang Yunchen wrote:
> On Wed, 2024-06-12 at 15:14 +0200, Linux regression tracking (Thorsten
> Leemhuis) wrote:
>> On 06.06.24 05:06, Winston Ma wrote:
>>> Hi I got the same problem on Linux Kernel 6.10-rc2. I got the problem
Am 23.05.24 um 18:29 schrieb Greg KH:
On Thu, May 23, 2024 at 05:59:39PM +0200, Armin Wolf wrote:
Am 23.05.24 um 15:13 schrieb Barry Kauler:
On Wed, May 22, 2024 at 12:58 AM Armin Wolf wrote:
Am 20.05.24 um 18:22 schrieb Alex Deucher:
On Sat, May 18, 2024 at 8:17 PM Armin Wolf wrote:
Am
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
also fix the typo in sriov_w/rreg:
for KIQ case, use xcc with xcc_id to r
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit
violation
RLCG will mask xcd out and always assume it's accessing its own xcd
also fix the typo in sriov_w/rreg:
for KIQ case, use xcc with xcc_id to r
This patchset tries to fix some workaround code in amdgpu/radeon driver,
that makes Loongson 3A+7A platform suffering from GPU crashes.
Icenowy Zheng (2):
drm/amdgpu: make duplicated EOP packet for GFX7/8 have real content
drm/radeon: repeat the same EOP packet for EOP workaround on CIK
driv
The duplication of EOP packets for GFX7/8, with the former one have
seq-1 written and the latter one have seq written, seems to confuse some
hardware platform (e.g. Loongson 7A series PCIe controllers).
Make the content of the duplicated EOP packet the same with the real
one, only masking any poss
Ths first EOP packet with a sequence number as seq-1 seems to confuse
some PCIe hardware (e.g. Loongson 7A PCHs).
Use the real sequence number instead.
Fixes: a9c73a0e022c ("drm/radeon: workaround for CP HW bug on CIK")
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/radeon/cik.c | 7 ++-
Am 17.06.24 um 12:58 schrieb Icenowy Zheng:
The duplication of EOP packets for GFX7/8, with the former one have
seq-1 written and the latter one have seq written, seems to confuse some
hardware platform (e.g. Loongson 7A series PCIe controllers).
Make the content of the duplicated EOP packet the
在 2024-06-17星期一的 14:35 +0200，Christian König写道：
> Am 17.06.24 um 12:58 schrieb Icenowy Zheng:
> > The duplication of EOP packets for GFX7/8, with the former one have
> > seq-1 written and the latter one have seq written, seems to confuse
> > some
> > hardware platform (e.g. Loongson 7A series PCIe
On Mon, 2024-06-17 at 06:55 +0800, Winston Ma wrote:
> I only build the kernel once. I could try but I think you couldn't
> expect much from my side.
>
> BTW I installed 6.10-rc4 this morning from Ubuntu mainline
> (https://kernel.ubuntu.com/mainline/v6.10-rc4/amd64/) and I couldn't
> replicate th
Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
在 2024-06-17星期一的 14:35 +0200，Christian König写道：
Am 17.06.24 um 12:58 schrieb Icenowy Zheng:
The duplication of EOP packets for GFX7/8, with the former one have
seq-1 written and the latter one have seq written, seems to confuse
some
hardware platform
From: Tasos Sahanidis
[ Upstream commit c6c4dd54012551cce5cde408b35468f2c62b0cce ]
Flexible arrays used [1] instead of []. Replace the former with the latter
to resolve multiple UBSAN warnings observed on boot with a BONAIRE card.
In addition, use the __counted_by attribute where possible to hi
在 2024-06-17星期一的 15:09 +0200，Christian König写道：
> Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
> > 在 2024-06-17星期一的 14:35 +0200，Christian König写道：
> > > Am 17.06.24 um 12:58 schrieb Icenowy Zheng:
> > > > The duplication of EOP packets for GFX7/8, with the former one
> > > > have
> > > > seq-1 writt
Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
在 2024-06-17星期一的 15:09 +0200，Christian König写道：
Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
在 2024-06-17星期一的 14:35 +0200，Christian König写道：
Am 17.06.24 um 12:58 schrieb Icenowy Zheng:
The duplication of EOP packets for GFX7/8, with the former one
ha
[Public]
Hi all,
This week this patchset was tested on the following systems:
* Lenovo ThinkBook T13s Gen4 with AMD Ryzen 5 6600U
* MSI Gaming X Trio RX 6800
* Gigabyte Gaming OC RX 7900 XTX
These systems were tested on the following display/connection types:
* eD
在 2024-06-17星期一的 15:59 +0200，Christian König写道：
> Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
> > 在 2024-06-17星期一的 15:09 +0200，Christian König写道：
> > > Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
> > > > 在 2024-06-17星期一的 14:35 +0200，Christian König写道：
> > > > > Am 17.06.24 um 12:58 schrieb Icenowy
On Thu, Jun 13, 2024 at 12:17:00AM -0500, Mario Limonciello wrote:
> If the lid on a laptop is closed when eDP connectors are populated
> then it remains enabled when the initial framebuffer configuration
> is built.
>
> When creating the initial framebuffer configuration detect the
> lid status a
Am 17.06.24 um 16:30 schrieb Icenowy Zheng:
在 2024-06-17星期一的 15:59 +0200，Christian König写道：
Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
在 2024-06-17星期一的 15:09 +0200，Christian König写道：
Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
在 2024-06-17星期一的 14:35 +0200，Christian König写道：
Am 17.06.24 um 1
Signed-off-by: Vignesh Chander
Change-Id: Ifead637951c00e5b4e97c766d172323dcac4da08
---
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 19 +++
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 23 +++
2 files changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/
For RAS error scenario, VF guest driver will check mailbox
and set fed flag to avoid unnecessary HW accesses.
additionally, poll for reset completion message first
to avoid accidentally spamming multiple reset requests to host.
Signed-off-by: Vignesh Chander
Change-Id: I364c417ce292bec6bf98671bc0
在 2024-06-17星期一的 16:42 +0200，Christian König写道：
> Am 17.06.24 um 16:30 schrieb Icenowy Zheng:
> > 在 2024-06-17星期一的 15:59 +0200，Christian König写道：
> > > Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
> > > > 在 2024-06-17星期一的 15:09 +0200，Christian König写道：
> > > > > Am 17.06.24 um 15:03 schrieb Icenowy
On Wed, Jun 12, 2024 at 6:37 PM Douglas Anderson wrote:
>
> Based on grepping through the source code this driver appears to be
> missing a call to drm_atomic_helper_shutdown() at system shutdown
> time. Among other things, this means that if a panel is in use that it
> won't be cleanly powered of
Am 17.06.24 um 16:57 schrieb Icenowy Zheng:
在 2024-06-17星期一的 16:42 +0200，Christian König写道：
Am 17.06.24 um 16:30 schrieb Icenowy Zheng:
在 2024-06-17星期一的 15:59 +0200，Christian König写道：
Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
在 2024-06-17星期一的 15:09 +0200，Christian König写道：
...
In this cas
Am 17.06.24 um 17:35 schrieb Xi Ruoyao:
On Mon, 2024-06-17 at 22:30 +0800, Icenowy Zheng wrote:
Two consecutive writes to the same bus address are perfectly legal
from
the PCIe specification and can happen all the time, even without this
specific hw workaround.
Yes I know it, and I am not from
在 2024-06-17星期一的 15:59 +0200，Christian König写道：
> Am 17.06.24 um 15:43 schrieb Icenowy Zheng:
> > 在 2024-06-17星期一的 15:09 +0200，Christian König写道：
> > > Am 17.06.24 um 15:03 schrieb Icenowy Zheng:
> > > > 在 2024-06-17星期一的 14:35 +0200，Christian König写道：
> > > > > Am 17.06.24 um 12:58 schrieb Icenowy
From: Likun Gao
Add support to init TA firmware for psp v14.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
index cc0248efa6b6..4d33c95
On Mon, Jun 17, 2024 at 3:14 PM Aurabindo Pillai
wrote:
>
> From: Likun Gao
>
> Add support to init TA firmware for psp v14.
>
> Signed-off-by: Likun Gao
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/driver
Add the necessary register definitions to enable DCC on DCN4x
Signed-off-by: Aurabindo Pillai
---
.../include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 110 ++
1 file changed, 110 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h
b/drivers/gpu/dr
Add registers and entry points to enable DCC on DCN4x
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 11 +
drivers/gpu/drm/amd/display/dc/dc.h | 4 +
.../drm/amd/display/dc/dml2/dml2_wrapper.
[AMD Official Use Only - AMD Internal Distribution Only]
Ping on this...
Thanks,
Jane
-Original Message-
From: Jane Jian
Sent: Monday, June 17, 2024 6:11 PM
To: Lazar, Lijo ; Chang, HaiJun ;
Zhao, Victor
Cc: amd-gfx@lists.freedesktop.org; Jian, Jane
Subject: [PATCH] drm/amdgpu: normal
[AMD Official Use Only - AMD Internal Distribution Only]
@Lazar, Lijo Can you help to review the code?
Thanks
-Original Message-
From: Jian, Jane
Sent: Tuesday, June 18, 2024 10:37 AM
To: Jian, Jane ; Lazar, Lijo ; Chang,
HaiJun ; Zhao, Victor
Cc: amd-gfx@lists.freedesktop.org; Ma, Qin
On Fri, Jun 07, 2024 at 03:04:55PM +0800, Zhang, Julia wrote:
> Instead of using state->fb->obj[0] directly, get object from framebuffer
> by calling drm_gem_fb_get_obj() and return error code when object is
> null to avoid using null object of framebuffer.
>
> Signed-off-by: Julia Zhang
Reviewe
AMD hardware can do async flips with overlay planes, but currently there's no
easy way to enable that in DRM. To solve that, this patchset creates a new
drm_plane field, bool async_flip, that allows drivers to choose which plane can
or cannot do async flips. This is latter used on drm_atomic_set_pr
Allow userspace to use explicit synchronization with atomic async flips.
That means that the flip will wait for some hardware fence, and then
will flip as soon as possible (async) in regard of the vblank.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++-
1 file changed
Drivers have different capabilities on what plane types they can or
cannot perform async flips. Create a plane::async_flip field so each
driver can choose which planes they allow doing async flips.
Signed-off-by: André Almeida
---
include/drm/drm_plane.h | 5 +
1 file changed, 5 insertions(+
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_p
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++
drivers/gpu/drm/i915/display/skl_universal_plane.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drive
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/vc4/vc4_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 07caf2a47c6c..e3d41d
Replace the generic "is this plane primary" for a plane::async_flip
check, so DRM follows the plane restrictions set by the driver.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomi
amdgpu can handle async flips on overlay planes, so mark it as true
during the plane initialization.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.
Am 17.06.24 um 18:09 schrieb Icenowy Zheng:
BTW is there any operation that could be taken to examine this specific
workaround?
Is there any case possible to reproduce?
No idea, I mean that's for GFX7/8 which was released between 2013 and 2017.
My educated guess is that you could create a tes
Add variable to record the deferred error
number read by driver.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 62 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +-
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 4 +-
3 files changed, 48 insertions
In order to apply to the case where a large number
of ras poison interrupts:
1. Change to use variable to record poison creation
requests to avoid fifo full.
2. Prioritize handling poison creation requests
instead of following the order of requests
received by the driver.
Signed-off-by: Y
1. The poison fifo is only used for poison consumption
requests.
2. Merge reset requests when poison fifo caches multiple
poison consumption messages
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 58 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umc
Add gpu reset check and exception handling for
page retirement.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 43 +
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
Add completion to wait for ras reset to complete.
Signed-off-by: YiPeng Chai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/am
53 matches
Mail list logo
