Am 12.06.24 um 14:45 schrieb gre...@linuxfoundation.org:
This is a note to let you know that I've just added the patch titled
Revert "drm/amdgpu: init iommu after amdkfd device init"
to the 5.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/
m-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20240613051700.1112-1-mario.limonciello%40amd.com
patch subject: [PATCH v3] drm/fb-helper: Detect when lid is closed during
initialization
config: sparc-randconfig-001-20240614
(https://download.01.org/0day-ci/archiv
Hi Mario
Am 13.06.24 um 07:17 schrieb Mario Limonciello:
If the lid on a laptop is closed when eDP connectors are populated
then it remains enabled when the initial framebuffer configuration
is built.
When creating the initial framebuffer configuration detect the
lid status and if it's closed d
if (domain & abo->preferred_domains &
AMDGPU_GEM_DOMAIN_VRAM &&
- !(adev->flags & AMD_IS_APU))
- places[c].flags |= TTM_PL_FLAG_FALLBACK;
+ !(adev->flags & AMD_IS_APU)) {
+ /*
+ * When GTT is just an alternative to VRAM make sur
[WHY]
sriov has the higher bit violation when flushing tlb
[HOW]
for sriov only init XCC0(lower 16-bit) for all XCCs to avoid higher bit
violation
since kiq ring is always local, local address without XCC ID is enough to be
sent to the XCC KIQ
Signed-off-by: Jane Jian
---
drivers/gpu/drm/amd/
On 6/14/2024 4:40 PM, Jane Jian wrote:
> [WHY]
> sriov has the higher bit violation when flushing tlb
>
> [HOW]
> for sriov only init XCC0(lower 16-bit) for all XCCs to avoid higher bit
> violation
> since kiq ring is always local, local address without XCC ID is enough to be
> sent to the XC
On 6/14/2024 03:15, Thomas Zimmermann wrote:
Hi Mario
Am 13.06.24 um 07:17 schrieb Mario Limonciello:
If the lid on a laptop is closed when eDP connectors are populated
then it remains enabled when the initial framebuffer configuration
is built.
When creating the initial framebuffer configurat
Hi
Am 14.06.24 um 15:47 schrieb Mario Limonciello:
On 6/14/2024 03:15, Thomas Zimmermann wrote:
Hi Mario
Am 13.06.24 um 07:17 schrieb Mario Limonciello:
If the lid on a laptop is closed when eDP connectors are populated
then it remains enabled when the initial framebuffer configuration
is bui
On 6/14/2024 09:17, Thomas Zimmermann wrote:
Hi
Am 14.06.24 um 15:47 schrieb Mario Limonciello:
On 6/14/2024 03:15, Thomas Zimmermann wrote:
Hi Mario
Am 13.06.24 um 07:17 schrieb Mario Limonciello:
If the lid on a laptop is closed when eDP connectors are populated
then it remains enabled whe
AMD hardware can do async flips with overlay planes, but currently there's no
easy way to enable that in DRM. To solve that, this patchset creates a new
drm_plane field, bool async_flip, that allows drivers to choose which plane can
or cannot do async flips. This is latter used on drm_atomic_set_pr
Allow userspace to use explicit synchronization with atomic async flips.
That means that the flip will wait for some hardware fence, and then
will flip as soon as possible (async) in regard of the vblank.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++-
1 file changed
Drivers have different capabilities on what plane types they can or
cannot perform async flips. Create a plane::async_flip field so each
driver can choose which planes they allow doing async flips.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
include/drm/drm_plane
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drive
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/vc4/vc4_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 07caf2a47c6c..e3d41d
amdgpu can handle async flips on overlay planes, so mark it as true
during the plane initialization.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0279c
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_p
On 2024-06-13 18:22, Nathan Chancellor wrote:
> Hi Palmer (and AMD folks),
>
> On Tue, Jun 04, 2024 at 09:04:23AM -0700, Palmer Dabbelt wrote:
>> On Mon, 03 Jun 2024 15:29:48 PDT (-0700), nat...@kernel.org wrote:
>>> On Thu, May 30, 2024 at 07:57:42AM -0700, Palmer Dabbelt wrote:
From: Pal
On 14/06/2024 10:53, Christian König wrote:
if (domain & abo->preferred_domains &
AMDGPU_GEM_DOMAIN_VRAM &&
- !(adev->flags & AMD_IS_APU))
- places[c].flags |= TTM_PL_FLAG_FALLBACK;
+ !(adev->flags & AMD_IS_APU)) {
+ /*
+ * Wh
The attribute is not helpful if commented out.
Cc: Tasos Sahanidis
Fixes: c6c4dd540125 ("drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds")
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/include/pptable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
This attribute is used to hint the length of flexible arrays to
compiler and sanitizers.
Signed-off-by: Mario Limonciello
---
.../drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h | 36 +-
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h | 38 +--
2 files changed, 37 inserti
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Mario
> Limonciello
> Sent: Friday, June 14, 2024 1:06 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Limonciello, Mario ; Tasos Sahanidis
>
> Subject: [PATCH 1/2] drm/amdgpu/pptable: Fix __counted_by attribute
>
> The attribute is
On Fri, Jun 14, 2024 at 12:35:29PM GMT, André Almeida wrote:
> Drivers have different capabilities on what plane types they can or
> cannot perform async flips. Create a plane::async_flip field so each
> driver can choose which planes they allow doing async flips.
>
> Signed-off-by: André Almeida
On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote:
> AMD hardware can do async flips with overlay planes, but currently there's no
> easy way to enable that in DRM. To solve that, this patchset creates a new
> drm_plane field, bool async_flip, that allows drivers to choose which plane
>
On Fri, Jun 14, 2024 at 1:42 PM Mario Limonciello
wrote:
>
> This attribute is used to hint the length of flexible arrays to
> compiler and sanitizers.
>
> Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
> ---
> .../drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h | 36 +-
>
v3.x changed the how vram width was encoded. The previous
implementation actually worked correctly for most boards.
Fix the implementation to work correctly everywhere.
This fixes the vram width reported in the kernel log on
some boards.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdg
On Tue, Jun 11, 2024 at 12:42 AM Li Ma wrote:
>
> [Why]
> SMU firmware has not supported MALL PG.
>
> [How]
> Disable MALL PG and make it always on until SMU firmware is ready.
>
> Signed-off-by: Li Ma
> Reviewed-by: Tim Huang
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgp
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Jane Jian
Sent: Tuesday, June 11, 2024 6:06 AM
To: Chen, JingWen (Wayne)
Cc: amd-gfx@lists.freedesktop.org ; Jian, Jane
Subject: [PATCH] drm/amdgpu/vcn: port mmsch ctx table size fix from jpeg v4
ad
Adds bounds check for sumo_vid_mapping_entry.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3392
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
b/drivers/gpu/dr
Adds bounds check for sumo_vid_mapping_entry.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/sumo_dpm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index 21d27e6235f3..b11f7c5bbcbe 100644
--- a/drivers/gpu/d
On Fri, Jun 14, 2024 at 12:35:32PM -0300, André Almeida wrote:
> This driver can perfom async flips on primary planes, so enable it.
>
Cc: Ville Syrjälä
Cc: Naveen Kumar
c: Vandita Kulkarni
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++
> 1 file ch
Hi Dmitry,
Em 14/06/2024 14:32, Dmitry Baryshkov escreveu:
On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote:
AMD hardware can do async flips with overlay planes, but currently there's no
easy way to enable that in DRM. To solve that, this patchset creates a new
drm_plane field, bool
On 6/14/2024 13:33, Alex Deucher wrote:
Adds bounds check for sumo_vid_mapping_entry.
Signed-off-by: Alex Deucher
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/radeon/sumo_dpm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm
On 6/14/2024 13:33, Alex Deucher wrote:
Adds bounds check for sumo_vid_mapping_entry.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3392
Signed-off-by: Alex Deucher
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 ++
1 file changed, 2 insertions
Em 14/06/2024 14:32, Dmitry Baryshkov escreveu:> On Fri, Jun 14, 2024 at
12:35:29PM GMT, André Almeida wrote:
>> Drivers have different capabilities on what plane types they can or
>> cannot perform async flips. Create a plane::async_flip field so each
>> driver can choose which planes they allow
(!ARM64 ||
!CC_IS_CLANG)
+ select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT && !(CC_IS_CLANG &&
(ARM64 || RISCV))
help
Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and
---
base-c
SRIOV does not need to wait for IFWI init, and MP0_C2PMSG_33 is blocked
for VF access.
Signed-off-by: Victor Lu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 26 ++-
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.
This reverts commit aa68f57443c5aed125079ae66fef0e9fd7008b33.
This is causing a BUG message during suspend.
[ 61.603542] BUG: sleeping function called from invalid context at
kernel/locking/mutex.c:283
[ 61.603550] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 2028,
name: kworker/u
[AMD Official Use Only - AMD Internal Distribution Only]
Series is:
Reviewed-by: Mukul Joshi
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Monday, June 3, 2024 5:03 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 3/3] drm/amd
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Vignesh Chander
From: Victor Lu
Sent: Friday, June 14, 2024 4:32:21 p.m.
To: amd-gfx@lists.freedesktop.org
Cc: Chander, Vignesh ; Lu, Victor Cheng Chi (Victor)
Subject: [PATCH] drm/amdgpu:
[AMD Official Use Only - AMD Internal Distribution Only]
Never mind, bit 16 and above is probably because of dword aligned offset.
Any reason not to do this in kiq/rlc based writes to normalise all?
Thanks,
Lijo
From: Lazar, Lijo
Sent: Friday, June 14, 2024 5:20:
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