[Public]
>-Original Message-
>From: Lazar, Lijo
>Sent: Wednesday, May 22, 2024 12:57 PM
>To: Zhang, Jesse(Jie) ; amd-
>g...@lists.freedesktop.org
>Cc: Deucher, Alexander ; Koenig, Christian
>; Huang, Tim ; Yu, Lang
>
>Subject: Re: [PATCH 1/4 V2] drm/amdgpu: fix invadate operation for umsc
Add gfx queue register for all instances in devcoredump
for gfx10.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 90 +
2 files changed, 91 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/am
Add support to dump registers of all instances of
cp queue registers of gfx10 to devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 116 +++-
2 files changed, 113 insertions(+), 4 deletions(-
Add support of gfx11 ipdump print so devcoredump
could trigger it to dump the captured registers
in devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu
Add general registers of gfx11 in ipdump for
devcoredump support.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 107 -
1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/a
IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.
Signed-off-by: Sunil Khatri
---
.../gpu/drm/amd/include/asic_
add prints before and after ip registers are
dump. It avoids user to think of system being
stuck/hung as register dump takes time after a
gpu hang.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd
Add gfx11 support of CP queue registers for all queues
to be used by devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 111 -
1 file changed, 109 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/driv
Add support of all the CP GFX queues for gfx11 ipdump
to be used by devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/drivers/gpu/drm/amd/am
Rename the memory pointer from ip_dump to ip_dump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 +++--
Adding more device information:
a. PCI info
b. VRAM and GTT info
c. GDC config
Also correct the print layout and section information for
in devcoredump.
Signed-off-by: Sunil Khatri
---
.../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 21 +--
1 file changed, 19 insertions(+), 2 de
With this support for gfx10 and gfx11 ipdump is complete.
Also added dev_info needed fields for devcoredump.
Sunil Khatri (10):
drm/amdgpu: rename the ip_dump to ip_dump_core
drm/amdgpu: Add cp queues support fro gfx10 in ipdump
drm/amdgpu: add gfx queue support of gfx10 in ipdump
drm/amdg
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Lijo,
This patch alone is not working.
Since in your approach amdgpu_virt_rlcg_reg_rw is taking logical xcc id, so all
the read/write calls need to be fixed with it.
For example, WREG32_SOC15_OFFSET. There will be bunch of places need t
Hi, Thorsten here, the Linux kernel's regression tracker. Top-posting
for once, to make this easily accessible to everyone.
Hmm, from here it looks like the patch now that it was reviewed more
that a week ago is still not even in -next. Is there a reason?
I know, we are in the merge window. But a
Am Di., 21. Mai 2024 um 16:00 Uhr schrieb Mario Limonciello
:
>
> On 5/21/2024 08:43, Simon Ser wrote:
> > This makes sense to me in general. I like the fact that it's simple and
> > vendor-neutral.
> >
> > Do we want to hardcode "panel" in the name? Are we sure that this will
> > ever only apply t
Am Di., 21. Mai 2024 um 19:28 Uhr schrieb Leo Li :
>
>
>
> On 2024-05-21 12:21, Mario Limonciello wrote:
> > On 5/21/2024 11:14, Xaver Hugl wrote:
> >> Am Di., 21. Mai 2024 um 16:00 Uhr schrieb Mario Limonciello
> >> :
> >>>
> >>> On 5/21/2024 08:43, Simon Ser wrote:
> This makes sense to me i
What is already there in debugfs is 'bpc' and 'colorspace', but not
the pixel encoding/format.
I have searched high and low for that to be able to verify that my
monitor and computer are using my preferred combination of all those
three values.
I do think it should be available as a standard DRM C
Am 20.05.24 um 18:22 schrieb Alex Deucher:
On Sat, May 18, 2024 at 8:17 PM Armin Wolf wrote:
Am 17.05.24 um 03:30 schrieb Barry Kauler:
Armin, Yifan, Prike,
I will top-post, so you don't have to scroll down.
After identifying the commit that causes black screen with my gpu, I
posted the resu
On 5/22/2024 1:11 PM, Zhao, Victor wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Hi Lijo,
>
> This patch alone is not working.
> Since in your approach amdgpu_virt_rlcg_reg_rw is taking logical xcc id, so
> all the read/write calls need to be fixed with it.
> For examp
On 22/05/2024 08:25, Dmitry Baryshkov wrote:
Fix sparse warning regarding symbol 'sw43408_backlight_ops' not being
declared.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/202404200739.hbwzvohr-...@intel.com/
Reviewed-by: Neil Armstrong
Fixes: 069a6c0e94f9 ("drm:
On 22/05/2024 08:25, Dmitry Baryshkov wrote:
This panel driver uses DSC PPS functions and as such depends on the
DRM_DISPLAY_DP_HELPER. Select this symbol to make required functions
available to the driver.
Reported-by: kernel test robot
Closes:
https://lore.kernel.org/oe-kbuild-all/2024042008
+ Simon
On 5/22/2024 05:07, Rino André Johnsen wrote:
To be perfectly honest with you, I haven't given that much though. I
used the 'bpc' and 'colorspace' property in debugfs, since I could not
find that information anywhere else. And since I also needed to verify
the pixel encoding being used,
On Wednesday, May 22nd, 2024 at 15:36, Mario Limonciello
wrote:
> > To be perfectly honest with you, I haven't given that much though. I
> > used the 'bpc' and 'colorspace' property in debugfs, since I could not
> > find that information anywhere else. And since I also needed to verify
> > the p
On Wed, May 22, 2024 at 3:30 AM Sunil Khatri wrote:
>
> add prints before and after ip registers are
> dump. It avoids user to think of system being
> stuck/hung as register dump takes time after a
> gpu hang.
>
> Signed-off-by: Sunil Khatri
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2
On Wed, May 22, 2024 at 3:30 AM Sunil Khatri wrote:
>
> With this support for gfx10 and gfx11 ipdump is complete.
> Also added dev_info needed fields for devcoredump.
A few comments on patch 4. The rest are:
Reviewed-by: Alex Deucher
>
> Sunil Khatri (10):
> drm/amdgpu: rename the ip_dump to
Series is:
Reviewed-by: Alex Deucher
On Wed, May 22, 2024 at 1:47 AM Shane Xiao wrote:
>
> This patch changes the implementation of AMDGPU_PTE_MTYPE_VG10,
> clear the bits before setting the new one.
>
> Suggested-by: Alex Deucher
> Signed-off-by: longlyao
> Signed-off-by: Shane Xiao
> ---
>
The fix involves adding a null check for 'stream' at the beginning of
the function. If 'stream' is NULL, the function immediately returns
false. This ensures that 'stream' is not NULL when we dereference it to
access 'ctx' in 'dc = stream->ctx->dc;' the function.
Fixes the below:
drivers/g
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 8314289a8d50a4e05d8ece1ae0445a3b57bb4d3b Add linux-next specific
files for 20240522
Error/Warning: (recently discovered and may have been fixed)
m68k-linux-ld: regmap-spi.c:(.text+0x272
From: Likun Gao
Remove hdp flush for gc v11/12 when enable gart.
Remove flush tlb for gc v10/11/12 when enable gart.
Signed-off-by: Likun Gao
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 ---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 ---
drivers/gpu/drm/amd/amdg
Random accesses to the GPU while it is not re-initialized can lead to a
bad time. So add a rwsem to prevent such accesses. Normal accesses will
now take the read lock for shared GPU access, reset takes the write lock
for exclusive GPU access.
Care need to be taken so that the recovery thread does
At this point the gart is not set up, there's no point to invalidate tlb
here and it could even be harmful.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/d
When amdgpu_gart_invalidate_tlb helper is introduced this part was left
out of the conversion. Avoid the code duplication here.
Signed-off-by: Yunxiang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
On 2024-05-22 11:36, Srinivasan Shanmugam wrote:
> The fix involves adding a null check for 'stream' at the beginning of
> the function. If 'stream' is NULL, the function immediately returns
> false. This ensures that 'stream' is not NULL when we dereference it to
> access 'ctx' in 'dc = stream-
Hi Dave, Sima,
Fixes for 6.10.
The following changes since commit 5a5a10d9db77939a22e1d65fc0a4ba6b5d8f4fce:
drm/buddy: Fix the warn on's during force merge (2024-05-20 06:42:12 +1000)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes
On GFXIP9.4.3, make CPX mode as the default compute mode if the node is
setup in NPS4 memory partition mode. This change is only applicable for
dGPU, for APU, continue to use TPX mode.
Cc: Lijo Lazar
Signed-off-by: Rajneesh Bhardwaj
---
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 2 +-
1 file
On 2024-05-19 09:02, Mario Limonciello wrote:
> Errors in amdgpu_dm_init() are silently ignored and dm_hw_init()
> will succeed. However often these are fatal errors and it would
> be better to pass them up.
>
> Signed-off-by: Mario Limonciello
Reviewed-by: Harry Wentland
Harry
> ---
> drive
The `power saving policy` DRM property is an optional property that
can be added to a connector by a driver.
This property is for compositors to indicate intent of policy of
whether a driver can use power saving features that may compromise
the experience intended by the compositor.
Signed-off-by
When the `power_saving_policy` property is set to bit mask
"Require color accuracy" ABM should be disabled immediately and
any requests by sysfs to update will return an -EBUSY error.
When the `power_saving_policy` property is set to bit mask
"Require low latency" PSR should be disabled.
When the
During the Display Next hackfest 2024 one of the topics discussed
was the need for compositor to be able to relay intention to drivers
that color fidelity is preferred over power savings.
To accomplish this a new optional DRM property is being introduced called
"power saving policy". This propert
During the Display Next hackfest 2024 one of the topics discussed
was the need for compositor to be able to relay intention to drivers
that color fidelity or low latency is preferred over power savings.
To accomplish this a new optional DRM property is being introduced called
"power saving policy"
---
lib/igt_kms.c | 26 ++
lib/igt_kms.h | 6 ++
2 files changed, 32 insertions(+)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index af63d13b1..4ce5e4a95 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -6581,3 +6581,29 @@ int get_num_scalers(int drm_fd, enum pipe pip
Verify that the property has disabled PSR
---
tests/amdgpu/amd_psr.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/tests/amdgpu/amd_psr.c b/tests/amdgpu/amd_psr.c
index 9da161a09..a9f4a6aa5 100644
--- a/tests/amdgpu/amd_psr.c
+++ b/tests/amdgpu/amd
From: Mario Limonciello
In order to bubble of cases of expeted errors on set_abm_level()
change the return type to int.
Signed-off-by: Mario Limonciello
---
tests/amdgpu/amd_abm.c | 33 +++--
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/tests/amdg
From: Mario Limonciello
When the "panel power saving" property is set to forbidden the
compositor has indicated that userspace prefers to have color
accuracy and fidelity instead of power saving.
Verify that the sysfs file behaves as expected in this situation.
Signed-off-by: Mario Limonciello
Hi Dmitry,
On 21/05/24 12:39, Vignesh Raman wrote:
Hi Dmitry,
On 20/05/24 16:32, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 02:54:59PM +0530, Vignesh Raman wrote:
With latest IGT, the tests tries to load the module and it
fails. So build the virtual GPU driver for virtio as module.
Why
Hi Dmitry,
On 20/05/24 16:13, Dmitry Baryshkov wrote:
On Fri, May 17, 2024 at 02:54:57PM +0530, Vignesh Raman wrote:
zlib.net is not allowing tarball download anymore and results
in below error in kernel+rootfs_arm32 container build,
urllib.error.HTTPError: HTTP Error 403: Forbidden
urllib.erro
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
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