[AMD Official Use Only - General]
Looks good to me.
Reviewed-by: Veerabadhran Gopalakrishnan
Regards,
Veera
-Original Message-
From: Jamadar, Saleemkhan
Sent: Wednesday, January 31, 2024 1:23 PM
To: Zhang, Yifan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Gopalakrishnan,
Hi Mario,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rafael-pm/linux-next]
[also build test WARNING on rafael-pm/acpi-bus linus/master v6.8-rc2
next-20240131]
[cannot apply to drm-misc/drm-misc-next rafael-pm/devprop]
[If your patch is applied to the
Hi Mario,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rafael-pm/linux-next]
[also build test WARNING on rafael-pm/acpi-bus linus/master v6.8-rc2
next-20240131]
[cannot apply to drm-misc/drm-misc-next rafael-pm/devprop]
[If your patch is applied to the
On 2024/1/30 22:23, Christian König wrote:
> Am 30.01.24 um 12:16 schrieb Daniel Vetter:
>> On Tue, Jan 30, 2024 at 12:10:31PM +0100, Daniel Vetter wrote:
>>> On Mon, Jan 29, 2024 at 06:31:19PM +0800, Julia Zhang wrote:
As vram objects don't have backing pages and thus can't implement
d
Hi Mario,
kernel test robot noticed the following build errors:
[auto build test ERROR on rafael-pm/linux-next]
[also build test ERROR on rafael-pm/acpi-bus linus/master v6.8-rc2
next-20240131]
[cannot apply to drm-misc/drm-misc-next rafael-pm/devprop]
[If your patch is applied to the wrong git
Problem:
The computer in the bios initialization process, unplug the HDMI display,
wait until the system up, plug in the HDMI display, did not enter the
hotplug interrupt function, the display is not bright.
Fix:
After the above problem occurs, and the hpd ack interrupt bit is 1,
the interrupt sho
Am 30.01.24 um 21:08 schrieb Felix Kuehling:
The reservation is there to catch NULL pointer dereferences from the
GPU. Reduce the size to 64KB to make sure that shared virtual address
programming models can map all CPU-accessible virtual addresses for GPU
access. This is also the default for CPU
Am 30.01.24 um 21:08 schrieb Felix Kuehling:
The TBA and TMA, along with an unused IB allocation, reside at low
addresses in the VM address space. A stray VM fault which hits these
pages must be serviced by making their page table entries invalid.
The scheduler depends upon these pages being r
Skip the debugfs file creation for mes event log if the GPU
doesn't use MES. This to prevent potential kernel oops when
user try to read the event log in debugfs on a GPU without MES
Signed-off-by: shaoyunl
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 +++---
1 file changed, 3 insertions(+),
Am 31.01.24 um 11:20 schrieb Zhang, Julia:
On 2024/1/30 22:23, Christian König wrote:
Am 30.01.24 um 12:16 schrieb Daniel Vetter:
On Tue, Jan 30, 2024 at 12:10:31PM +0100, Daniel Vetter wrote:
[SNIP]
Hi Sima, Christian,
Yeah, that is really just speculative. All importers need to set the pe
Hi Mario,
kernel test robot noticed the following build warnings:
[auto build test WARNING on rafael-pm/linux-next]
[also build test WARNING on rafael-pm/acpi-bus linus/master v6.8-rc2
next-20240131]
[cannot apply to drm-misc/drm-misc-next rafael-pm/devprop]
[If your patch is applied to the
From: Christian König
The callback we installed for the SDMA update were actually pretty
horrible. since we now have seq64 use that one and HW seq writes
instead.
V2:(Shashank)
- rebased on amd-drm-staging-next
- changed amdgpu_seq64_gpu_addr
Cc: Christian König
Cc: Alex Deucher
Cc: Felix K
This patch:
- Attaches the TLB flush fence to the PT objects being freed
- Adds a new ptr in VM to save this last TLB flush fence
- Adds a new lock in VM to prevent out-of-context update of saved
TLB flush fence
- Adds a new ptr in tlb_flush structure to save vm
The idea is to delay freeing of p
From: Christian König
The problem is that when (for example) 4k pages are replaced
with a single 2M page we need to wait for change to be flushed
out by invalidating the TLB before the PT can be freed.
Solve this by moving the TLB flush into a DMA-fence object which
can be used to delay the free
On 30/01/2024 19:48, Arunpravin Paneer Selvam wrote:
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each block as cleared.
- Track the available cleared pages siz
On 30/01/2024 20:30, Arunpravin Paneer Selvam wrote:
Hi Matthew,
On 12/21/2023 12:51 AM, Matthew Auld wrote:
Hi,
On 14/12/2023 13:42, Arunpravin Paneer Selvam wrote:
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks i
Call the 2nd level trap handler if the cwsr handler is entered with any
one of wave_state, wave_end, or trap_after_inst exceptions.
Signed-off-by: Laurent Morichetti
Tested-by: Lancelot Six
---
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2 +-
.../drm/amd/amdkfd/cwsr_trap_handler_gfx10.a
From: Michael Strauss
[WHY]
Only required if FIXED_VS retimer does not support DP2-capable.
[HOW]
Gate link rate toggle with DP 128b/132b LTTPR channel coding cap check.
Reviewed-by: Charlene Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Michael Strauss
---
.../link_dp_training_fixed_vs_pe_ret
This version brings along the following:
* DCN35 fixes
* DMUB fixes
* Link training fixes
* Misc code style fixes
* MST fixes
* ODM fixes
* SubVP fixes
Allen Pan (1):
drm/amd/display: correct static screen event mask
Alvin Lee (2):
Revert "drm/amd/display: For FPO and SubVP/DRR configs progra
From: Allen Pan
[Why]
Hardware register definition changed
Reviewed-by: Charlene Liu
Acked-by: Hamza Mahfooz
Signed-off-by: Allen Pan
---
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 21 +--
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 3 +++
.../amd/display/dc/hwss/dc
From: Michael Strauss
The New sequence has been in use in DCN314 with no regressions
introduced. Therefore, it is safe to enable this sequence for all
devices using FIXED_VS retimers. So, remove the legacy codepath and its
associated config flag.
Reviewed-by: Ovidiu Bunea
Acked-by: Hamza Mahfoo
From: Wenjing Liu
[why]
When populating dml pipes, odm combine policy should be assigned based
on the pipe topology of the context passed in. DML pipes could be
repopulated multiple times during single validate bandwidth attempt. We
need to make sure that whenever we repopulate the dml pipes it i
From: Nicholas Kazlauskas
[Why]
Any interface that touches registers needs to wake up the system.
[How]
Add a new interface dc_exit_ips_for_hw_access that wraps the check
for IPS support and insert it into the public DC interfaces that
touch registers.
We don't re-enter, since we expect that th
From: Nicholas Kazlauskas
[Why]
Workaroud for a race condition where DMCUB is in the process of
committing to IPS1 during the handshake causing us to miss the
transition into IPS2 and touch the INBOX1 RPTR causing a HW hang.
[How]
Disable the reallow to ensure that we have enough of a gap betwee
From: Nicholas Kazlauskas
[Why]
To match firmware measurements and avoid hanging when accessing HW
that's in idle.
[How]
Increase the delays to what we've measured.
Reviewed-by: Ovidiu Bunea
Acked-by: Hamza Mahfooz
Signed-off-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/dc/resource/d
From: George Shen
[Why]
Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM
pipesplit is used, pixels on the left edge of ODM slices need one extra
pixel from the right edge of the previous slice to calculate the correct
chroma value.
Without this change, the chroma value is sl
From: George Shen
[Why]
Default driver behaviour is 3-tap subsampling, so we should keep
it the same for test patterns as well. However, it is also useful
to force 1-tap subsampling for testing purposes.
Reviewed-by: Michael Strauss
Acked-by: Hamza Mahfooz
Signed-off-by: George Shen
---
driv
From: Nicholas Kazlauskas
[Why]
We're still missing a few and we'd like to avoid continuining when
a hang occurs for debug purposes.
[How]
Add the loop anywhere we try to wait on rptr == wptr in dc_dmub_srv.
Reviewed-by: Ovidiu Bunea
Acked-by: Hamza Mahfooz
Signed-off-by: Nicholas Kazlauskas
From: Ethan Bitnun
Add a small delay before reading clks from hw, to ensure correct values
are used for logging.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Ethan Bitnun
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 ++
1 file changed, 2 insertions(+)
From: Camille Cho
0 nits is a valid default value for OLED panels. So, update the relevant
comment to account for that fact.
Reviewed-by: Krunoslav Kovac
Signed-off-by: Camille Cho
---
.../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 2 +-
1 file changed, 1 insertion(+), 1 de
From: Fangzhi Zuo
The change try to fix below error specific to RV platform:
BUG: kernel NULL pointer dereference, address: 0008
PGD 0 P4D 0
Oops: [#1] PREEMPT SMP NOPTI
CPU: 4 PID: 917 Comm: sway Not tainted 6.3.9-arch1-1 #1
124dc55df4f5272ccb409f39ef4872fc2b3376a2
Hardware na
From: Ethan Bitnun
Update the p_state type before update_clocks is called to ensure
accurate values are used for logging.
Reviewed-by: Alvin Lee
Acked-by: Hamza Mahfooz
Signed-off-by: Ethan Bitnun
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 22 +++---
1 file changed, 11 in
From: Alvin Lee
This reverts commit af89970ba286ef0237b971f28721b0d3d0d6b794.
Since, it was causing regression for some DRR scenarios.
Reviewed-by: Aric Cyr
Reviewed-by: Nevenko Stupar
Acked-by: Hamza Mahfooz
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 45 +
From: Rodrigo Siqueira
Display code keeps getting improvements, and because of that, some
legacy code is left behind. This commit drops some of those unused
codes.
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
.../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 4
.../amd/di
From: Rodrigo Siqueira
Just ensure that ODM optimization is disabled by default.
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/resour
From: Rodrigo Siqueira
Just adjust the code indentation in the header and add a simple comment
in the dm_cp_psp file.
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.h | 3 +--
drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
From: Alvin Lee
Previously we would call apply_ctx_to_hw to enable and disable
phantom pipes. However, apply_ctx_to_hw can potentially update
non-phantom pipes as well which is undesired. Instead of calling
apply_ctx_to_hw as a whole, call the relevant helpers for each
phantom pipe when enabling
From: Rodrigo Siqueira
Some of the CONFIG_DRM_AMD_DC_FP was added in some non-related FPU code,
which may cause confusion. This commit dropped some of the unnecessary
guards.
Acked-by: Hamza Mahfooz
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
From: Aric Cyr
This version brings along the following:
- DCN35 fixes
- DMUB fixes
- Link training fixes
- Misc code style fixes
- MST fixes
- ODM fixes
- SubVP fixes
Acked-by: Hamza Mahfooz
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+)
On 1/31/2024 12:50, Laurent Morichetti wrote:
> Call the 2nd level trap handler if the cwsr handler is entered with any
> one of wave_state, wave_end, or trap_after_inst exceptions.
^ wave_start
A more descriptive title would be helpful. Perhaps something like "Pass debug
exceptions to second-l
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