Hi
Am 01.12.23 um 03:36 schrieb Sui Jingfeng:
Hi,
On 2023/11/28 18:45, Thomas Zimmermann wrote:
The udl driver is the only caller of drm_plane_helper_atomic_check().
Move the function into the driver. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_plane_he
Thomas Zimmermann writes:
Hello Thomas,
> Remove unnecessary include statements for .
> The file contains helpers for non-atomic code and should not be
> required by most drivers. No functional changes.
>
> Signed-off-by: Thomas Zimmermann
> ---
> drivers/gpu/drm/solomon/ssd130x.h | 1 -
> 1 f
zhuweixi writes:
> Glad to know that there is a common demand for a new syscall like
> hmadvise(). I expect it would also be useful for homogeneous NUMA
> cases. Credits to cudaMemAdvise() API which brought this idea to
> GMEM's design.
It's not clear to me that this would need to be a new sys
"Zeng, Oak" writes:
> See inline comments
>
>> -Original Message-
>> From: dri-devel On Behalf Of
>> zhuweixi
>> Sent: Thursday, November 30, 2023 5:48 AM
>> To: Christian König ; Zeng, Oak
>> ; Christian König ; linux-
>> m...@kvack.org; linux-ker...@vger.kernel.org; a...@linux-founda
[AMD Official Use Only - General]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Friday, December 1, 2023 15:37
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
Subject: [PATCH 3/3] drm/amdgpu: Avoid querying
Am 01.12.23 um 06:48 schrieb Zeng, Oak:
[SNIP]
3. MMU notifiers register hooks at certain core MM events, while GMEM
declares basic functions and internally invokes them. GMEM requires less from
the driver side -- no need to understand what core MM behaves at certain MMU
events. GMEM also exp
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Enable writeback.
* Add multiple fixes for DML2 and DCN35.
* Introduce small code style adjustments.
Cc: Daniel Wheeler
Thanks
Siqueira
Alex Hung (12):
drm/amd/display: Avoid virtual stream encoder if not ex
From: Relja Vojvodic
[why]
When querying DML for a vlevel after pipes have been split or merged the
ODM policy would revert to a default policy, which could cause the query
to use the incorrect ODM status. In this case ODM 2to1 was validated,
but the last DML query would assume no ODM and return
From: Charlene Liu
Fix issue when override level bigger than default. Levels 5, 6, and 7
had zero stutter latency, this is because override level being
initialized after stutter latency inits.
Reviewed-by: Syed Hassan
Reviewed-by: Allen Pan
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene L
From: Alvin Lee
Optimize fast validation cases to only validate the highest voltage
level. This works because during fast validation we only care if the
mode can be supported or not (at any vlevel).
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
.../dc/dml/dcn3
From: Michael Strauss
[WHY]
Many DCN generations only have two HPO link encoders and therefore only
support driving a max of two DP2 PHYs. DP2 MST hubs currently can not
pass 3x display validation as each downstream sink is enumerated as
separate DP2 output.
[HOW]
Count MST hubs once by treating
From: Lewis Huang
[Why]
OTG inst and pwrseq inst mapping is not align therefore we cannot use
otg_inst as pwrseq inst to get DCIO register.
[How]
1. Pass the correct pwrseq instance to dmub when set abm pipe.
2. LVTMA control index change from panel_inst to pwrseq_inst.
Reviewed-by: Phil Hsieh
From: Krunoslav Kovac
We use spatial dither by default for all output bpc (6/8/10). While it
makes some sense for FP16, for ARGB2101010 surfaces it makes little
sense as even if we skip color pipeline to preserve bit accuracy,
spatial dither adds random noise so a few percent pixels are 1 bit off
From: Daniel Miess
[Why]
Some registers needed for root clock gating in dcn35 are not defined in
the dccg header.
[How]
Add the needed registers and temporarily disable some register writes
that are now taking place successfully until the registers can be
properly enabled.
Reviewed-by: Charlene
From: Josip Pavic
[Why]
Larger data blocks are expected to be transferred between driver and FW
in the future.
[How]
Embiggen the scratch buffer to a cromulent size.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Josip Pavic
---
drivers/gpu/drm/amd/display/dmub/s
From: Alvin Lee
VBIOS has suggested to use channel_width=2 for any ASIC that uses vram
info 3.0. This is because channel_width in the vram table no longer
represents the memory width
Reviewed-by: Samson Tam
Acked-by: Rodrigo Siqueira
Signed-off-by: Alvin Lee
---
drivers/gpu/drm/amd/display/d
From: Charlene Liu
w/a use case:
- dual display, compliance, toggling between the displays
- switching between 120Hz 420 -> 144Hz 444 and vice versa
- switching between 144Hz -> 60Hz TMDS or vice versa
It'd typically involve TMDS in some capacity since that's the only link
signal we leave the OT
From: Ilya Bakoulin
Changing PBN calculation to be more in line with spec. We don't need to
inflate PBN_NATIVE value by the 1.006 margin, since that is already
taken care of in the get_pbn_per_slot function.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Ilya Bakoulin
---
From: Charlene Liu
Rollback to new context for active display: this was previous tested
sequence. Avoid to do OTG master toggle is no active display at all,
this w/a was for fifo err.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
.../display/dc/clk_mgr/dc
From: Johnson Chen
Add guard for NULL pointer access
Reviewed-by: Charlene Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Johnson Chen
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c
b
From: Chris Park
[Why]
BIOS FW info version 3.5 is introduced to support new ASICs, but it's
content is currently same as 3.4.
[How]
Include minor version 5 in parsing to enable support.
Reviewed-by: Dillon Varone
Acked-by: Rodrigo Siqueira
Signed-off-by: Chris Park
---
drivers/gpu/drm/amd/
From: Nicholas Susanto
[Why]
When switching to another HDMI mode, we are unnecesarilly
disabling/enabling FIFO causing both HPO and DIG registers to be set at
the same time when only HPO is supposed to be set.
This can lead to a system hang the next time we change refresh rates as
there are case
From: George Shen
[Why]
The is_automated flag logic only applies to USB4 DPIA links during DP LL
compliance test automation. The flag should not be set for non-DPIA
cases.
[How]
Add check for DPIA link endpoint type before setting the flag. Also,
rename is_automated to skip_fallback_on_link_loss
From: Charlene Liu
This is w/a: we need to keep domain 24 power up in driver side, and let
dmubfw handle it for S0i3. For last display unplugged, if OTG in PG, no
interrupt call back coming.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
.../amd/display/dc
From: Relja Vojvodic
HW registers were being read to quickly, causing incorrect values to be
logged after a clock frequency was changed
Reviewed-by: Martin Leung
Acked-by: Rodrigo Siqueira
Signed-off-by: Relja Vojvodic
---
.../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 26 --
From: Wenjing Liu
Current implementation will choose to use refclk as dscclk. This is not
recommended by hardware team as refclk is a fixed value which could
cause unnecessary power consumption or it could be not enough for large
DSC timings. So we are adding new interfaces so we could switch to
From: Nicholas Kazlauskas
[Why]
The DC debug options currently do not function for dynamically adjusting
our watermarks.
[How]
Hook them up before passing them to DML2.
Also make sure we're using dc->bb_overrides since dc->debug isn't
populated during dc_construct.
Reviewed-by: Michael Strauss
From: Yihan Zhu
Missing clock gating programming blocks memory power on from boot up.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Yihan Zhu
---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c | 3 ++-
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_re
From: Dennis Chan
In previous case, Replay didn't identify the IRQ type, This commit fixes
the issues for the interrupt.
Reviewed-by: Robin Chen
Acked-by: Rodrigo Siqueira
Signed-off-by: Dennis Chan
---
.../display/dc/link/protocols/link_dp_irq_handler.c | 12 ++--
1 file changed, 6
From: Dillon Varone
Add function to handle deep copying dml2 context.
Reviewed-by: Chaitanya Dhere
Acked-by: Rodrigo Siqueira
Signed-off-by: Dillon Varone
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 15 +++---
.../drm/amd/display/dc/dml2/dml2_wrapper.c| 29 ++-
From: Harry Wentland
[WHY]
Previously this only excluded build for a few amdgpu_dm
binaries which makes no sense.
[HOW]
Wrap the entire Makefile in "ifneq ($(CONFIG_DRM_AMD_DC),)"
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/a
From: Ivan Lipski
[WHY]
Some eDP panels's ext caps don't write initial value cause the value of
dpcd_addr(0x317) is random. It means that sometimes the eDP will
clarify it is OLED, miniLED...etc cause the backlight control interface
is incorrect.
[HOW]
Add a new panel patch to remove sink ext c
From: Alex Hung
[WHAT]
Create a drm_writeback_connector when connector signal equals
SIGNAL_TYPE_VIRTUAL.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/Makefile| 3 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +-
.../drm/amd/displa
From: Alex Hung
Virtual stream encoder should not be a free match for thunderbolt or
usbc, and thus should be avoided.
Reviewed-by: Harry Wentland
Acked-by: Rodrigo Siqueira
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 5 -
1 file changed, 4
From: Harry Wentland
[WHY]
Writeback connectors are based on a different object:
drm_writeback_connector, and are therefore different from
amdgpu_dm_connector. We need to be careful to ensure code
designed for amdgpu_dm_connector doesn't inadvertently try
to operate on a drm_writeback_connector.
From: Harry Wentland
[WHAT]
Prepare a virtual connector for writeback.
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +--
.../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 3 ++-
2 f
From: Harry Wentland
[WHAT]
We need to use this function for both amdgpu_dm_connectors
and drm_writeback_connectors. Modify it to operate on
a drm_connector as a common base.
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/a
From: Harry Wentland
[WHY]
We will be dealing with two types of connector: amdgpu_dm_connector
and drm_writeback_connector.
[HOW]
We want to find both and then cast to the appriopriate type afterwards.
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers
From: Alex Hung
[WHY & HOW]
This is to replace 24a2efb3aa08 to check connector type to avoid
unhandled null pointer for writeback connectors.
Fixes: 310b5f1a3c9e ("drm/amd/display: Revert "drm/amd/display: Use
drm_connector in create_validate_stream_for_sink"")
Signed-off-by: Alex Hung
Reviewe
From: Alex Hung
[WHY]
wb_enabled field is set to false before it is used, and the following
code will never be executed.
[HOW]
Setting wb_enable to false after all removal work is completed.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc_strea
From: Alex Hung
[WHY]
Hardware may require different warmup approaches - big buffer or
individual buffers.
[HOW]
Setup warmup for big buffer when it is required by specific hardware.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
From: Alex Hung
[WHAT]
hw_points_num is 0 before ogam LUT is programmed; however, function
"dwb3_program_ogam_pwl" assumes hw_points_num is always greater than 0,
i.e. substracting it by 1 as an array index.
[HOW]
Check hw_points_num is not equal to 0 before using it.
Reviewed-by: Harry Wentlan
From: Harry Wentland
[WHY]
We need to track the dc_link and it would get confusing if
re-using the amdgpu_dm_connector.
[HOW]
Creating new amdgpu_dm_wb_connector.
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
From: Alex Hung
[WHY]
Counter j was not updated to present the num of writeback_info when
writeback pipes are removed.
[HOW]
update j (num of writeback info) under the correct condition.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
From: Roman Li
[Why]
UBSAN errors observed in dmesg.
array-index-out-of-bounds in dml2/display_mode_core.c
[How]
Fix the index.
Acked-by: Rodrigo Siqueira
Signed-off-by: Roman Li
---
drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deleti
From: Alex Hung
[WHAT]
The enable and disable writeback calls need to be included in the
coressponding functions in dc_stream.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/core/dc_stream.c | 33 +++
.../amd/display/dc/hwss/dcn30/dcn30_h
From: Alex Hung
[WHAT]
Add a new field to keep track whether a crtc is previously
writeback-enabled.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
2 files change
From: Alex Hung
[WHAT]
Add a function to enable and disable DWB's frame captures.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c | 23 +++
.../gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h | 2 ++
drivers/gpu/drm/amd/display
From: Harry Wentland
[WHAT]
Writeback connectors don't have a physical sink but DC still
needs a sink to function. Create a fake sink and stream for
writeback connectors
Reviewed-by: Alex Hung
Signed-off-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu
From: Alex Hung
[WHY]
drm_writeback requires to capture exact one frame in each writeback
call.
[HOW]
frame_capture is disabled after each writeback is completed.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +-
.../gpu/d
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 102d00a9a24f..9d3925603979 1
From: Aric Cyr
This version brings along following fixes:
* Enable writeback.
* Add multiple fixes for DML2 and DCN35.
* Introduce small code style adjustments.
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+),
From: Alex Hung
[WHAT]
Handle writeback requests and fill in the required information for DWB
programming and setup.
Reviewed-by: Harry Wentland
Signed-off-by: Alex Hung
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 159
This simple commit adjusts part of the code style in some of the dc bios
files.
Reviewed-by: Aurabindo Pillai
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/bios/bios_parser2.c| 63 +--
1 file changed, 30 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/d
Acked-by: Alex Deucher
On Fri, Dec 1, 2023 at 3:32 AM Lijo Lazar wrote:
>
> MP0 v13.0.6 SOCs don't support DRM MGCG.
>
> Signed-off-by: Lijo Lazar
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/so
[CCing stable list and Mario, who submitted this to 6.1.y]
On 01.12.23 01:30, Bagas Sanjaya wrote:
>
> I notice a regression report on Bugzilla [1]. Quoting from it:
>
>> Since kernel version 6.1.57 I have problems with external monitor
>> wakeup after suspend on Thinkpad X13 AMD Gen2 Notebook.
Hi,
On 2023/12/1 16:22, Thomas Zimmermann wrote:
Hi
Am 01.12.23 um 03:36 schrieb Sui Jingfeng:
Hi,
On 2023/11/28 18:45, Thomas Zimmermann wrote:
The udl driver is the only caller of drm_plane_helper_atomic_check().
Move the function into the driver. No functional changes.
Signed-off-by: T
Avoid pointer type value compared with 0 to make code clear.
./drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c:532:62-63: WARNING comparing
pointer to 0.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7672
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/d
On 01.12.23 03:44, zhuweixi wrote:
Thanks!
I hope you understood that that was a joke :)
I am planning to present GMEM in Linux MM Alignment Sessions so I can collect
more input from the mm developers.
Sounds good. But please try inviting key HMM/driver developer as well.
Most of the core
On 28.11.23 13:50, Weixi Zhu wrote:
This patch adds an abstraction layer, struct vm_object, that maintains
per-process virtual-to-physical mapping status stored in struct gm_mapping.
For example, a virtual page may be mapped to a CPU physical page or to a
device physical page. Struct vm_object ef
No functional modification involved.
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1106
amdgpu_connector_dvi_detect() warn: inconsistent indenting.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7673
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/amdgpu
./drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c:964:49-51:
WARNING !A || A && B is equivalent to !A || B.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7671
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_h
On 2023-11-30 17:43, Alex Deucher wrote:
> Does the same thing as:
> commit 6740ec97bcdb ("drm/amd/display: Increase frame warning limit with
> KASAN or KCSAN in dml2")
>
> Reported-by: kernel test robot
> Closes:
> https://lore.kernel.org/oe-kbuild-all/202311302107.hudxvywt-...@intel.com/
> Fi
On 2023-11-30 16:56, Aurabindo Pillai wrote:
> [Why&How]
> To enable testing/development of DML2, expose a new debug mask for future use.
>
> Signed-off-by: Aurabindo Pillai
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/include/amd_shared.h | 1 +
> 1 file changed, 1 inser
Applied. Thanks!
On Thu, Nov 30, 2023 at 2:46 AM Yang Yingliang
wrote:
>
> From: Yang Yingliang
>
> check the alloc_workqueue return value in radeon_crtc_init()
> to avoid null-ptr-deref.
>
> Fixes: fa7f517cb26e ("drm/radeon: rework page flip handling v4")
> Signed-off-by: Yang Yingliang
> ---
[AMD Official Use Only - General]
For the series.
From: Alex Deucher
Sent: Friday, December 1, 2023 9:00 AM
To: Lazar, Lijo
Cc: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Zhang, Hawking
Subject: Re: [PATCH 3/3] drm/amdgpu: Avoid querying DRM MGCG stat
On 2023-11-30 06:34, Daniel Vetter wrote:
> On Tue, 28 Nov 2023 at 23:11, Harry Wentland wrote:
>>
>> On 2023-11-16 14:57, Melissa Wen wrote:
>>> Hello,
>>>
>>> This series extends the current KMS color management API with AMD
>>> driver-specific properties to enhance the color management suppo
Phillip,
Can you test this patch? I was not able to repro the issue on the
navi2x card I had handy, but I think it should fix it.
Thanks,
Alex
On Wed, Nov 29, 2023 at 3:49 PM Alex Deucher wrote:
>
> On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
> >
> > Actually I think I see the proble
Hi Dave, Sima,
New stuff for 6.8.
The following changes since commit e8c2d3e25b844ad8f7c8b269a7cfd65285329264:
drm/amdgpu/gmc9: disable AGP aperture (2023-11-17 00:58:41 -0500)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-next-6.8-202
On 01.12.23 12:37, Thorsten Leemhuis wrote:
> Maybe one of the developers among the recipients has a idea. Oliver, but
> if none of them replies any time soon, it would be best if you'd check
> if 6.6 (and/or 6.7-rc) is affected as well; and if reverting it there
> fixes it, too.
OK, I checked i
On Fri, 2023-12-01 at 02:37 +, zhuweixi wrote:
> From your argument on KVM I can see that the biggest miscommunication
> between us is that you believed that GMEM wanted to share the whole
> address space. No, it is not the case. GMEM is only providing
> coordination via certain mmap() calls. S
This reverts commit 71a7974ac7019afeec105a54447ae1dc7216cbb3.
These helper functions are needed for KFD to export and import DMABufs
the right way without duplicating the tracking of DMABufs associated with
GEM objects while ensuring that move notifier callbacks are working as
intended.
Acked-by:
Create a new VM state to track user BOs that are in the system domain.
In the next patch this will be used do conditionally re-validate them in
amdgpu_vm_handle_moved.
Signed-off-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +
drivers/gpu/drm/amd/amdgpu/amdg
This is not strictly a change in the IOCTL API. This version bump is meant
to indicate to user mode the presence of a number of changes and fixes
that enable the management of VA mappings in compute VMs using the GEM_VA
ioctl for DMABufs exported from KFD.
Signed-off-by: Felix Kuehling
---
inclu
Create GEM handles for exporting DMABufs using GEM-Prime APIs. The GEM
handles are created in a drm_client_dev context to avoid exposing them
in user mode contexts through a DMABuf import.
Signed-off-by: Felix Kuehling
Reviewed-by: Ramesh Errabolu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This
ensures that a GEM handle is created on import and that obj->dma_buf
will be set and remain set as long as the object is imported into KFD.
Signed-off-by: Felix Kuehling
Reviewed-by: Ramesh Errabolu
Reviewed-by: Xiaogang.Chen
Ac
DMABuf imports in compute VMs are not wrapped in a kgd_mem object on the
process_info->kfd_bo_list. There is no explicit KFD API call to validate
them or add eviction fences to them.
This patch automatically validates and fences dymanic DMABuf imports when
they are added to a compute VM. Revalidat
Hi Alex,
I'm about to push patches 1-3 to the rebased amd-staging-drm-next. It
would be good to get patch 1 into drm-fixes so that Linux 6.6 will be
the only kernel without these prime helpers. That would minimize the
hassle for DKMS driver installations on future distros.
Thanks,
Felix
This improves latency if the GPU is already busy with other work.
This is useful for VR compositors that submit highly latency-sensitive
compositing work on high-priority compute queues while the GPU is busy
rendering the next frame.
Userspace merge request:
https://gitlab.freedesktop.org/mesa/mes
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