[Why]
Unplug mst hub will cause warning. That's because
dm_helpers_construct_old_payload() is changed to be called after
payload removement from dc link.
In dm_helpers_construct_old_payload(), We refer to the vcpi in
payload allocation table of dc link to construct the old payload
and payload is n
Am 02.10.23 um 20:22 schrieb Kees Cook:
On Mon, Oct 02, 2023 at 08:11:41PM +0200, Christian König wrote:
Am 02.10.23 um 20:08 schrieb Kees Cook:
On Mon, Oct 02, 2023 at 08:01:57PM +0200, Christian König wrote:
Am 02.10.23 um 18:53 schrieb Kees Cook:
On Mon, Oct 02, 2023 at 11:06:19AM -0400, A
Hey Felix,
On 04/10/2023 23:34, Felix Kuehling wrote:
On 2023-09-18 06:32, Christian König wrote:
Am 08.09.23 um 18:04 schrieb Shashank Sharma:
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function
On 04/10/2023 23:23, Felix Kuehling wrote:
On 2023-09-08 12:04, Shashank Sharma wrote:
From: Alex Deucher
This patch intorduces new UAPI/IOCTL for usermode graphics
queue. The userspace app will fill this structure and request
the graphics driver to add a graphics work queue for it. The
out
Am 04.10.23 um 05:39 schrieb Mario Limonciello:
On 10/3/2023 16:22, Deucher, Alexander wrote:
[Public]
-Original Message-
From: Limonciello, Mario
Sent: Tuesday, October 3, 2023 5:17 PM
To: Deucher, Alexander ; amd-
g...@lists.freedesktop.org
Cc: Wentland, Harry
Subject: Re: [PATCH v
Am 04.10.23 um 09:39 schrieb Lijo Lazar:
Move definition of package type to amdgpu_smuio header and add new
package types for CEM and OAM.
Signed-off-by: Lijo Lazar
Reviewed-by: Christian König
---
v2: Move definition to amdgpu_smuio.h instead of amdgpu.h (Christian/Hawking)
drivers/gp
On 2023-10-04 08:44:58 [-0400], Harry Wentland wrote:
> CI passed.
>
> Series is
> Acked-by: Harry Wentland
Thank you.
> Harry
Sebastian
On 2023-10-04 08:10:35 [-0400], Hamza Mahfooz wrote:
> I did some digging, and it seems like the intention of that patch was to
> fix the following splat:
>
> WARNING: CPU: 5 PID: 1062 at
> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.c:71
> dc_assert_fp_enabled+0x1a/0x30 [amdgpu]
> [...
Sorry for the late reply, just notice 2 other issues:
1. function svm_range_split_by_granularity can be removed now.
2. svm_range_restore_pages should map partial range to GPUs after
partial migration.
Regards,
Philip
On 2023-10-03 19:31, Xiaogang.Chen
On 10/5/2023 07:35, Christian König wrote:
Am 04.10.23 um 05:39 schrieb Mario Limonciello:
On 10/3/2023 16:22, Deucher, Alexander wrote:
[Public]
-Original Message-
From: Limonciello, Mario
Sent: Tuesday, October 3, 2023 5:17 PM
To: Deucher, Alexander ; amd-
g...@lists.freedesktop.or
On 10/4/2023 16:50, Alex Deucher wrote:
On Wed, Oct 4, 2023 at 5:42 PM Mario Limonciello
wrote:
For pptable structs that use flexible array sizes, use flexible arrays.
Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742
Signed-off-by: Mario Limonciello
Acked-by: Alex Deucher
On Thu, Oct 5, 2023 at 12:42 AM Mario Limonciello
wrote:
>
> For pptable structs that use flexible array sizes, use flexible arrays.
>
> Suggested-by: Felix Held
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894
> Signed-off-by: Mario Limonciello
Series is:
Acked-by: Alex Deucher
>
From: Boyuan Zhang
Update IB starting address alignment and size alignment with correct values
for decode and encode IPs.
Decode IB starting address alignment: 256 bytes
Decode IB size alignment: 64 bytes
Encode IB starting address alignment: 256 bytes
Encode IB size alignment: 4 bytes
Also bum
On Wed, Oct 4, 2023 at 1:37 PM Mario Limonciello
wrote:
>
> Linux PM core has a prepare() callback run before suspend.
>
> If the system is under high memory pressure, the resources may need
> to be evicted into swap instead. If the storage backing for swap
> is offlined during the suspend() step
On Wed, Oct 4, 2023 at 1:37 PM Mario Limonciello
wrote:
>
> If there is memory pressure at suspend time then dynamically
> allocating a large structure as part of DC suspend code will
> fail.
>
> Instead re-use the same structure and clear all members except
> those that should be maintained.
>
>
On Wed, Oct 4, 2023 at 1:27 PM Mario Limonciello
wrote:
>
> As dc_set_power_state() no longer allocates memory, it's not necessary
> to have return types and check return code as it can't fail anymore.
>
> Change it back to `void`.
>
> Signed-off-by: Mario Limonciello
Reviewed-by: Alex Deucher
On Thu, Oct 5, 2023 at 10:17 AM wrote:
>
> From: Boyuan Zhang
>
> Update IB starting address alignment and size alignment with correct values
> for decode and encode IPs.
>
> Decode IB starting address alignment: 256 bytes
> Decode IB size alignment: 64 bytes
> Encode IB starting address alignmen
Am 04.10.23 um 01:29 schrieb Kees Cook:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURC
Am 04.10.23 um 23:34 schrieb Felix Kuehling:
On 2023-09-18 06:32, Christian König wrote:
Am 08.09.23 um 18:04 schrieb Shashank Sharma:
To support oversubscription, MES FW expects WPTR BOs to
be mapped into GART, before they are submitted to usermode
queues. This patch adds a function for the s
Am 05.10.23 um 15:49 schrieb boyuan.zh...@amd.com:
From: Boyuan Zhang
Update IB starting address alignment and size alignment with correct values
for decode and encode IPs.
Decode IB starting address alignment: 256 bytes
Decode IB size alignment: 64 bytes
Encode IB starting address alignment:
On 10/5/2023 09:27, Alex Deucher wrote:
On Wed, Oct 4, 2023 at 1:37 PM Mario Limonciello
wrote:
If there is memory pressure at suspend time then dynamically
allocating a large structure as part of DC suspend code will
fail.
Instead re-use the same structure and clear all members except
those
Am 04.10.23 um 19:18 schrieb Mario Limonciello:
Linux PM core has a prepare() callback run before suspend.
If the system is under high memory pressure, the resources may need
to be evicted into swap instead. If the storage backing for swap
is offlined during the suspend() step then such a call
On 10/5/2023 09:39, Christian König wrote:
Am 04.10.23 um 19:18 schrieb Mario Limonciello:
Linux PM core has a prepare() callback run before suspend.
If the system is under high memory pressure, the resources may need
to be evicted into swap instead. If the storage backing for swap
is offlined
On 10/5/2023 8:25 AM, Philip Yang wrote:
Sorry for the late reply, just notice 2 other issues:
1. function svm_range_split_by_granularity can be removed now.
yes, the code has been sent to gerrit and merged. Will do it next time.
2. svm_range_restore_pages should map partial range to GPUs
On Wed, Oct 4, 2023 at 11:47 PM Zhang, Hawking wrote:
>
> [AMD Official Use Only - General]
>
> Hmm... thinking about it more, will it override the profile mode/workload for
> 0xC8 or 0xCC SKU as well. In another words, does it mean the pmfw fix is
> general to all the 13_0_0 SKUs.
Yes, my unde
On Thu, Oct 5, 2023 at 4:04 AM Wayne Lin wrote:
>
> [Why]
> Unplug mst hub will cause warning. That's because
> dm_helpers_construct_old_payload() is changed to be called after
> payload removement from dc link.
>
> In dm_helpers_construct_old_payload(), We refer to the vcpi in
> payload allocatio
On Thu, Oct 05, 2023 at 11:42:38AM +0200, Christian König wrote:
> Am 02.10.23 um 20:22 schrieb Kees Cook:
> > On Mon, Oct 02, 2023 at 08:11:41PM +0200, Christian König wrote:
> > > Am 02.10.23 um 20:08 schrieb Kees Cook:
> > > > On Mon, Oct 02, 2023 at 08:01:57PM +0200, Christian König wrote:
> >
DRM_OBJECT_MAX_PROPERTY limits the number of properties to be attached
and we are increasing that value all time we add a new property (generic
or driver-specific).
In this series, we are adding 13 new KMS driver-specific properties for
AMD color manage:
- CRTC Gamma enumerated Transfer Function
-
Place it in drm_property where drm_property_replace_blob and
drm_property_lookup_blob live. Then we can use the DRM helper for
driver-specific KMS properties too.
Reviewed-by: Harry Wentland
Reviewed-by: Liviu Dudau
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/arm/malidp_crtc.c | 2 +-
driv
Hook up driver-specific atomic operations for managing AMD color
properties. Create AMD driver-specific color management properties
and attach them according to HW capabilities defined by `struct
dc_color_caps`.
First add plane degamma LUT properties that means user-blob and its
size. We will add
We will add color mgmt properties to DRM planes in the next patches and
we want to track when one of this properties change to define atomic
commit behaviors. Using a similar approach from CRTC color props, we set
a color_mgmt_changed boolean whenever a plane color prop changes.
Reviewed-by: Harry
Hello,
Just another iteration for AMD driver-specific color properties.
Basically, addressing comments from the previous version.
Recap: this series extends the current KMS color management API with AMD
driver-specific properties to enhance the color management support on
AMD Steam Deck. The key
Instead of relying on color block names to get the transfer function
intention regarding encoding pixel's luminance, define supported
Electro-Optical Transfer Functions (EOTFs) and inverse EOTFs, that
includes pure gamma or standardized transfer functions.
v3:
- squash linear and unity TFs to iden
From: Joshua Ashton
Allow userspace to tell the kernel driver the input space and,
therefore, uses correct predefined transfer function (TF) to go from
encoded values to linear values.
v2:
- rename TF enum prefix from DRM_ to AMDGPU_ (Harry)
- remove HLG TF
Reviewed-by: Harry Wentland
Signed-o
Brief documentation about pre-defined transfer function usage on AMD
display driver and standardized EOTFs and inverse EOTFs.
v3:
- Document BT709 OETF (Pekka)
- Fix description of sRGB and pure power funcs (Pekka)
v4:
- Add description of linear and non-linear forms (Harry)
Co-developed-by: Har
From: Joshua Ashton
Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier = 80
nits for SDR content. So if you want, 203 nits for SDR content,
Add 3D LUT property for plane color transformations using a 3D lookup
table. 3D LUT allows for highly accurate and complex color
transformations and is suitable to adjust the balance between color
channels. It's also more complex to manage and require more
computational resources.
Since a 3D LUT h
On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT. Add pre-defined transfer function to enable delinearizing content
with or without shaper LUT, where AMD color module calculates the
resulted shaper curve. W
From: Joshua Ashton
Blend 1D LUT or a pre-defined transfer function (TF) can be set to
linearize content before blending, so that it's positioned just before
blending planes in the AMD color mgmt pipeline, and after 3D LUT
(non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D
LUT
From: Joshua Ashton
Add predefined transfer function programming. There is no post-blending
out gamma ROM for hardcoded curves, but we can use AMD color modules to
program LUT parameters from pre-defined coefficients and an empty
regamma LUT (or bump up LUT parameters with pre-defined TF values).
Add AMD pre-defined transfer function property to default DRM CRTC gamma
to convert to wire encoding with or without a user gamma LUT. There is
no post-blending regamma ROM for pre-defined TF. When setting Gamma TF
(!= Identity) and LUT at the same time, the color module will combine
the pre-define
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT
From: Joshua Ashton
We should reset a plane state if at least one of the color management
properties differs from old and new state.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amd
Describe some expected behavior of the AMD DM color mgmt programming.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amd
From: Joshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgp
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinat
From: Joshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgp
From: Joshua Ashton
Detach value translation from CTM to reuse it for programming HDR
multiplier property.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Signed-off-by: Melissa Wen
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +---
drivers/gpu/drm/amd/display/i
From: Joshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority. That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We retu
DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.
Reviewed-by: Harry Wentland
Enable usage of predefined transfer func in addition to shaper 1D LUT.
That means we can save some complexity by just setting a predefined
curve, instead of programming a custom curve when preparing color space
for applying 3D LUT.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../
Map DC shaper LUT to DM plane color management. Shaper LUT can be used
to delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. If a plane degamma is
apply to linearize the color space, a custom shaper 1D LUT can be used
just before applying
Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD
display HW, 3D LUT comes after a shaper curve and we always have to
program a shaper curve to delinearize or normalize the color space
before applying a 3D LUT (since we have a reduced number of LUT
entries).
In this version, th
From: Joshua Ashton
Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.
Reviewed-by: Harry Wentland
From: Joshua Ashton
Need to funnel the color caps through to these functions so it can check
that the hardware is capable.
v2:
- remove redundant color caps assignment on plane degamma map (Harry)
- pass color caps to degamma params
v3:
- remove unused color_caps parameter from set_color_proper
From: Joshua Ashton
Map plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
modu
From: Joshua Ashton
When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
Co-developed-by: Melissa Wen
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_
Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
-
Map the plane CTM driver-specific property to DC plane, instead of DC
stream. The remaining steps to program DPP block are already implemented
on DC shared-code.
v3:
- fix comment about plane and CRTC CTMs priorities (Harry)
Reviewed-by: Harry Wentland
Signed-off-by: Melissa Wen
---
.../gpu/dr
From: Joshua Ashton
Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and
convert DRM CTM to DC CSC float matrix.
v3:
- rename ctm2 to ctm_3x4 (Harry)
Reviewed-by: Harry Wentland
Signed-off-by: Joshua Ashton
---
.../amd/display/amdgpu_dm/amdgpu_dm_color.c | 28
On older chips, the absolute doorbell offset within
the doorbell page is based on the queue ID.
KFD is using queue ID and doorbell size to get an
absolute doorbell offset in userspace.
Here, adding db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So
Here, Adding db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So that doorbell offset will be aligned based on the doorbell
size.
v2:
- Addressed the review comment from Felix.
v3:
- Adding doorbell_size as parameter to get db absolute offset.
v4:
On 2023-10-02 13:02, Chen, Xiaogang
wrote:
On 9/29/2023 9:11 AM, Philip Yang wrote:
Caution: This message originated from an
External Source. Use proper caution when opening attachments,
clicking links, or responding.
On some OEM systems multiple navi3x dGPUS are triggering RAS errors
and BACO errors.
These errors come from elements of the OEM system that weren't part of
original test environment. This series addresses those problems.
NOTE: Although this series touches two subsystems, I would prefer to
take t
This reverts commit 0e5e1a84f0b8c814d502a135824244127fed8f23.
Reviewed-by: Alex Deucher
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
On some OEM systems, adding a W7900 dGPU triggers RAS errors and hangs
at a black screen on startup. This issue occurs only if `ucsi_acpi` has
loaded before `amdgpu` has loaded. The reason for this failure is that
`amdgpu` uses power_supply_is_system_supplied() to determine if running
on AC or DC
On Thu, Oct 05, 2023 at 12:52:30PM -0500, Mario Limonciello wrote:
> This reverts commit 0e5e1a84f0b8c814d502a135824244127fed8f23.
>
> Reviewed-by: Alex Deucher
> Signed-off-by: Mario Limonciello
No explaination as to why this needs to be reverted? And does this need
to be backported anywhere?
On Thu, Oct 05, 2023 at 12:52:29PM -0500, Mario Limonciello wrote:
> On some OEM systems, adding a W7900 dGPU triggers RAS errors and hangs
> at a black screen on startup. This issue occurs only if `ucsi_acpi` has
> loaded before `amdgpu` has loaded. The reason for this failure is that
> `amdgpu`
On 10/5/2023 14:12, Greg Kroah-Hartman wrote:
On Thu, Oct 05, 2023 at 12:52:30PM -0500, Mario Limonciello wrote:
This reverts commit 0e5e1a84f0b8c814d502a135824244127fed8f23.
Reviewed-by: Alex Deucher
Signed-off-by: Mario Limonciello
No explaination as to why this needs to be reverted? And
On Thu, Oct 5, 2023 at 3:13 PM Greg Kroah-Hartman
wrote:
>
> On Thu, Oct 05, 2023 at 12:52:30PM -0500, Mario Limonciello wrote:
> > This reverts commit 0e5e1a84f0b8c814d502a135824244127fed8f23.
> >
> > Reviewed-by: Alex Deucher
> > Signed-off-by: Mario Limonciello
>
> No explaination as to why t
On 2023-10-02 14:35, Felix Kuehling
wrote:
On 2023-09-29 10:11, Philip Yang
wrote:
Replace prange->mapped_to_gpu with prange->bitmap_mapped[], which is
based on prange granularity, updated when map to GPUS or
On 2023-10-02 13:06, Chen, Xiaogang
wrote:
On 9/29/2023 9:11 AM, Philip Yang wrote:
Caution: This message originated from an
External Source. Use proper caution when opening attachments,
clicking links, or responding.
On 2023-10-02 15:27, Felix Kuehling
wrote:
On 2023-09-29 10:11, Philip Yang
wrote:
Align unmap range start and last address to granularity boundary.
Skip unmap if range is already unmapped from GPUs.
This only
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 7d730f1bf6f39ece2d9f3ae682f12e5b593d534d Add linux-next specific
files for 20231005
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202309122047.cri9yjrq-...@intel.com
https
On 2023-10-02 13:08, Chen, Xiaogang
wrote:
On 9/29/2023 9:11 AM, Philip Yang wrote:
Caution: This message originated from an
External Source. Use proper caution when opening attachments,
clicking links, or responding.
On 2023-10-05 13:20, Arvind Yadav wrote:
Here, Adding db_size in byte to find the doorbell's
absolute offset for both 32-bit and 64-bit doorbell sizes.
So that doorbell offset will be aligned based on the doorbell
size.
v2:
- Addressed the review comment from Felix.
v3:
- Adding doorbell_size as
On 10/4/2023 18:10, Sebastian Reichel wrote:
Hi,
On Sun, Oct 01, 2023 at 07:00:11PM -0500, Mario Limonciello wrote:
Let me try to add more detail.
This is an OEM system that has 3 USB type C ports. It's an Intel system,
but this doesn't matter for the issue.
* when ucsi_acpi is not loaded the
Hi,
On Thu, Oct 05, 2023 at 12:52:29PM -0500, Mario Limonciello wrote:
> On some OEM systems, adding a W7900 dGPU triggers RAS errors and hangs
> at a black screen on startup. This issue occurs only if `ucsi_acpi` has
> loaded before `amdgpu` has loaded. The reason for this failure is that
> `am
Applied. Thanks!
Alex
On Thu, Oct 5, 2023 at 10:32 AM Christian König
wrote:
>
> Am 04.10.23 um 01:29 schrieb Kees Cook:
> > Prepare for the coming implementation by GCC and Clang of the __counted_by
> > attribute. Flexible array members annotated with __counted_by can have
> > their accesses b
IP discovery region has increased to > 8K on some SOCs.Maximum reserve
size is upto 12K, but not used. For now increase to 10K.
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdg
Add API support to fetch a snapshot of power management log from PMFW.
Signed-off-by: Lijo Lazar
---
v2: Add max size of input buffer to take care of overflows
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 16
drivers/g
From: Alex Deucher
Define the pmlog structures to be exposed via sysfs.
Signed-off-by: Alex Deucher
Signed-off-by: Lijo Lazar
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
Add support to fetch PM log sample from SMU v13.0.6
Signed-off-by: Lijo Lazar
---
v2: Check if input buffer has enough space to copy log data
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 +
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 4 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.
Add sysfs attribute to read power management log. A snapshot is
captured to the buffer when the attribute is read.
Signed-off-by: Lijo Lazar
---
v2: Pass PAGE_SIZE as the max size of input buffer
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 40 ++
1 file changed, 40 inserti
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