add hub->ctx_distance when read CONTEXT1_CNTL, align w/
write back operation.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c| 2 +-
drivers/gpu/drm/amd/amdgpu/gfxh
With S/G display becomes stable, enable S/G display for recent APUs
by default rather than white list.
v2: explicitly disable sg on pre-CZ chips (Alex)
Co-authored-by: Alex Deucher
Signed-off-by: Yifan Zhang
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 47 ++-
1 file cha
Am 28.09.23 um 10:31 schrieb Yifan Zhang:
add hub->ctx_distance when read CONTEXT1_CNTL, align w/
write back operation.
Good catch, but please double check the coding style with checkpath.pl.
With that done the patch is Acked-by: Christian König
Signed-off-by: Yifan Zhang
---
drivers/
Hi,
On Thu, Sep 21, 2023 at 12:57:43PM +0200, Maxime Ripard wrote:
> We've had a number of times when a patch slipped through and we couldn't
> pick them up either because our MAINTAINERS entry only covers the
> framework and thus we weren't Cc'd.
>
> Let's take another approach where we match ev
On older chips, the absolute doorbell offset within
the doorbell page is based on the queue ID.
KFD is using queue ID and doorbell size to get an
absolute doorbell offset in userspace.
This patch is to adjust the absolute doorbell offset
against the doorbell id considering the doorbell
size of 32/
This patch is to adjust the absolute doorbell offset
against the doorbell id considering the doorbell
size of 32/64 bit.
v2:
- Addressed the review comment from Felix.
Cc: Christian Koenig
Cc: Alex Deucher
Signed-off-by: Shashank Sharma
Signed-off-by: Arvind Yadav
---
drivers/gpu/drm/amd/amd
On 14/09/2023 10:24, Shashank Sharma wrote:
On 14/09/2023 09:45, Christian König wrote:
Am 08.09.23 um 18:04 schrieb Shashank Sharma:
A Memory queue descriptor (MQD) of a userqueue defines it in
the hw's context. As MQD format can vary between different
graphics IPs, we need gfx GEN specific
Hello Hamza Mahfooz,
The patch 5d72e247e58c: "drm/amd/display: switch DC over to the new
DRM logging macros" from Sep 20, 2023 (linux-next), leads to the
following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:542
dm_helpers_dp_read_dp
drivers/gpu/drm/radeon/atom.c:396 atom_skip_src_int() warn: ignoring
unreachable code.
Reported-by: Abaci Robot
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6713
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/radeon/atom.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/
Hello Ashley Thomas,
The patch 2631ac1ac328: "drm/amd/display: add DMUB registers to crash
dump diagnostic data." from May 17, 2021 (linux-next), leads to the
following Smatch static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:800
dc_dmub_srv_log_diagnostic_da
Ping on this series? Fixes an issue for SR-IOV in stress tests.
Alex
On Wed, Sep 27, 2023 at 2:31 PM Alex Deucher wrote:
>
> We normally place GART based on the location of VRAM and the
> available address space around that, but provide an option
> to force a particular location for hardware th
On Thu, Sep 28, 2023 at 9:22 AM Shashank Sharma wrote:
>
>
> On 14/09/2023 10:24, Shashank Sharma wrote:
> >
> > On 14/09/2023 09:45, Christian König wrote:
> >> Am 08.09.23 um 18:04 schrieb Shashank Sharma:
> >>> A Memory queue descriptor (MQD) of a userqueue defines it in
> >>> the hw's context.
On 28/09/2023 15:27, Alex Deucher wrote:
On Thu, Sep 28, 2023 at 9:22 AM Shashank Sharma wrote:
On 14/09/2023 10:24, Shashank Sharma wrote:
On 14/09/2023 09:45, Christian König wrote:
Am 08.09.23 um 18:04 schrieb Shashank Sharma:
A Memory queue descriptor (MQD) of a userqueue defines it i
On Thu, Sep 28, 2023 at 5:11 AM Yifan Zhang wrote:
>
> With S/G display becomes stable, enable S/G display for recent APUs
> by default rather than white list.
>
> v2: explicitly disable sg on pre-CZ chips (Alex)
>
> Co-authored-by: Alex Deucher
> Signed-off-by: Yifan Zhang
> ---
> .../gpu/drm/
On Thu, Sep 28, 2023 at 9:40 AM Shashank Sharma wrote:
>
>
> On 28/09/2023 15:27, Alex Deucher wrote:
> > On Thu, Sep 28, 2023 at 9:22 AM Shashank Sharma
> > wrote:
> >>
> >> On 14/09/2023 10:24, Shashank Sharma wrote:
> >>> On 14/09/2023 09:45, Christian König wrote:
> Am 08.09.23 um 18:04
On 28/09/2023 15:52, Alex Deucher wrote:
On Thu, Sep 28, 2023 at 9:40 AM Shashank Sharma wrote:
On 28/09/2023 15:27, Alex Deucher wrote:
On Thu, Sep 28, 2023 at 9:22 AM Shashank Sharma wrote:
On 14/09/2023 10:24, Shashank Sharma wrote:
On 14/09/2023 09:45, Christian König wrote:
Am 08.0
[AMD Official Use Only - General]
> -Original Message-
> From: Yadav, Arvind
> Sent: Thursday, September 28, 2023 5:54 AM
> To: Koenig, Christian ; Deucher, Alexander
> ; Sharma, Shashank
> ; Kuehling, Felix ;
> Joshi, Mukul ; Pan, Xinhui ;
> airl...@gmail.com; dan...@ffwll.ch
> Cc: amd-g
Hi Kees,
On 9/22/23 14:32, Kees Cook wrote:
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG
On 2023-09-28 10:30, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: Yadav, Arvind
Sent: Thursday, September 28, 2023 5:54 AM
To: Koenig, Christian ; Deucher, Alexander
; Sharma, Shashank
; Kuehling, Felix ;
Joshi, Mukul ; Pan, Xinhui ;
airl...@gmail.com;
The period to submit XDC 2024 hosting proposals has been extended and
the new deadline is **November 1, 2023**
Please, submit your proposals as soon as possible, thank you!
On Mon, 2023-06-19 at 15:43 +0200, Ricardo Garcia wrote:
> Hello everyone!
>
> The X.org board is soliciting proposals to h
Hello Felix, Mukul,
On 28/09/2023 17:30, Felix Kuehling wrote:
On 2023-09-28 10:30, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: Yadav, Arvind
Sent: Thursday, September 28, 2023 5:54 AM
To: Koenig, Christian ; Deucher, Alexander
; Sharma, Shashank
;
On Thu, Sep 28, 2023 at 5:46 AM Jiapeng Chong
wrote:
>
> drivers/gpu/drm/radeon/atom.c:396 atom_skip_src_int() warn: ignoring
> unreachable code.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6713
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/ra
Remove set df cstate as disallow df state is
not required for SMUv13.0.6
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
b/
On some systems with Navi3x dGPU will attempt to use BACO for runtime
PM but fails to resume properly. This is because on these systems
the root port goes into D3cold which is incompatible with BACO.
This happens because in this case dGPU is connected to a bridge between
root port which causes BO
On some systems AMD Navi3x dGPU triggers RAS errors on startup; but
only if the amdgpu kernel module is not part of the initramfs.
This is because the hardware is not properly programmed for the
AC/DC state of the system when it is loaded later in boot.
The AC/DC state of the system is incorrect s
On some OEM systems multiple navi3x dGPUS are triggering RAS errors
and BACO errors.
These errors come from elements of the OEM system that weren't part of
original test environment. This series addresses those problems.
NOTE: Although this series touches two subsystems, I would prefer to
take t
This workaround is not necessary with the power supply core fixed.
This reverts commit 0e5e1a84f0b8c814d502a135824244127fed8f23.
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
2 files
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: Tuesday, September 26, 2023 7:00 PM
> To: amd-gfx@lists.freedesktop.org; Sebastian Reichel ;
> Deucher, Alexander
> Cc: linux...@vger.kernel.org; linux-ker...@vger.kernel.org; Ma, Jun
> ; Limonciello, Mario
> Subject: [PAT
On Thu, Sep 28, 2023 at 12:41 PM Mario Limonciello
wrote:
>
> On some OEM systems multiple navi3x dGPUS are triggering RAS errors
> and BACO errors.
>
> These errors come from elements of the OEM system that weren't part of
> original test environment. This series addresses those problems.
>
> NO
On 2023-09-28 11:38, Shashank Sharma wrote:
Hello Felix, Mukul,
On 28/09/2023 17:30, Felix Kuehling wrote:
On 2023-09-28 10:30, Joshi, Mukul wrote:
[AMD Official Use Only - General]
-Original Message-
From: Yadav, Arvind
Sent: Thursday, September 28, 2023 5:54 AM
To: Koenig, Christi
On 9/28/2023 13:00, Alex Deucher wrote:
On Thu, Sep 28, 2023 at 12:41 PM Mario Limonciello
wrote:
On some OEM systems multiple navi3x dGPUS are triggering RAS errors
and BACO errors.
These errors come from elements of the OEM system that weren't part of
original test environment. This series
This patch set adds support for an application to query GPU
page faults. It's useful for debugging and there are
vulkan extensions that could make use of this. Preliminary
user space code which uses this can be found here:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238
https://gi
When we get a GPU page fault, cache the fault for later
analysis.
Cc: samuel.pitoi...@gmail.com
Acked-by: Guchun Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 31 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 18 +++
2 files chan
Don't update the fault cache if status is 0. In the multiple
fault case, subsequent faults will return a 0 status which is
useless for userspace and replaces the useful fault status, so
only update if status is non-0.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 ++
Add a interface to query the last GPU page fault for the process.
Useful for debugging context lost errors.
v2: split vmhub representation between kernel and userspace
v3: add locking when fetching fault info in INFO IOCTL
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238
l
Cache the current fault info in the vm struct. This can be queried
by userspace later to help debug UMDs.
Cc: samuel.pitoi...@gmail.com
Acked-by: Guchun Chen
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 +++
driver
On 2023-09-25 15:49, Melissa Wen wrote:
> Brief documentation about pre-defined transfer function usage on AMD
> display driver and standardized EOTFs and inverse EOTFs.
>
> v3:
> - Document BT709 OETF (Pekka)
> - Fix description of sRGB and pure power funcs (Pekka)
>
> Co-developed-by: Harry
On 2023-09-20 13:32, Xiaogang.Chen wrote:
From: Xiaogang Chen
This patch implements partial migration in gpu page fault according to migration
granularity(default 2MB) and not split svm range in cpu page fault handling.
A svm range may include pages from both system ram and vram of one gpu now.
On 2023-09-22 17:37, Philip Yang wrote:
Otherwise kfd flush tlb does nothing if vm update fence callback doesn't
update vm->tlb_seq. H/W will generate retry fault again.
This works now because retry fault keep coming, recover will update page
table again after AMDGPU_SVM_RANGE_RETRY_FAULT_PENDIN
On Fri, Aug 25, 2023 at 02:27:09PM +0800, Sui Jingfeng wrote:
> From: Sui Jingfeng
>
> There is no function that can be used to get all PCI(e) devices in a
> system by matching against its the PCI base class code only, while keep
> the sub-class code and the programming interface ignored. Therefo
While aligning SMU11 with SMU13 implementation an assumption was made that
`dpm_context->dpm_tables.pcie_table` was populated in dpm table initialization
like in SMU13 but it isn't.
So restore some of the original logic and instead just check for
amdgpu_device_pcie_dynamic_switching_supported() to
Use ratelimited version of dev_dbg to avoid flooding dmesg log. No
functional change.
Signed-off-by: Philip Yang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/
42 matches
Mail list logo
