Am 06.09.23 um 17:36 schrieb Alex Deucher:
This matches the behavior for soc15 and nv.
Signed-off-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/d
Am 06.09.23 um 21:55 schrieb Alex Deucher:
Commit 254986e324ad ("drm/radeon: Use the drm suballocation manager
implementation.")
made the fence wait in amdgpu_sa_bo_new() interruptible but there is no
code to handle an interrupt. This caused the kernel to randomly explode
in high-VRAM-pressure s
On 07/09/2023 08:57, Christian König wrote:
Am 06.09.23 um 16:35 schrieb Shashank Sharma:
On 06/09/2023 16:25, Shashank Sharma wrote:
On 05/09/2023 08:04, Christian König wrote:
Testing for reset is pointless since the reset can start right
after the
test. Grab the reset semaphore instead
[AMD Official Use Only - General]
Reviewed-by: Asad Kamal
Tested-by: Asad Kamal
Thanks & Regards
Asad
-Original Message-
From: Lazar, Lijo
Sent: Wednesday, September 6, 2023 4:56 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kamal, Asad
Subject: [PAT
Am 07.09.23 um 04:30 schrieb Sui Jingfeng:
Hi,
On 2023/9/6 17:40, Christian König wrote:
Am 06.09.23 um 11:08 schrieb suijingfeng:
Well, welcome to correct me if I'm wrong.
You seem to have some very basic misunderstandings here.
The term framebuffer describes some VRAM memory used for sca
On Wed, 06 Sep 2023, suijingfeng wrote:
> Another limitation of the 'nomodeset' parameter is that
> it is only available on recent upstream kernel. Low version
> downstream kernel don't has this parameter supported yet.
> So this create inconstant developing experience. I believe that
> there alwa
GC 10.1.3/4 have problems with TLB_FLUSH_HEAVYWEIGHT
which is used by SVM in svm_range_unmap_from_gpus().
This causes problems on GC 10.1.3/4.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff -
Hi,
On 2023/9/7 17:08, Christian König wrote:
Well, I have over 25 years of experience with display hardware and
what you describe here was never an issue.
I want to give you an example to let you know more.
I have a ASRock AD2550B-ITX board[1],
When another discrete video card is mounted i
Am 07.09.23 um 14:32 schrieb suijingfeng:
Hi,
On 2023/9/7 17:08, Christian König wrote:
Well, I have over 25 years of experience with display hardware and
what you describe here was never an issue.
I want to give you an example to let you know more.
I have a ASRock AD2550B-ITX board[1],
Wh
On Wed, 6 Sep 2023 15:30:04 -0400
Harry Wentland wrote:
> On 2023-08-10 12:02, Melissa Wen wrote:
> > Add 3D LUT property for plane gamma correction using a 3D lookup table.
> > Since a 3D LUT has a limited number of entries in each dimension we want
> > to use them in an optimal fashion. This me
On Wed, 6 Sep 2023 16:15:10 -0400
Harry Wentland wrote:
> On 2023-08-25 10:18, Melissa Wen wrote:
> > On 08/22, Pekka Paalanen wrote:
> >> On Thu, 10 Aug 2023 15:02:47 -0100
> >> Melissa Wen wrote:
> >>
> >>> Instead of relying on color block names to get the transfer function
> >>> intentio
On 2023-09-07 03:49, Pekka Paalanen wrote:
> On Wed, 6 Sep 2023 16:15:10 -0400
> Harry Wentland wrote:
>
>> On 2023-08-25 10:18, Melissa Wen wrote:
>>> On 08/22, Pekka Paalanen wrote:
On Thu, 10 Aug 2023 15:02:47 -0100
Melissa Wen wrote:
> Instead of relying on color bl
amdxcp unloads incompletely, and below error will be seen during load/unload,
sysfs: cannot create duplicate filename '/devices/platform/amdgpu_xcp.0'
devres_release_group will free xcp device at first, platform device will be
unregistered later in platform_device_unregister.
Signed-off-by: James
Hi,
On 2023/9/7 20:43, Christian König wrote:
Am 07.09.23 um 14:32 schrieb suijingfeng:
Hi,
On 2023/9/7 17:08, Christian König wrote:
Well, I have over 25 years of experience with display hardware and
what you describe here was never an issue.
I want to give you an example to let you kno
Am 07.09.23 um 17:26 schrieb suijingfeng:
[SNIP]
Then, I'll give you another example, see below for elaborate description.
I have one AMD BC160 GPU, see[1] to get what it looks like.
The GPU don't has a display connector interface exported.
It actually can be seen as a render-only GPU or comp
Hi,
On 2023/9/7 17:08, Christian König wrote:
I strongly suggest that you just completely drop this here
Drop this is OK, no problem. Then I will go to develop something else.
This version is not intended to merge originally, as it's a RFC.
Also, the core mechanism already finished, it is
Needed for HDP flush to work correctly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index d5ed9e0e1a5f..e5b5b0f4940f 100644
--- a/dri
We need heavy-weight flushes not just for SVM. If this is broken it will
affect ROCm either way.
Regards,
Felix
On 2023-09-07 08:08, Lang Yu wrote:
GC 10.1.3/4 have problems with TLB_FLUSH_HEAVYWEIGHT
which is used by SVM in svm_range_unmap_from_gpus().
This causes problems on GC 10.1.3/4.
I'd like to see checks for nonsensical flag combinations in the kernel
mode driver as well. We can only make some of those combinations valid
and meaningful in the future, if we implement well defined behaviour
(i.e. return an error) now. Otherwise we risk breaking misbehaving user
mode applica
On 2023-09-06 11:44, Mukul Joshi wrote:
Currently, we store CU info only for a single XCC assuming
that it is the same for all XCCs. However, that may not be
true. As a result, store CU info for all XCCs. This info is
later used for CU masking.
Signed-off-by: Mukul Joshi
One last nit-pick i
Applied. Thanks!
Alex
On Wed, Sep 6, 2023 at 10:00 PM Quan, Evan wrote:
>
> [AMD Official Use Only - General]
>
> Yeah, nice catch. But personally I would prefer to change the check as "if
> (retry <= 0)".
> Either way, the patch is reviewed-by: Evan Quan
>
> Evan
> > -Original Message---
On 2023-09-06 11:44, Mukul Joshi wrote:
Update cache info reporting in sysfs to report the correct
number of CUs and associated cache information based on
different spatial partitioning modes.
Signed-off-by: Mukul Joshi
---
v1->v2:
- Revert the change in kfd_crat.c
- Add a comment to not chan
On 2023-09-06 11:44, Mukul Joshi wrote:
The CU mask passed from user-space will change based on
different spatial partitioning mode. As a result, update
CU masking code for GFX9.4.3 to work for all partitioning
modes.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
---
v1->v2:
- In
On 2023-09-06 11:44, Mukul Joshi wrote:
Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with
the naming convention followed in amdgpu_gfx.h. No functional
change.
Signed-off-by: Mukul Joshi
Reviewed-by: Felix Kuehling
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 4 +
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Thursday, September 7, 2023 4:31 PM
> To: Joshi, Mukul ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCHv2 1/4] drm/amdgpu: Store CU info from all XCCs for GFX
> v9.4.3
>
>
> On 2023-09-06 11:44, Mu
[AMD Official Use Only - General]
> -Original Message-
> From: Kuehling, Felix
> Sent: Thursday, September 7, 2023 4:51 PM
> To: Joshi, Mukul ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCHv2 2/4] drm/amdkfd: Update cache info reporting for GFX
> v9.4.3
>
>
> On 2023-09-06 11:44, Mu
On 09/07/ , Felix Kuehling wrote:
> We need heavy-weight flushes not just for SVM. If this is broken it will
> affect ROCm either way.
Currently, TLB_FLUSH_HEAVYWEIGHT is called in 2 places,
1, kfd_ioctl_unmap_memory_from_gpu()
Under following conditions.
KFD_GC_VERSION(dev) == IP_VERSION(9, 4
Some BOs might be pinned. So the first eviction's failure will abort the
suspend sequence. These pinned BOs will be unpined afterwards during
suspend.
Actaully it has evicted most BOs, so that should stil work fine in sriov
full access mode.
Fixes: 47ea20762bb7 ("drm/amdgpu: Add an extra evict_re
update smu firmware header to support smu mca debug feature.
Signed-off-by: Yang Wang
---
.../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h | 3 +++
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/
enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled.
Signed-off-by: Yang Wang
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 26 +++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/g
Am 08.09.23 um 05:39 schrieb xinhui pan:
Some BOs might be pinned. So the first eviction's failure will abort the
suspend sequence. These pinned BOs will be unpined afterwards during
suspend.
That doesn't make much sense since pinned BOs don't cause eviction
failure here.
What exactly is the
Am 07.09.23 um 18:33 schrieb suijingfeng:
Hi,
On 2023/9/7 17:08, Christian König wrote:
I strongly suggest that you just completely drop this here
Drop this is OK, no problem. Then I will go to develop something else.
This version is not intended to merge originally, as it's a RFC.
Also,
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