This reverts commit c105518679b6e87232874ffc989ec403bee59664.
This patch disables the TOPDOWN flag for APU and few dGPU cards
which has the VRAM size equal to the BAR size.
When we enable the TOPDOWN flag, we get the free blocks at
the highest available memory region and we don't split the
lower
Hello, I just filed a bug for the Radeon driver crashing:
https://bugzilla.kernel.org/show_bug.cgi?id=217464
It looks similar to this bug
(https://bugzilla.kernel.org/show_bug.cgi?id=198669) because they are
both locking up the GPU and the page fault address is at the same page
offset of 0xffc, wh
In gfxhub_v2_1_setup_vmid_config(), the GCVM_CONTEXT1_CNTL reg is
written before related GCVM_CONTEXT1_PAGE_TABLE_START_ADDR and
GCVM_CONTEXT1_PAGE_TABLE_END_ADDR regs are written, which may
cause undefined behavior.
This patch rearranges WREG32 operations in gfxhub_v2_1_setup_vmid_config(),
so th
From: Thong Thai
[ Upstream commit 476ac50fc30540e29191615a26aaf5f9dee91c49 ]
Update the maximum resolution reported for HEVC encoding on VCN 3
devices to reflect its 8K encoding capability.
v2: Also update the max height for H.264 encoding to match spec.
(Ruijing)
Signed-off-by: Thong Thai
R
From: Yifan Zhang
[ Upstream commit af7828fbceed4f9e503034111066a0adef3db383 ]
APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather
it is internal path w/ native atomic support. Set have_atomics_support
to true.
Signed-off-by: Yifan Zhang
Reviewed-by: Lang Yu
Acked-by: Felix Kuehling
A
From: Yifan Zhang
[ Upstream commit af7828fbceed4f9e503034111066a0adef3db383 ]
APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather
it is internal path w/ native atomic support. Set have_atomics_support
to true.
Signed-off-by: Yifan Zhang
Reviewed-by: Lang Yu
Acked-by: Felix Kuehling
A
Am 2023-05-20 um 05:25 schrieb Arunpravin Paneer Selvam:
This reverts commit c105518679b6e87232874ffc989ec403bee59664.
This patch disables the TOPDOWN flag for APU and few dGPU cards
which has the VRAM size equal to the BAR size.
With resizable BARs it's not that rare.
When we enable the T