[PATCH 05/14] drm/amdgpu: Add API to get numa information of XCC

From: Lijo Lazar Add interface to get numa information of ACPI XCC object. The interface uses logical id to identify an XCC. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 14 +++ drivers/gpu/drm/amd/amdgpu/amdg

[PATCH 10/14] drm/amdgpu: Move initialization of xcp before kfd

From: Lijo Lazar After partition switch, fill all relevant xcp information before kfd starts initialization. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 16 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_

[PATCH 1/3] drm/ttm: export ttm_pool_fini for cleanup

From: Rajneesh Bhardwaj ttm_pool_init is exported and used outside of ttm subsystem with amdgpu_ttm interface, similarly export ttm_pool_fini for proper cleanup. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_pool.c | 1 +

[PATCH 3/3] drm/amdkfd: Native mode memory partition support

From: Rajneesh Bhardwaj For native mode, after amdgpu_bo is created on CPU domain, then call amdgpu_ttm_tt_set_mem_pool to select the TTM pool using bo->mem_id. ttm_bo_validate will allocate the memory to the correct memory partition before mapping to GPUs. Reviewed-by: Felix Kuehling Acked-and

[PATCH 2/3] drm/amdgpu: Set TTM pools for memory partitions

From: Philip Yang For native mode only, create TTM pool for each memory partition to store the NUMA node id, then the TTM pool will be selected using memory partition id to allocate memory from the correct partition. Acked-by: Christian König (rajneesh: changed need_swiotlb and need_dma32 to fa

[PATCH] drm/amdgpu: Fix xGMI access P2P mapping failure on GFXIP 9.4.3

From: Rajneesh Bhardwaj On GFXIP 9.4.3, we dont need to rely on xGMI hive info to determine P2P access. Reviewed-by: Felix Kuehling Acked-and-tested-by: Mukul Joshi Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 f

[PATCH] drm/amdgpu: Fix unmapping of aperture

From: Lijo Lazar When aperture size is zero, there is no mapping done. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu

[PATCH] drm/amdkfd: Remove skiping userptr buffer mapping when mmu notifier marks it as invalid

From: Xiaogang Chen mmu notifier does not always hold mm->sem during call back. That causes a race condition between kfd userprt buffer mapping and mmu notifier which leds to gpu shadder or SDMA access userptr buffer before it has been mapped to gpu VM. Always map userptr buffer to avoid that tho

[PATCH 1/3] drm/amdgpu: Add compute mode descriptor function

From: Lijo Lazar Keep a helper function to get description of compute partition mode. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 24 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 21 +

[PATCH 2/3] drm/amdgpu: Return error on invalid compute mode

From: Lijo Lazar Return error if an invalid compute partition mode is requested. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 +- 2 fi

[PATCH 3/3] drm/amdgpu: Add PSP spatial parition interface

From: Lijo Lazar Add PSP ring command interface for spatial partitioning. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 21 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++ drivers/gpu/drm/

[PATCH 2/4] drm/amdgpu: Skip using MC FB Offset when APU flag is set for SRIOV.

From: Gavin Wan The MC_VM_FB_OFFSET is PF only register. It cannot be read on VF. So, the driver should not use MC_VM_FB_OFFSET address to set the address of dev->gmc.aper_base. Signed-off-by: Gavin Wan Reviewed-by: Zhigang Luo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v

[PATCH 1/4] drm/amdgpu: Add PSP supporting PSP 13.0.6 SRIOV ucode init.

From: Gavin Wan Add PSP supporting PSP 13.0.6 SRIOV ucode init. Signed-off-by: Gavin Wan Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gp

[PATCH 4/4] drm/amdgpu: Checked if the pointer NULL before use it.

From: Gavin Wan For SRIOV on some parts, the host driver does not post VBIOS. So the guest cannot get bios information. Therefore, adev->virt.fw_reserve.p_pf2vf and adev->mode_info.atom_context are NULL. Signed-off-by: Gavin Wan Reviewed-by: Zhigang Luo Acked-by: Felix Kuehling Signed-off-by:

[PATCH 3/4] drm/amdgpu: Set memory partitions to 1 for SRIOV.

From: Gavin Wan For SRIOV, the memory partitions are set on host drover. Each VF only has one memory partition. We need set the memory partitions to 1 on guest driver for SRIOV. V2: sqaush in fix ("drm/amdgpu: Fix memory range info of GC 9.4.3 VFs") Signed-off-by: Gavin Wan Acked-by: Zhigang L

[PATCH 3/9] drm/amdgpu: Add reset_ras_error_count for vcn v4_0_3

From: Hawking Zhang Add reset_ras_error_count callback for vcn v4_0_3. It will be used to reset vcn ras error count. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 22 ++ 1 file changed, 22 inse

[PATCH 2/9] drm/amdgpu: Add query_ras_error_count for vcn v4_0_3

From: Hawking Zhang Add query_ras_error_count callback for vcn v4_0_3. It will be used to query and log vcn error count. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 36 + 1 file changed,

[PATCH 4/9] drm/amdgpu: Initialize vcn v4_0_3 ras function

From: Hawking Zhang Initialize vcn v4_0_3 ras function Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 26 + 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0

[PATCH 1/9] drm/amdgpu: Add vcn/jpeg ras err status registers

From: Hawking Zhang Add new ras error status registers introduced in vcn v4_0_3 to log vcn and jpeg ras error. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- .../include/asic_reg/vcn/vcn_4_0_3_offset.h | 78 +++ .../include/asic_reg/vcn/vcn_4_0_3_sh_mas

[PATCH 7/9] drm/amdgpu: Add reset_ras_error_count for jpeg v4_0_3

From: Hawking Zhang Add reset_ras_error_count callback for jpeg v4_0_3. It will be used to reset jpeg ras error count. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 22 ++ 1 file changed, 22 i

[PATCH 9/9] drm/amdgpu: Adjust the sequence to query ras error info

From: Hawking Zhang It turns out STATUS_VALID_FLAG needs to be checked ahead of any other fields. ADDRESS_VALID_FLAG and ERR_INFO_VALID_FLAG only manages ADDRESS and ERR_INFO field respectively. driver should continue poll ERR CNT field even ERR_INFO_VALD_FLAG is not set. Signed-off-by: Hawking

[PATCH 5/9] drm/amdgpu: Re-enable VCN RAS if DPG is enabled

From: Hawking Zhang VCN RAS enablement sequence needs to be added in DPG HW init sequence. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 27 - 1 file changed, 26 insertions(+), 1 deletion(-

[PATCH 6/9] drm/amdgpu: Add query_ras_error_count for jpeg v4_0_3

From: Hawking Zhang Add query_ras_error_count callback for jpeg v4_0_3. It will be used to query and log jpeg error count. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 64 1 file changed

[PATCH 8/9] drm/amdgpu: Initialize jpeg v4_0_3 ras function

From: Hawking Zhang Initialize jpeg v4_0_3 ras function. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 26 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v

[PATCH 1/6] drm/amdkfd: Increase queue number per process to 255 on GFX9.4.3

From: Mukul Joshi Increase the maximum number of queues that can be created per process to 255 on GFX 9.4.3. There is no HWS limitation restricting the number queues that can be created. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/am

[PATCH 2/6] drm/amdgpu: Fix register accesses in GFX v9.4.3

From: Lijo Lazar Access registers with the right xcc id. Also, remove the unused logic as PG is not used in GFX v9.4.3 Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 16 +++- 1 file changed, 3 inserti

[PATCH 5/6] drm/amdgpu: Enable NPS4 CPX mode

From: Philip Yang CPX compute mode is valid mode for NPS4 memory partition mode. Signed-off-by: Philip Yang Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dr

[PATCH 6/6] drm/amdgpu: For GFX 9.4.3 APU fix vram_usage value

From: Harish Kasiviswanathan For GFX 9.4.3 APP APU VRAM is allocated in GTT domain. While freeing memory check for GTT domain instead of VRAM if it is APP APU Signed-off-by: Harish Kasiviswanathan Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_a

[PATCH 3/6] drm/amdgpu: Skip halting RLC on GFX v9.4.3

From: Lijo Lazar RLC-PMFW handshake happens periodically when GFXCLK DPM is enabled and halting RLC may cause unexpected results. Avoid halting RLC from driver side. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 23

[PATCH 4/6] drm/amdkfd: Move pgmap to amdgpu_kfd_dev structure

From: Philip Yang VRAM pgmap resource is allocated every time when switching compute partitions because kfd_dev is re-initialized by post_partition_switch, As a result, it causes memory region resource leaking and system memory usage accounting unbalanced. pgmap resource should be allocated and

Re: [RFC PATCH 12/40] drm/amd/display: add plane HDR multiplier driver-private property

On 5/9/23 16:35, Joshua Ashton wrote: > FWIW, we technically do use it right now, but it is always set to 1 in > S.31.32. > > Before we used shaper + 3D LUT we did use it for scaling SDR content, > but given we always have a shaper + 3D LUT it made sense for us to > roll that into there. > A

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