On 2023/5/9 00:34, Sui Jingfeng wrote:
I have tested glmark2 on ls3a5000 with this patch applied,
I have also bought a better gpu (vega 56), which is on the way.
currently only have a rx550 at hand.
I pasted the performance score here, how about this score?
Does this looks normal?
[snip of f
Remove IMU in vf2pf ucode id enum to align with host's definition.
Signed-off-by: YuanShang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 1 -
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/
On 5/9/2023 10:59 AM, Guchun Chen wrote:
Prevent further dpm casting on legacy asics without od_enabled in
amdgpu_dpm_is_overdrive_supported. This can avoid UBSAN complain
in init sequence.
v2: add a macro to check legacy dpm instead of checking asic family/type
Suggested-by: Evan Quan
Sign
The IMU firmware is loaded on the host side, not the guest.
Remove IMU in vf2pf ucode id enum.
Signed-off-by: YuanShang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 1 -
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
> -Original Message-
> From: Lazar, Lijo
> Sent: Tuesday, May 9, 2023 3:29 PM
> To: Chen, Guchun ; amd-
> g...@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Quan, Evan
> Subject: Re: [PATCH] drm/amd/pm: avoid potential UBSAN issue on legacy
> asics
>
>
>
> On 5/9/2
Prevent further dpm casting on legacy asics without od_enabled in
amdgpu_dpm_is_overdrive_supported. This can avoid UBSAN complain
in init sequence.
v2: add a macro to check legacy dpm instead of checking asic family/type
v3: refine macro name for naming consistency
Suggested-by: Evan Quan
Signe
When performing device unbind or halt, we have disabled all irqs at the
very begining like amdgpu_pci_remove or amdgpu_device_halt. So
amdgpu_irq_put for irqs stored in fence driver should not be called
any more, otherwise, below calltrace will arrive.
[ 139.114088] WARNING: CPU: 2 PID: 1550 at
The IMU firmware is loaded on the host side, not the guest.
Remove IMU in vf2pf ucode id enum.
Signed-off-by: YuanShang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 1 -
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdg
Set finished fence to ETIME error if job timedout.
Signed-off-by: ZhenGuo Yin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 57f8f8b3cd8a..f2c02e4167fe 1006
[Why]
drm_sched_entity_add_dependency_cb ignores the scheduled fence and return false.
If entity's dependency is a schedulerd error fence and drm_sched_stop is called
due to TDR, drm_sched_entity_pop_job will wait for the dependency infinitely.
[How]
Do not wait or ignore the scheduled error fence
On 4/14/23 17:52, Qingqing Zhuo wrote:
> From: Wesley Chalmers
>
> [WHY]
> Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
> pipe commit can cause underflow.
>
> [HOW]
> Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
> optimized_required.
>
> This
[Public]
> -Original Message-
> From: Chen, Guchun
> Sent: Monday, May 8, 2023 9:28 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Lazar, Lijo ; Quan, Evan
> ; Koenig, Christian ;
> Pan, Xinhui
> Cc: Chen, Guchun ; Zhou1, Tao
>
> Subject: [PATCH] drm/a
[AMD Official Use Only - General]
> -Original Message-
> From: Chen, Guchun
> Sent: Monday, May 8, 2023 9:28 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Lazar, Lijo ; Quan, Evan
> ; Koenig, Christian ;
> Pan, Xinhui
> Cc: Chen, Guchun ; Zhou1, Tao
>
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Guchun Chen
> Sent: Tuesday, May 9, 2023 4:02 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Lazar, Lijo ; Quan, Evan
>
> Cc: Chen, Guchun
> Subject: [PATCH v3] drm/amd/pm: avoid potential UB
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> Guchun Chen
> Sent: Tuesday, May 9, 2023 4:25 AM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Koenig, Christian
>
> Cc: Chen, Guchun
> Subject: [PATCH] drm/amdgpu: skip disabling fence driver
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of
> YuanShang
> Sent: Tuesday, May 9, 2023 5:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yin, ZhenGuo (Chris) ; Chen, Horace
> ; YuanShang Mao (River)
>
> Subject: [PATCH] drm/amdgpu: Remove IMU ucode in vf2pf
>
> The IMU firm
Register CC_UVD_HARVESTING is obsolete for JPEG 3.1.2
Signed-off-by: Saleemkhan Jamadar
Reviewed-by: Veerabadhran Gopalakrishnan
---
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/jp
Fix below warnings reported by checkpatch:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: static const char * array should probably be static const char * const
WARNING: space prohibited between function name and open parenthesis '('
WARNING: braces {} are not necessary for sing
This function was releasing the incorrect lock on the error path.
Reported-by: kernel test robot
Fixes: 9bfa241d1289 ("drm/amdgpu: add [en/dis]able_kgq() functions")
Signed-off-by: Dan Carpenter
---
The LKP robot sent me an email about this after I had already written
the patch. (I review LKP S
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 47cba14ce6fc4f314bd814d07269d0c8de1e4ae6 Add linux-next specific
files for 20230509
Warning reports:
https://lore.kernel.org/oe-kbuild-all/202305070840.x0g3ofjl-...@intel.com
Warning
On 5/7/23 23:09, Huacai Chen wrote:
LoongArch now provides kernel_fpu_begin() and kernel_fpu_end() that are
used like the x86 counterparts in commit 2b3bd32ea3a22ea2d ("LoongArch:
Provide kernel fpu functions"), so we can enable DC_FP on LoongArch for
supporting more DCN devices.
Signed-off-by:
On 05/08, Harry Wentland wrote:
> On 4/23/23 10:10, Melissa Wen wrote:
> > We are enabling a large set of color calibration features to enhance KMS
> > color mgmt but these properties are specific of AMD display HW, and
> > cannot be provided by other vendors. Therefore, set a config option to
> >
On 05/08, Harry Wentland wrote:
>
>
> On 4/23/23 10:10, Melissa Wen wrote:
> > CRTC shaper LUT shapes the content after blending, i.e., de-linearizes
> > or normalizes space before applying a 3D LUT color correction. In the
> > next patch, we add CRTC 3D LUT property to DRM color management after
On 05/08, Harry Wentland wrote:
>
>
> On 4/23/23 10:10, Melissa Wen wrote:
> > From: Joshua Ashton
> >
> > Add predefined transfer function property to DRM CRTC gamma to convert
> > to wire encoding with or without gamma LUT.
> >
>
> Are all these new CRTC properties used by gamescope? I woul
On 05/08, Harry Wentland wrote:
>
>
> On 4/23/23 10:10, Melissa Wen wrote:
> > From amdgpu_dm_plane we can get it for both CRTC and plane color
> > properties. We are adding new plane properties for AMD driver-private
> > color mgmt.
> >
> > Signed-off-by: Melissa Wen
> > ---
> > .../amd/displ
On 05/08, Harry Wentland wrote:
>
>
> On 4/23/23 10:10, Melissa Wen wrote:
> > From: Joshua Ashton
> >
> > Multiplier to 'gain' the plane. When PQ is decoded using the fixed func
> > transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at
> > least) When sRGB is decoded, 1.0 -> 1.0
On 05/08, Harry Wentland wrote:
>
>
> On 4/23/23 10:10, Melissa Wen wrote:
> > Hi all,
> >
> > Joshua Ashton and I (with the great collaboration of Harry Wentland -
> > thanks) have been working on KMS color pipeline enhancement for Steam
> > Deck/SteamOS by exposing the large set of color caps
From: "Guilherme G. Piccoli"
(Bas: speculative change to mirror gfx10/gfx9)
Signed-off-by: Guilherme G. Piccoli
Cc: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
b/driv
Otherwise we get a full system lock (looks like a FW mess).
Copied the order from the GFX9 powergating code.
Fixes: 366468ff6c34 ("drm/amdgpu: Allow GfxOff on Vangogh as default")
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2545
Signed-off-by: Bas Nieuwenhuizen
Tested-by: Guilherme G.
I think the idea is that we wouldn't have a config option so it
doesn't inherently become linux kernel uAPI?
Then we can just build our SteamOS kernels with that definiton set.
On Tue, 9 May 2023 at 16:26, Melissa Wen wrote:
>
> On 05/08, Harry Wentland wrote:
> > On 4/23/23 10:10, Melissa Wen w
We currently do not have a use for this as we settled on per-plane 3D
LUT + Shaper, but we might end up wanting to use in our scRGB stack
someday so I would like to keep it.
On Tue, 9 May 2023 at 16:37, Melissa Wen wrote:
>
> On 05/08, Harry Wentland wrote:
> >
> >
> > On 4/23/23 10:10, Melissa W
I am okay with us dropping the shaper + 3D LUT from crtc. It has
problems anyway wrt. atomicity.
On Tue, 9 May 2023 at 16:34, Melissa Wen wrote:
>
> On 05/08, Harry Wentland wrote:
> >
> >
> > On 4/23/23 10:10, Melissa Wen wrote:
> > > From: Joshua Ashton
> > >
> > > Add predefined transfer func
On 09/05/2023 13:49, Bas Nieuwenhuizen wrote:
> From: "Guilherme G. Piccoli"
>
> (Bas: speculative change to mirror gfx10/gfx9)
>
> Signed-off-by: Guilherme G. Piccoli
> Cc: Alex Deucher
> ---
Thanks a lot for both patches Bas! This second one, despite I've
attached it on gitlab, you should a
On 5/9/23 12:52, Joshua Ashton wrote:
> I think the idea is that we wouldn't have a config option so it
> doesn't inherently become linux kernel uAPI?
>
> Then we can just build our SteamOS kernels with that definiton set.
>
That's the idea. Would that work for you?
Harry
> On Tue, 9 May 20
On 5/9/23 12:23, Melissa Wen wrote:
> On 05/08, Harry Wentland wrote:
>> On 4/23/23 10:10, Melissa Wen wrote:
>>> We are enabling a large set of color calibration features to enhance KMS
>>> color mgmt but these properties are specific of AMD display HW, and
>>> cannot be provided by other vendo
On 5/9/23 12:52, Melissa Wen wrote:
> On 05/08, Harry Wentland wrote:
>>
>>
>> On 4/23/23 10:10, Melissa Wen wrote:
>>> Hi all,
>>>
>>> Joshua Ashton and I (with the great collaboration of Harry Wentland -
>>> thanks) have been working on KMS color pipeline enhancement for Steam
>>> Deck/SteamOS
Extend the address and size validations to AMDGPU_VA_OP_UNMAP and
AMDGPU_VA_OP_CLEAR by moving the validations to amdgpu_gem_va_ioctl.
Internal users of amdgpu_vm_bo_map are no longer validated but they
should be fine.
Userspace (radeonsi and radv) seems fine as well.
---
drivers/gpu/drm/amd/amd
The existing validations are incorrect and insufficient. This is
motivated by OOB access in amdgpu_vm_update_range when
offset_in_bo+map_size overflows.
Fixes: 9f7eb5367d00 ("drm/amdgpu: actually use the VM map parameters")
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +--
drivers/gpu/drm
On 5/9/23 12:54, Joshua Ashton wrote:
> We currently do not have a use for this as we settled on per-plane 3D
> LUT + Shaper, but we might end up wanting to use in our scRGB stack
> someday so I would like to keep it.
>
uAPI should always have a userspace that uses it. But if we go
and put it beh
FWIW, we technically do use it right now, but it is always set to 1 in S.31.32.
Before we used shaper + 3D LUT we did use it for scaling SDR content,
but given we always have a shaper + 3D LUT it made sense for us to
roll that into there.
On Tue, 9 May 2023 at 20:00, Harry Wentland wrote:
>
> On
From: Vitaly Prosyak
During an IGT GPU reset test we see again oops despite of
commit 0c8c901aaaebc9bf8bf189ffc116e678f7a2dc16
drm/sched: Check scheduler ready before calling timeout handling.
It uses ready condition whether to call drm_sched_fault which unwind
the TDR leads to GPU reset.
Howeve
+ dri-devel
On Tue, May 9, 2023 at 5:43 PM wrote:
>
> From: Vitaly Prosyak
>
> During an IGT GPU reset test we see again oops despite of
> commit 0c8c901aaaebc9bf8bf189ffc116e678f7a2dc16
> drm/sched: Check scheduler ready before calling timeout handling.
>
> It uses ready condition whether to ca
From: Rajneesh Bhardwaj
On GFXIP9.4.3 APP APU where there is no dedicated VRAM domain handle
VRAM BO allocation requests on CPU domain and validate them on GTT.
Support for handling multi-socket and multi-numa partitions within a
socket will be added by future patches, this enables 1P NPS1 asic
From: Rajneesh Bhardwaj
[For 1P NPS1 mode driver bringup]
Changes required to initialize the amdgpu driver with frontdoor firmware
loading and discovery=2 with the native mode SBIOS that enables CPU GPU
unified interleaved memory.
sudo modprobe amdgpu discovery=2
Once PSP TMR region is reporte
From: Rajneesh Bhardwaj
This adds dummy vram manager to support ASICs that do not have a
dedicated or carvedout vram domain.
Reviewed-by: Felix Kuehling
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 67 ++--
1
From: Le Ma
On newer GPUs, the number of kernel rings are increased.
Signed-off-by: Le Ma
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
From: Mukul Joshi
Increase Max GPU instances to 64 to handle multi-socket
system with GFX 9.4.3 asic.
Signed-off-by: Mukul Joshi
Acked-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dr
From: "Stanley.Yang"
It should change logical instance to device instance
to query ras info
Signed-off-by: Stanley.Yang
Reviewed-by: Hawking Zhang
Reviewed-by: Tao Zhou
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 7 +--
1 file changed, 5 insertions(+), 2 d
From: Le Ma
Avoid to mislead users as it's not a real error.
Signed-off-by: Le Ma
Reviewed-by: Asad Kamal
Reviewed-by: Amber Lin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd
From: Tao Zhou
Not all ASICs support GFX CP ECC irq.
Signed-off-by: Tao Zhou
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
From: Asad kamal
Update gfx clock frequency from metric table for SMU v13.0.6
Signed-off-by: Asad kamal
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a
From: Asad kamal
Add interrupt handler for thermal throttler events from
PMFW on SMUv13.0.6
Signed-off-by: Asad kamal
Acked-by: Evan Quan
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 107 +-
1 file changed, 104 inser
From: Lijo Lazar
PMFW will initialize the power limit values even if PPT throttler
feature is disabled. Fetch the limit value from FW.
Signed-off-by: Lijo Lazar
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 15 ---
1 f
From: Asad kamal
Update driver interface for SMU v13.0.6 to be
compatible with PMFW v85.48 version
Signed-off-by: Asad kamal
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
.../pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h | 12
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_
From: Lijo Lazar
It adds message support for FW notification on driver unload.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
---
.../inc/pmfw_if/smu13_driver_if_v13_0_6.h | 18 --
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_pp
From: Lijo Lazar
Use the interface version directly from PMFW interface header file rather
than keeping another definition in common smu13 file.
Signed-off-by: Lijo Lazar
Reviewed-by: Asad kamal
Signed-off-by: Alex Deucher
---
.../inc/pmfw_if/smu13_driver_if_aldebaran.h | 2 +
.../inc/pmf
From: Asad Kamal
Add mem temperature as part of hw mon attributes for GC version 9.4.3
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/g
From: Asad Kamal
Update hw mon attributes for GC Version 9.4.3 to valid ones
on APU and Non APU systems
v2: Group checks along existing one
Added power limit & mclock for gc version 9.4.3
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/p
From: Lijo Lazar
On SMU v13.0.6 APUs, FW will need to take some actions if driver is going
to halt RLC. Notify PMFW that driver is not going to manage device so
that FW takes care of the required actions.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Asad Kamal
Signed-off-by: Alex
From: Lijo Lazar
Modifications to mode-2 reset flow for SMU v13.0.6 ASICs.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Asad Kamal
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 9 +
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c |
From: Yang Wang
fix typo about smu socclk value.
Signed-off-by: Yang Wang
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v1
From: Lijo Lazar
It's not required to take lock on all cases while querying partition
mode. Querying partition mode during KFD init process doesn't need to
take a lock. Init process after a switch will already be happening under
lock. Control the behaviour by adding flags to xcp_query_partition_m
From: Mukul Joshi
This patch enables SVM capability on GFX9.4.3 when
run in Native mode. It also sets best_prefetch and
best_restore locations to CPU as there is no VRAM.
Signed-off-by: Mukul Joshi
Acked-by: Rajneesh Bhardwaj
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
---
drive
From: Lijo Lazar
It's not fine grain, behaves similar to MGCG.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/driver
From: Lijo Lazar
During partition switch, keep the state as transient mode. Fetch the
latest state if switch fails.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 18 +++---
drivers/gpu/drm/amd/amdgpu
From: Asad kamal
Update driver metrics table for SMU v13.0.6 to be
compatible with PMFW v85.47 version
Signed-off-by: Asad kamal
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
.../drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_6.h | 4 ++--
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw
From: Lijo Lazar
In certain configs, TMR information is available from ACPI. Add API to
fetch the information.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
From: Lijo Lazar
If SOC doesn't expose dedicated vram, discovery region may be
available through system memory. Rename the existing interface to
generic read_binary_from_mem and add a fallback path to read from system
memory.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by:
From: Lijo Lazar
On certain ASICs, discovery info is available at reserved region in system
memory. The location is available through ACPI interface. Add API to read
discovery info from there.
Signed-off-by: Lijo Lazar
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/dr
From: Philip Yang
kfd_flush_tlb_after_unmap should return true for GFX v9.4.3, to do TLB
heavyweight flush after unmapping from GPU to guarantee that the GPU
will not access pages after they have been unmapped. This also helps
improve the mapping to GPU performance.
Without this, KFD accidently
From: Shiwu Zhang
For topology reflection, each socket to every other socket has the
exactly same topology info as the other way around. So it is safe
to keep the reflected num_links value otherwise it will be overriden
by the link info output of GET_PEER_LINKS command.
Signed-off-by: Shiwu Zhan
From: Lijo Lazar
Add parsing of ACPI xcc objects and fill in relevant info from them by
invoking the DSM methods.
Signed-off-by: Lijo Lazar
Reviewed-and-tested-by: Rajneesh Bhardwaj
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +
drivers/gpu/drm/amd/amdgpu/a
From: Lijo Lazar
Initalize syfs nodes after harvest information is fetched and fetch the
correct harvest info based on each IP instance.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 41 +--
1 file
From: Lijo Lazar
Keep an instance mask formed by physical instance numbers for VCN and JPEG
IPs. Populate the mask from discovery table information.
Signed-off-by: Lijo Lazar
Acked-by: Leo Liu
Tested-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
From: Lijo Lazar
Add mappings for logical to physical id for VCN/JPEG 4.0.3
v2: make local function static (Alex)
Signed-off-by: Lijo Lazar
Acked-by: Leo Liu
Tested-by: James Zhu
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/aqua_vanjaram_reg_init.c| 18 ++
1 file
From: Sonny Jiang
VCN loading ucode is moved to early_init with using 'amdgpu_ucode_*'
helpers.
Reviewed-by: Leo Liu
Signed-off-by: Sonny Jiang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
From: Lijo Lazar
Address VCN/JPEG instances using logical ids. Whenever register access is
required, get the physical instance using GET_INST.
Signed-off-by: Lijo Lazar
Acked-by: Leo Liu
Tested-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 29
From: Sonny Jiang
Need parentheses for the micro parameters.
Signed-off-by: Sonny Jiang
Reviewed-by: David (Ming Qiang) Wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgp
From: James Zhu
Use dummy register 0xDEADBEEF selects AID for PSP VCN_RAM ucode.
Signed-off-by: James Zhu
Reviewed-by: Sonny Jiang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
From: Sonny Jiang
The 0xDEADBEEF standard anti-hang value. Use it may cause
fake pass.
Signed-off-by: Sonny Jiang
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/g
From: Lijo Lazar
Use VCN instance mask to check if an instance is harvested or not.
Signed-off-by: Lijo Lazar
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
From: James Zhu
Use physical AID index for VCN/JPEG ring name instead of
logical AID index.
Signed-off-by: James Zhu
Reviewed-by: Sonny Jiang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
2 files changed, 2 i
From: Sonny Jiang
The jpeg_v4_0_3 jpeg_pitch register uses UVD_JRBC_SCRATCH0. It needs to
move WREG() to after jpeg_start.
Switch to a posted register write when doing the ring test to make sure
the register write lands before we test the result.
Signed-off-by: Sonny Jiang
Reviewed-by: Leo Liu
From: Sonny Jiang
To make sure VCN DB_CTRL is delivered before doorbell write.
Signed-off-by: Sonny Jiang
Reviewed-by: Lijo Lazar
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4
From: Lijo Lazar
VCN DPG buffer object is intialized to NULL. If allotted, buffer object
deletion logic will take care of NULL check and delete accordingly. This
is useful for cases where indirect sram flag could be manipulated later
after buffer allocation.
Signed-off-by: Lijo Lazar
Reviewed-b
From: Lijo Lazar
Simplify so as to use the same sequence to assign logical to physical
ids for all IPs.
Signed-off-by: Lijo Lazar
Acked-by: Leo Liu
Tested-by: James Zhu
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 33 +--
1 file changed, 8
From: Lijo Lazar
For IH ring buffer and read/write pointers, use GPU VA space rather than
Guest PA on APU configs. Access through Guest PA doesn't work when IOMMU
is enabled. It is also beneficial in NUMA configs as it allocates from
the closest numa pool in a numa enabled system.
Signed-off-by:
From: Lijo Lazar
Use the generic term fw_reserved_memory for FW reserve region. This
region may also hold discovery TMR in addition to other reserve
regions. This region size could be larger than discovery tmr size, hence
don't change the discovery tmr size based on this.
Signed-off-by: Lijo Laz
From: Lijo Lazar
GMC block handles memory related information, it makes more sense to
keep memory partition functions in gmc block.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 30 +
drivers/gpu/drm/amd
From: Lijo Lazar
Expand the interface to get supported memory partition modes also along
with the current memory partition mode.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0
From: Lijo Lazar
Use a struct to store additional numa node information including size
and base address. Add numa_info pointer to xcc object to point to the
relevant structure based on its proximity domain.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/
From: Lijo Lazar
Some ASICs have the device memory divided into multiple partitions. The
parititions could be denoted by a numa node or by a range of pages.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 17 +
From: Lijo Lazar
Add utility functions to get details of xcp and iterate through
available xcps.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 12 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 31
From: Lijo Lazar
Add callback in xcp interface to fill xcp memory id information. Memory
id is used to identify the range/partition of an XCP from the available
memory partitions in device. Also, fill the id information.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
From: Lijo Lazar
GC 9.4.3 ASICS may have memory split into multiple partitions.Initialize
the memory partition information for each range. The information may be
in the form of a numa node id or a range of pages.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
dr
From: Lijo Lazar
Fetch xcp information from xcp_mgr and also add xcc_mask to kfd node.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 19 +--
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++
2 files chan
From: Lijo Lazar
When auto mode is specified, driver will choose the right compute
partition mode.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Philip Yang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_d
From: Lijo Lazar
Check the memory ranges available to the device also for deciding a
valid partition mode. Only select combinations are valid for a
particular mode.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Reviewed-by: Philip Yang
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/aqua_
From: Lijo Lazar
Implement callbacks to fill memory node information in aquavanjaram.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
.../drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --g
From: Lijo Lazar
Instead of start xcc id and number of xcc per node, use the xcc mask
which is the mask of logical ids of xccs belonging to a parition.
Signed-off-by: Lijo Lazar
Reviewed-by: Le Ma
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 9 +-
.../drm/
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