gds_va is unnecessary.
Marek
On Thu, Mar 30, 2023 at 3:18 PM Alex Deucher
wrote:
> For GFX11, the UMD needs to allocate some shadow buffers
> to be used for preemption. The UMD allocates the buffers
> and passes the GPU virtual address to the kernel since the
> kernel will program the packet t
On 05/04/2023 23:18, Luben Tuikov wrote:
On 2023-04-05 06:06, Shashank Sharma wrote:
On 04/04/2023 22:58, Luben Tuikov wrote:
On 2023-04-04 12:36, Shashank Sharma wrote:
On 04/04/2023 18:30, Luben Tuikov wrote:
On 2023-03-29 12:04, Shashank Sharma wrote:
From: Shashank Sharma
This patch
Hi,
I have read on the internet that asrock launched a nvme pcie gpu.
On Linux distros we dont have support to graphics 3D and stream processors
(opencl) simultaneously like windows 10/11.
My notebook have two nvme slots.
So, why not a amd's dedicated nvme vram (video ram) devices?
It would re
Hi!
On Wed, Apr 05, 2023 at 03:32:21PM +1000, Michael Ellerman wrote:
> Segher Boessenkool writes:
> > On Tue, Apr 04, 2023 at 08:28:47PM +1000, Michael Ellerman wrote:
> >> The amdgpu driver builds some of its code with hard-float enabled,
> >> whereas the rest of the kernel is built with soft-f
Fix sdma v4 sw fini error for sdma 4.2.2 to
solve the following general protection fault
[ +0.108196] general protection fault, probably for non-canonical
address 0xd5e5a4ae79d24a32: [#1] PREEMPT SMP PTI
[ +0.18] RIP: 0010:free_fw_priv+0xd/0x70
[ +0.22] Call Trace:
[ +0.12]
Am 05.04.23 um 17:31 schrieb Shane Xiao:
For userptr bo with iommu on, multiple GPUs use same system
memory dma mapping address when both adev and bo_adev are in
identity mode or in the same iommu group.
If RAM direct map to one GPU, other GPUs can share the original
BO in order to reduce dma ad
[AMD Official Use Only - General]
This patch is Reviewed-by: Likun Gao .
Regards,
Likun
-Original Message-
From: lyndonli
Sent: Thursday, April 6, 2023 4:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; Gao, Likun ; Zhang,
Hawking ; Li, Lyndon
Subject: [PATCH] drm/amdgpu: Fix
[AMD Official Use Only - General]
Reviewed-by: Feifei Xu
-Original Message-
From: lyndonli
Sent: Thursday, April 6, 2023 4:12 PM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; Gao, Likun ; Zhang,
Hawking ; Li, Lyndon
Subject: [PATCH] drm/amdgpu: Fix sdma v4 sw fini error
Fix s
Why that?
This is the save buffer for GDS, not the old style GDS BOs.
Christian.
Am 06.04.23 um 09:36 schrieb Marek Olšák:
gds_va is unnecessary.
Marek
On Thu, Mar 30, 2023 at 3:18 PM Alex Deucher
wrote:
For GFX11, the UMD needs to allocate some shadow buffers
to be used for pree
GDS memory isn't used on gfx11. Only GDS OA is used.
Marek
On Thu, Apr 6, 2023 at 5:09 AM Christian König
wrote:
> Why that?
>
> This is the save buffer for GDS, not the old style GDS BOs.
>
> Christian.
>
> Am 06.04.23 um 09:36 schrieb Marek Olšák:
>
> gds_va is unnecessary.
>
> Marek
>
> On T
Am 05.04.23 um 17:23 schrieb Srinivasan Shanmugam:
The driver doesn't resubmit jobs on hangs any more, hence drop
the hang limit parameter - amdgpu_job_hang_limit, wherever it is used.
Suggested-by: Christian König
Cc: Alex Deucher
Cc: Mario Limonciello
Cc: Kent Russell
Signed-off-by: Sriniv
[why]
regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and
unaccessible under sriov.
The clock counter high bit may update during reading process.
[How]
Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with
regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sr
That's what I thought as well, but Mitch/Hans insisted on that.
We should probably double check internally.
Christian.
Am 06.04.23 um 11:43 schrieb Marek Olšák:
GDS memory isn't used on gfx11. Only GDS OA is used.
Marek
On Thu, Apr 6, 2023 at 5:09 AM Christian König
wrote:
Why that?
When the SMT changes on the fly, send the message to the PMFW
to notify the SMT status changed.
Changes in v5
1./ Add a new vangogh_fini_smc_tables() to accommodate the timer fini
and smu_v11_0_fini_smc_tables().
2./ Move the version check of SMU version before initializing the timer.
Changes in
Add a timer to poll the SMT state periodically, if the SMT state
is changed, invoke the interface to notify the PMFW.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 44 +++
drivers/gpu/drm/am
When the SMT state is changed on the fly, sent the SMT enable
message to the PMFW to notify it that the SMT state changed.
Add the support to send PPSMC_MSG_SetCClkSMTEnable(0x58) message
to the PMFW for Vangogh.
Signed-off-by: Wenyou Yang
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3
On 4/6/2023 07:45, Wenyou Yang wrote:
When the SMT state is changed on the fly, sent the SMT enable
message to the PMFW to notify it that the SMT state changed.
Add the support to send PPSMC_MSG_SetCClkSMTEnable(0x58) message
to the PMFW for Vangogh.
Signed-off-by: Wenyou Yang
---
.../pm/sws
On 4/6/2023 07:45, Wenyou Yang wrote:
Add a timer to poll the SMT state periodically, if the SMT state
is changed, invoke the interface to notify the PMFW.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c|
Am 04.04.23 um 23:59 schrieb Mukul Joshi:
Update the invalid PTE flag setting to ensure, in addition
to transitioning the retry fault to a no-retry fault, it
also causes the wavefront to enter the trap handler. With the
current setting, it only transitions to a no-retry fault.
Well that was act
Am 2023-04-06 um 10:36 schrieb Christian König:
Am 04.04.23 um 23:59 schrieb Mukul Joshi:
Update the invalid PTE flag setting to ensure, in addition
to transitioning the retry fault to a no-retry fault, it
also causes the wavefront to enter the trap handler. With the
current setting, it only tra
There is no GDS shadowing info in the device info uapi, so userspace can't
create any GDS buffer and thus can't have any GDS va. It's a uapi issue,
not what firmware wants to do.
Marek
On Thu, Apr 6, 2023 at 6:31 AM Christian König <
ckoenig.leichtzumer...@gmail.com> wrote:
> That's what I thoug
Am 06.04.23 um 17:01 schrieb Felix Kuehling:
Am 2023-04-06 um 10:36 schrieb Christian König:
Am 04.04.23 um 23:59 schrieb Mukul Joshi:
Update the invalid PTE flag setting to ensure, in addition
to transitioning the retry fault to a no-retry fault, it
also causes the wavefront to enter the trap
Am 2023-04-06 um 03:45 schrieb Shashank Sharma:
On 05/04/2023 23:18, Luben Tuikov wrote: So, then why isn't Felix in
the Cc tags? Doorbell changes touch that area too.
He's actually the only one you left out, other than the MLs emails.
Either add everyone to the Cc tags in the commit message,
On 4/4/23 06:28, Michael Ellerman wrote:
The amdgpu driver builds some of its code with hard-float enabled,
whereas the rest of the kernel is built with soft-float.
When building with 64-bit long double, if soft-float and hard-float
objects are linked together, the build fails due to incompati
From: Vitaly Prosyak
During an IGT GPU reset test we see the following oops,
[ +0.03] [ cut here ]
[ +0.00] WARNING: CPU: 9 PID: 0 at kernel/workqueue.c:1656
__queue_delayed_work+0x6d/0xa0
[ +0.04] Modules linked in: iptable_filter bpfilter amdgpu(OE)
nls
[AMD Official Use Only - General]
Hi Mario,
Thank you for your review.
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, April 6, 2023 10:05 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan, Evan
>
> Cc: Yuan, Perry ; Liang, Richar
[AMD Official Use Only - General]
Hi Mario,
Thank you for your review.
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, April 6, 2023 10:09 PM
> To: Yang, WenYou ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan,
> Evan
> Cc: Yuan, Perry ; Liang, Richa
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: e134c93f788fb93fd6a3ec3af9af850a2048c7e6 Add linux-next specific
files for 20230406
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202303082135.njdx1bij-...@intel.com
https
[AMD Official Use Only - General]
Hi Mario,
> -Original Message-
> From: Yang, WenYou
> Sent: Friday, April 7, 2023 10:47 AM
> To: Limonciello, Mario ; Deucher, Alexander
> ; Koenig, Christian
> ; Pan, Xinhui ; Quan,
> Evan
> Cc: Yuan, Perry ; Liang, Richard qi
> ; Li, Ying ; Liu, Kun
>
When the SMT changes on the fly, send the message to the PMFW
to notify the SMT status changed.
Changes in v6
1./ Update last_smt_active only when the return from
smu_set_cpu_smt_enable() successfully.
2./ Use smu->adev->pm.fw_version to check smu version, if it is not
assigned, get the smu versi
When the SMT state is changed on the fly, sent the SMT enable
message to the PMFW to notify it that the SMT state changed.
Add the support to send PPSMC_MSG_SetCClkSMTEnable(0x58) message
to the PMFW for Vangogh.
Signed-off-by: Wenyou Yang
---
.../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h| 3
Add a timer to poll the SMT state periodically, if the SMT state
is changed, invoke the interface to notify the PMFW.
Signed-off-by: Wenyou Yang
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 44 +++
drivers/gpu/drm/am
On 06/04/2023 17:16, Felix Kuehling wrote:
Am 2023-04-06 um 03:45 schrieb Shashank Sharma:
On 05/04/2023 23:18, Luben Tuikov wrote: So, then why isn't Felix in
the Cc tags? Doorbell changes touch that area too.
He's actually the only one you left out, other than the MLs emails.
Either add e
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