Use fw->size instead of discovery_tmr_size for fallback path.
Change-Id: I61f1ec55314ea5948ed3ef821becfdd63d876272
Signed-off-by: Le Ma
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: de90d455a35e474a184c898e66a6a108c3a99434 Add linux-next specific
files for 20220928
Error/Warning reports:
https://lore.kernel.org/linux-mm/202209150141.wgbakqmx-...@intel.com
https://lore.kern
[AMD Official Use Only - General]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Le Ma
Sent: Thursday, September 29, 2022 15:50
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: [PATCH] drm/amdgpu: correct the memcpy size for ip discovery
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On Tue, Sep 27, 2022 at 11:38 AM Sharma, Shashank
wrote:
On 9/27/2022 5:23 PM, Felix Kuehling wrote:
Am 2022-09-27 um 10:58 schrieb Sharma,
From: "Jiadong.Zhu"
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer.
From: "Jiadong.Zhu"
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
From: "Jiadong.Zhu"
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer Preemption for
From: "Jiadong.Zhu"
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue, and pops
On 9/29/2022 2:18 PM, Sharma, Shashank wrote:
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On Tue, Sep 27, 2022 at 11:38 AM Sharma, Shashank
wrote:
On 9/27/2022 5:23 PM, Felix Kuehlin
Hi folks,
We are excited to welcome you in person to the 2022 X.Org Developers
Conference, held in conjunction with WineConf and FOSS XR conference.
The conference will start officially on Tuesday morning, October 4th.
The program is here:
https://indico.freedesktop.org/event/2/timetable/
Andrew Morton writes:
> On Wed, 28 Sep 2022 22:01:22 +1000 Alistair Popple wrote:
>
>> @@ -1401,22 +1494,7 @@ static int dmirror_device_init(struct dmirror_device
>> *mdevice, int id)
>>
>> static void dmirror_device_remove(struct dmirror_device *mdevice)
>> {
>> -unsigned int i;
>> -
>
Alistair Popple writes:
> Michael Ellerman writes:
>> Alistair Popple writes:
>>> When the CPU tries to access a device private page the migrate_to_ram()
>>> callback associated with the pgmap for the page is called. However no
>>> reference is taken on the faulting page. Therefore a concurrent
enc314_stream_encoder_dp_blank is only used in dcn314_dio_stream_encoder.c now,
change it to static.
Fixes: c9c2ff53cc20 ("drm/amd/display: Add explicit FIFO disable for DP blank")
Signed-off-by: Yang Yingliang
---
.../gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c | 2 +-
1 file ch
Ping on this series?
Alex
On Thu, Sep 8, 2022 at 10:39 AM Alex Deucher wrote:
>
> amdgpu_device_asic_has_dc_support() just checks the asic itself.
> amdgpu_device_has_dc_support() is a runtime check which not
> only checks the asic, but also other things in the driver
> like whether virtual disp
On 9/29/2022 1:10 PM, Lazar, Lijo wrote:
On 9/29/2022 2:18 PM, Sharma, Shashank wrote:
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On Tue, Sep 27, 2022 at 11:38 AM Sharma, Shashank
wr
Feel free to add my acked-by, but that's really not my field of expertise.
Christian.
Am 29.09.22 um 15:15 schrieb Alex Deucher:
Ping on this series?
Alex
On Thu, Sep 8, 2022 at 10:39 AM Alex Deucher wrote:
amdgpu_device_asic_has_dc_support() just checks the asic itself.
amdgpu_device_has_d
On 9/29/2022 6:50 PM, Sharma, Shashank wrote:
On 9/29/2022 1:10 PM, Lazar, Lijo wrote:
On 9/29/2022 2:18 PM, Sharma, Shashank wrote:
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On T
On 9/29/2022 3:37 PM, Lazar, Lijo wrote:
To be clear your understanding -
Nothing is automatic in PMFW. PMFW picks a priority based on the actual
mask sent by driver.
Assuming lower bits corresponds to highest priority -
If driver sends a mask with Bit3 and Bit 0 set, PMFW will chose prof
In some error path in amdgpu_sdma_init_microcode(), release_firmware() is
not called, the memory allocated in request_firmware() will be leaked,
calling amdgpu_sdma_destroy_inst_ctx() which calls release_firmware() to
avoid memory leak.
Fixes: 60704ab9 ("drm/amdgpu: add function to init SDMA m
On Tue, Aug 30, 2022 at 1:29 PM Simon Ser wrote:
>
> This series adds support for DRM_MODE_PAGE_FLIP_ASYNC for atomic
> commits, aka. "immediate flip" (which might result in tearing).
> The feature was only available via the legacy uAPI, however for
> gaming use-cases it may be desirable to enable
On 9/29/2022 7:30 PM, Sharma, Shashank wrote:
On 9/29/2022 3:37 PM, Lazar, Lijo wrote:
To be clear your understanding -
Nothing is automatic in PMFW. PMFW picks a priority based on the
actual mask sent by driver.
Assuming lower bits corresponds to highest priority -
If driver sends a m
On 9/29/2022 4:14 PM, Lazar, Lijo wrote:
On 9/29/2022 7:30 PM, Sharma, Shashank wrote:
On 9/29/2022 3:37 PM, Lazar, Lijo wrote:
To be clear your understanding -
Nothing is automatic in PMFW. PMFW picks a priority based on the
actual mask sent by driver.
Assuming lower bits correspond
Hi Dave, Daniel,
Fixes for 6.0.
The following changes since commit f76349cf41451c5c42a99f18a9163377e4b364ff:
Linux 6.0-rc7 (2022-09-25 14:01:02 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-6.0-2022-09-29
for you to fetch
On 2022-09-06 12:46, Melissa Wen wrote:
> Hi,
>
> From all feedback at [3DLUT_RFC] and an extensive AMD driver
> examination, here I am back with a first attempt to wire up a user 3D
> LUT (post-blending) to DC interface via DM CRTC color mgmt :)
>
> I'm following some specific approaches to h
I'm still seeing a warning even with this fix:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:
In function ?dc_stream_remove_writeback?:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:527:55:
warning: array subscr
On 2022-09-29 11:36, Felix Kuehling wrote:
I'm still seeing a warning even with this fix:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:
In function ?dc_stream_remove_writeback?:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/
Am 2022-09-29 um 11:41 schrieb Hamza Mahfooz:
On 2022-09-29 11:36, Felix Kuehling wrote:
I'm still seeing a warning even with this fix:
/home/fkuehlin/compute/kernel/drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:
In function ?dc_stream_remove_writeback?:
/home/fkuehlin/compute/
On 2022-09-28 15:02, Felix Kuehling wrote:
Am 2022-09-28 um 12:11 schrieb Philip Yang:
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to o
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to on,
subsequent free ranges allocated with xnack off will not unreserve
memory. When switching
Enable sram on vcn_4_0_2
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index f36e4f08db6d..0b52af415b28 100644
--- a/dri
Enable VCN DPG on GC11_0_1
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 5f0d6983714a..16b757664a35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21
Reviewed-by:JamesZhufortheseries.
On 2022-09-29 12:50 p.m., Sonny Jiang wrote:
Enable VCN DPG on GC11_0_1
Signed-off-by: Sonny Jiang
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
b/drivers/gpu/drm/amd/amdgpu/soc
On 2022-09-29 12:47, Philip Yang wrote:
Unified memory usage with xnack off is tracked to avoid oversubscribe
system memory, with xnack on, we don't track unified memory usage to
allow memory oversubscribe. When switching xnack mode from off to on,
subsequent free ranges allocated with xnack off
On 2022-09-29 07:10, Lazar, Lijo wrote:
On 9/29/2022 2:18 PM, Sharma, Shashank wrote:
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On Tue, Sep 27, 2022 at 11:38 AM Sharma, Shashank
wrote:
On 9/28/22 22:32, Alex Deucher wrote:
> On Wed, Sep 28, 2022 at 3:24 PM Dmitry Osipenko
> wrote:
>>
>> On 9/28/22 20:47, Dmitry Osipenko wrote:
>>> On 9/28/22 20:44, Deucher, Alexander wrote:
[AMD Official Use Only - General]
This should be fixed in a backwards compatible way with t
On 2022-09-28 08:01, Alistair Popple wrote:
When the CPU tries to access a device private page the migrate_to_ram()
callback associated with the pgmap for the page is called. However no
reference is taken on the faulting page. Therefore a concurrent
migration of the device private page can free t
On Thu, Sep 29, 2022 at 10:14 AM Lazar, Lijo wrote:
>
>
>
> On 9/29/2022 7:30 PM, Sharma, Shashank wrote:
> >
> >
> > On 9/29/2022 3:37 PM, Lazar, Lijo wrote:
> >> To be clear your understanding -
> >>
> >> Nothing is automatic in PMFW. PMFW picks a priority based on the
> >> actual mask sent by d
This series adds support for DRM_MODE_PAGE_FLIP_ASYNC for atomic
commits, aka. "immediate flip" (which might result in tearing).
The feature was only available via the legacy uAPI, however for
gaming use-cases it may be desirable to enable it via the atomic
uAPI too.
- Patchwork: https://patchwork
This is a subset of [1], included here because a subsequent patch
needs to document the behavior of this flag under the atomic uAPI.
v2: new patch
[1]: https://patchwork.freedesktop.org/patch/500177/
Signed-off-by: Simon Ser
Reviewed-by: André Almeida
Reviewed-by: Alex Deucher
---
include/ua
Up until now, amdgpu was silently degrading to vsync when
user-space requested an async flip but the hardware didn't support
it.
The hardware doesn't support immediate flips when the update changes
the FB pitch, the DCC state, the rotation, enables or disables CRTCs
or planes, etc. This is reflect
This new field indicates whether the driver has the necessary logic
to support async page-flips via the atomic uAPI. This is leveraged by
the next commit to allow user-space to use this functionality.
All atomic drivers setting drm_mode_config.async_page_flip are updated
to also set drm_mode_confi
If the driver supports it, allow user-space to supply the
DRM_MODE_PAGE_FLIP_ASYNC flag to request an async page-flip.
Set drm_crtc_state.async_flip accordingly.
Document that drivers will reject atomic commits if an async
flip isn't possible. This allows user-space to fall back to
something else.
This new kernel capability indicates whether async page-flips are
supported via the atomic uAPI. DRM clients can use it to check
for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
Make it clear that DRM_CAP_ASYNC_PAGE_FLIP is for legacy uAPI only.
Signed-off-by: Simon Ser
Reviewe
amdgpu_dm_commit_planes() already sets the flip_immediate flag for
async page-flips. This flag is used to set the UNP_FLIP_CONTROL
register. Thus, no additional change is required to handle async
page-flips with the atomic uAPI.
v2: make it clear this commit is about DC and not only DCN
Signed-of
From: Andrey Grodzovsky
When many entities are competing for the same run queue
on the same scheduler, we observe an unusually long wait
times and some jobs get starved. This has been observed on GPUVis.
The issue is due to the Round Robin policy used by schedulers
to pick up the next entity's j
Inlined:
On 2022-09-29 14:46, Luben Tuikov wrote:
> From: Andrey Grodzovsky
>
> When many entities are competing for the same run queue
> on the same scheduler, we observe an unusually long wait
> times and some jobs get starved. This has been observed on GPUVis.
>
> The issue is due to the Rou
On 2022-09-28 08:01, Alistair Popple wrote:
Since 27674ef6c73f ("mm: remove the extra ZONE_DEVICE struct page
refcount") device private pages have no longer had an extra reference
count when the page is in use. However before handing them back to the
owning device driver we add an extra referen
Alistair Popple wrote:
>
> Jason Gunthorpe writes:
>
> > On Mon, Sep 26, 2022 at 04:03:06PM +1000, Alistair Popple wrote:
> >> Since 27674ef6c73f ("mm: remove the extra ZONE_DEVICE struct page
> >> refcount") device private pages have no longer had an extra reference
> >> count when the page is
From: Andrey Grodzovsky
When many entities are competing for the same run queue
on the same scheduler, we observe an unusually long wait
times and some jobs get starved. This has been observed on GPUVis.
The issue is due to the Round Robin policy used by schedulers
to pick up the next entity's j
On 9/29/2022 11:37 PM, Felix Kuehling wrote:
On 2022-09-29 07:10, Lazar, Lijo wrote:
On 9/29/2022 2:18 PM, Sharma, Shashank wrote:
On 9/28/2022 11:51 PM, Alex Deucher wrote:
On Wed, Sep 28, 2022 at 4:57 AM Sharma, Shashank
wrote:
On 9/27/2022 10:40 PM, Alex Deucher wrote:
On Tue,
On 9/30/2022 12:02 AM, Alex Deucher wrote:
On Thu, Sep 29, 2022 at 10:14 AM Lazar, Lijo wrote:
On 9/29/2022 7:30 PM, Sharma, Shashank wrote:
On 9/29/2022 3:37 PM, Lazar, Lijo wrote:
To be clear your understanding -
Nothing is automatic in PMFW. PMFW picks a priority based on the
actu
In SDMA0_QUEUE0_RB_CNTL, queue size is 2^RB_SIZE, not 2^(RB_SIZE +1).
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/am
clean sdma_v6_0_get_reg_offset function.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index db51230163c5..b2c71f533e
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