On Friday, August 26th, 2022 at 16:39, Alex Deucher
wrote:
> On Fri, Aug 26, 2022 at 3:38 AM Simon Ser wrote:
> >
> > On Thursday, August 25th, 2022 at 20:22, Alex Deucher
> > wrote:
> >
> > > On Wed, Aug 24, 2022 at 11:09 AM Simon Ser cont...@emersion.fr wrote:
> > >
> > > > amdgpu_dm_commit
On Mon, Aug 29, 2022 at 04:01:44PM +, Simon Ser wrote:
> On Friday, August 26th, 2022 at 10:19, Ville Syrjälä
> wrote:
>
> > On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> > > This new kernel capability indicates whether async page-flips are
> > > supported via the atomic uAPI.
Not all the gfx10 variants need to integrate
global tap_delay and per se tap_delay firmwares
Only init tap_delay ucode when it does include in
rlc ucode binary so driver doesn't send a null buffer
to psp for firmware loading
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.
[AMD Official Use Only - General]
Reviewed-by: Jack Gui
-Original Message-
From: Zhang, Hawking
Sent: Tuesday, August 30, 2022 4:10 PM
To: amd-gfx@lists.freedesktop.org; Gui, Jack
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: only init tap_delay ucode when it's included in
ucode b
People sometimes still think they can enable UMS by specifying
radeon.modeset=0 on the kernel command line, but UMS support was
removed years ago and the driver just fails to load when the option is
specified.
If the driver shouldn't load at all then this can be easily done with
modprobe.blacklist
On Tue, 30 Aug 2022 11:08:22 +0300
Ville Syrjälä wrote:
> On Mon, Aug 29, 2022 at 04:01:44PM +, Simon Ser wrote:
> > On Friday, August 26th, 2022 at 10:19, Ville Syrjälä
> > wrote:
> >
> > > On Wed, Aug 24, 2022 at 03:08:55PM +, Simon Ser wrote:
> > > > This new kernel capability i
On Tue, Aug 30, 2022 at 11:40:10AM +0300, Pekka Paalanen wrote:
> On Tue, 30 Aug 2022 11:08:22 +0300
> Ville Syrjälä wrote:
>
> > On Mon, Aug 29, 2022 at 04:01:44PM +, Simon Ser wrote:
> > > On Friday, August 26th, 2022 at 10:19, Ville Syrjälä
> > > wrote:
> > >
> > > > On Wed, Aug 24, 2
From: Ma Jun
Remove redundant reference of the header file drm_gem_atomic_helper.h
Signed-off-by: Ma Jun
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amd
On Tuesday, August 30th, 2022 at 10:08, Ville Syrjälä
wrote:
> > In the documentation patch discussion [1], it appears it's not clear what
> > drivers should do when async flip isn't possible with the legacy uAPI.
> >
> > For the atomic uAPI, we need to pick on of these two approaches:
> >
> > 1
This patch is: Reviewed-by: Guchun Chen
Looks it needs to add it to upstream instead of amd-staging-drm-next branch.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Ma Jun
Sent: Tuesday, August 30, 2022 8:06 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
Cc: C
On Tuesday, August 30th, 2022 at 12:24, Ville Syrjälä
wrote:
> > > The current behaviour is to fall back to a blit if the async
> > > flip fails. So you still get the same effective behaviour, just
> > > not as efficient. I think that's a reasonable way to handle it.
> >
> > That's purely an Xor
(Oops, I replied to the wrong thread. Re-sending to the correct one.)
On Tuesday, August 30th, 2022 at 10:41, Michel Dänzer
wrote:
> > For the atomic uAPI, we need to pick on of these two approaches:
> >
> > 1. Let the kernel fall back to a sync flip if async isn't possible. This
> >simplif
From: ye xingchen
Return the value sdma_v4_0_start() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/
Fixes a build failure.
Fixes: e990bd60716d ("drm/amd/display: Only commit SubVP state after pipe
programming")
Signed-off-by: Alex Deucher
Cc: Alvin Lee
Cc: Jun Lei
Cc: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
di
Document missing parameter.
Fixes: 8889a13f99e5 ("drm/amd/display: Add some extra kernel doc to amdgpu_dm")
Reported-by: Stephen Rothwell
Signed-off-by: Alex Deucher
Cc: Rodrigo Siqueira
Cc: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 +
1 file changed, 1 insertio
On Tue, Aug 30, 2022 at 12:05 AM Lazar, Lijo wrote:
>
>
>
> On 8/29/2022 10:20 PM, Alex Deucher wrote:
> > On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
> >>
> >> HDP flush is used early in the init sequence as part of memory controller
> >> block initialization. Hence remapping of HDP regist
On Tue, Aug 30, 2022 at 3:08 AM Simon Ser wrote:
>
> On Friday, August 26th, 2022 at 16:39, Alex Deucher
> wrote:
>
> > On Fri, Aug 26, 2022 at 3:38 AM Simon Ser wrote:
> > >
> > > On Thursday, August 25th, 2022 at 20:22, Alex Deucher
> > > wrote:
> > >
> > > > On Wed, Aug 24, 2022 at 11:09 A
On Tuesday, August 30th, 2022 at 16:06, Alex Deucher
wrote:
> On Tue, Aug 30, 2022 at 3:08 AM Simon Ser cont...@emersion.fr wrote:
>
> > On Friday, August 26th, 2022 at 16:39, Alex Deucher alexdeuc...@gmail.com
> > wrote:
> >
> > > On Fri, Aug 26, 2022 at 3:38 AM Simon Ser cont...@emersion.fr
On Tue, Aug 30, 2022 at 10:24 AM Simon Ser wrote:
>
> On Tuesday, August 30th, 2022 at 16:06, Alex Deucher
> wrote:
>
> > On Tue, Aug 30, 2022 at 3:08 AM Simon Ser cont...@emersion.fr wrote:
> >
> > > On Friday, August 26th, 2022 at 16:39, Alex Deucher alexdeuc...@gmail.com
> > > wrote:
> > >
>
On 8/30/2022 7:18 PM, Alex Deucher wrote:
On Tue, Aug 30, 2022 at 12:05 AM Lazar, Lijo wrote:
On 8/29/2022 10:20 PM, Alex Deucher wrote:
On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
HDP flush is used early in the init sequence as part of memory controller
block initialization. He
On Tuesday, August 30th, 2022 at 16:42, Alex Deucher
wrote:
> > Hm, can you elaborate on the difference between "immediate flip" (as in
> > UNP_FLIP_CONTROL) and GRPH_SURFACE_UPDATE_H_RETRACE_EN? What are their
> > relationship with KMS's concept of "async flips"?
>
> The display surface regist
On Tue, Aug 30, 2022 at 10:45 AM Lazar, Lijo wrote:
>
>
>
> On 8/30/2022 7:18 PM, Alex Deucher wrote:
> > On Tue, Aug 30, 2022 at 12:05 AM Lazar, Lijo wrote:
> >>
> >>
> >>
> >> On 8/29/2022 10:20 PM, Alex Deucher wrote:
> >>> On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
>
> HDP f
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
engine exists and map/unmap SDMA queues to the non-existent engine.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 8
1
On Tue, Aug 30, 2022 at 11:24 AM Yifan Zhang wrote:
>
> there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
> zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
> engine exists and map/unmap SDMA queues to the non-existent engine.
>
> Signed-off-by: Yifan Zha
On 2022-08-30 02:00, Christian König wrote:
Am 29.08.22 um 21:30 schrieb Felix Kuehling:
Am 2022-08-29 um 14:59 schrieb Christian König:
Am 29.08.22 um 18:07 schrieb Felix Kuehling:
Am 2022-08-29 um 11:38 schrieb Christian König:
Am 27.08.22 um 01:16 schrieb Felix Kuehling:
BOs can be in a d
On 8/30/2022 8:39 PM, Alex Deucher wrote:
On Tue, Aug 30, 2022 at 10:45 AM Lazar, Lijo wrote:
On 8/30/2022 7:18 PM, Alex Deucher wrote:
On Tue, Aug 30, 2022 at 12:05 AM Lazar, Lijo wrote:
On 8/29/2022 10:20 PM, Alex Deucher wrote:
On Mon, Aug 29, 2022 at 4:18 AM Lijo Lazar wrote:
[Public]
Hi all,
This week this patchset was tested on the following systems:
Sapphire Pulse RX5700XT
Reference AMD RX6800
Engineering board with Ryzen 9 5900H
These systems were tested on the following display types:
eDP, (1080p 60hz)
VGA and DVI (1680x1050 60HZ [DP to VGA/DVI, USB-C to D
From: YiPeng Chai
[ Upstream commit 9d705d7741ae70764f3d6d87e67fad3b5c30ffd0 ]
V1:
The amdgpu_xgmi_remove_device function will send unload command
to psp through psp ring to terminate xgmi, but psp ring has been
destroyed in psp_hw_fini.
V2:
1. Change the commit title.
2. Restore amdgpu_xgmi_re
From: YiPeng Chai
[ Upstream commit f5994da72ba124a3d0463672fdfbec073e3bb72f ]
Only amdgpu_get_xgmi_hive but no amdgpu_put_xgmi_hive
which will leak the hive reference.
Signed-off-by: YiPeng Chai
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: shaoyunl
[ Upstream commit 06671734881af2bcf7f453661b5f8616e32bb3fc ]
The additional call is caused by merge conflict
Reviewed-by: Felix Kuehling
Signed-off-by: shaoyunl
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
1 fi
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Tim Huang
[ Upstream commit 00047c3d967d7ef8adf8bac3c3579294a3bc0bb1 ]
For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,
so not need to configure SDMA1_RLC_CGCG_CTRL for this case.
Signed-off-by: Tim Huang
Reviewed-by: Yifan Zhang
Signed-off-by: Alex Deucher
Signed-off-
From: Qu Huang
[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ]
The mmVM_L2_CNTL3 register is not assigned an initial value
Signed-off-by: Qu Huang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 inserti
From: YiPeng Chai
[ Upstream commit 9d705d7741ae70764f3d6d87e67fad3b5c30ffd0 ]
V1:
The amdgpu_xgmi_remove_device function will send unload command
to psp through psp ring to terminate xgmi, but psp ring has been
destroyed in psp_hw_fini.
V2:
1. Change the commit title.
2. Restore amdgpu_xgmi_re
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Qu Huang
[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ]
The mmVM_L2_CNTL3 register is not assigned an initial value
Signed-off-by: Qu Huang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 inserti
From: YiPeng Chai
[ Upstream commit 9d705d7741ae70764f3d6d87e67fad3b5c30ffd0 ]
V1:
The amdgpu_xgmi_remove_device function will send unload command
to psp through psp ring to terminate xgmi, but psp ring has been
destroyed in psp_hw_fini.
V2:
1. Change the commit title.
2. Restore amdgpu_xgmi_re
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: Qu Huang
[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ]
The mmVM_L2_CNTL3 register is not assigned an initial value
Signed-off-by: Qu Huang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 inserti
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Qu Huang
[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ]
The mmVM_L2_CNTL3 register is not assigned an initial value
Signed-off-by: Qu Huang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 inserti
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Qu Huang
[ Upstream commit b8983d42524f10ac6bf35bbce6a7cc8e45f61e04 ]
The mmVM_L2_CNTL3 register is not assigned an initial value
Signed-off-by: Qu Huang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 inserti
From: Candice Li
[ Upstream commit c351938350ab9b5e978dede2c321da43de7eb70c ]
No need to set up rb when no gfx rings.
Signed-off-by: Candice Li
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
1 file change
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
From: Zhenneng Li
[ Upstream commit f461950fdc374a3ada5a63c669d997de4600dffe ]
Although radeon card fence and wait for gpu to finish processing current batch
rings,
there is still a corner case that radeon lockup work queue may not be fully
flushed,
and meanwhile the radeon_suspend_kms() funct
This series adds support for DRM_MODE_PAGE_FLIP_ASYNC for atomic
commits, aka. "immediate flip" (which might result in tearing).
The feature was only available via the legacy uAPI, however for
gaming use-cases it may be desirable to enable it via the atomic
uAPI too.
- v1: https://patchwork.freede
Up until now, amdgpu was silently degrading to vsync when
user-space requested an async flip but the hardware didn't support
it.
The hardware doesn't support immediate flips when the update changes
the FB pitch, the DCC state, the rotation, enables or disables CRTCs
or planes, etc. This is reflect
This is a subset of [1], included here because a subsequent patch
needs to document the behavior of this flag under the atomic uAPI.
v2: new patch
[1]: https://patchwork.freedesktop.org/patch/500177/
Signed-off-by: Simon Ser
---
include/uapi/drm/drm_mode.h | 7 +++
1 file changed, 7 insert
This new field indicates whether the driver has the necessary logic
to support async page-flips via the atomic uAPI. This is leveraged by
the next commit to allow user-space to use this functionality.
All atomic drivers setting drm_mode_config.async_page_flip are updated
to also set drm_mode_confi
If the driver supports it, allow user-space to supply the
DRM_MODE_PAGE_FLIP_ASYNC flag to request an async page-flip.
Set drm_crtc_state.async_flip accordingly.
Document that drivers will reject atomic commits if an async
flip isn't possible. This allows user-space to fall back to
something else.
This new kernel capability indicates whether async page-flips are
supported via the atomic uAPI. DRM clients can use it to check
for support before feeding DRM_MODE_PAGE_FLIP_ASYNC to the kernel.
Make it clear that DRM_CAP_ASYNC_PAGE_FLIP is for legacy uAPI only.
Signed-off-by: Simon Ser
Cc: Dan
amdgpu_dm_commit_planes() already sets the flip_immediate flag for
async page-flips. This flag is used to set the UNP_FLIP_CONTROL
register. Thus, no additional change is required to handle async
page-flips with the atomic uAPI.
v2: make it clear this commit is about DC and not only DCN
Signed-of
On Tue, Aug 30, 2022 at 12:06 PM Lazar, Lijo wrote:
>
>
>
> On 8/30/2022 8:39 PM, Alex Deucher wrote:
> > On Tue, Aug 30, 2022 at 10:45 AM Lazar, Lijo wrote:
> >>
> >>
> >>
> >> On 8/30/2022 7:18 PM, Alex Deucher wrote:
> >>> On Tue, Aug 30, 2022 at 12:05 AM Lazar, Lijo wrote:
>
>
> >>
From: Horace Chen
For further chips we will use CHIP_IP_DISCOVERY, so add this
support for virtualization
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drive
From: Yifan Zha
[Why]
VF should not program these registers, the value were defined in the host.
[How]
Skip writing them in SRIOV environment and program them on host side.
Signed-off-by: Yifan Zha
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
driver
From: Horace Chen
[Why]
under SR-IOV, the nbio doorbell range will be defined by PF. So VF
nbio doorbell range registers will be blocked. It will cause violation
if VF access those registers directly.
[How]
create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
skip the setting fo
From: Horace Chen
Add support for PSP 13.0.10 for SR-IOV VF
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 62
drivers/gpu/drm/amd/a
From: Horace Chen
SRIOV needs to initialize mmsch instead of multimedia engines
directly. So currently remove them for SR-IOV until the code and
firmwares are ready.
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discov
From: Yifan Zha
[Why]
With L1 Policy applied, IH_RB_CNTL/RING cannot be accessed by VF.
[How]
Use PSP program IH_RB_CNTL in VF.
Signed-off-by: Yifan Zha
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 26 +
From: Horace Chen
[Why]
Under SR-IOV, we are not sure whether pipe status is
good or not when doing initialization. The compute engine
maybe fail to bringup if pipe status is bad.
[How]
Do an RS64 pipe reset for MEC before we do initialization.
Also apply to bare-metal.
Signed-off-by: Horace Ch
From: Horace Chen
[Why]
Under SR-IOV, if VF is switched out then its doorbell will be disabled,
SDMA rely on WPTR_POLL to get doorbells which was sent during VF
switched-out time.
[How]
For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1.
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-of
From: Yifan Zha
[Why]
vm_l2_bank_select_reserved_cid2 is a PF_only register
that cannot be programmed by VF. This feature is only
support HDP using GPUVM page tables to access FB memory
which should be disabled on SRIOV.
[How]
Disable the feature on VF.
Signed-off-by: Yifan Zha
Signed-off-by:
From: Yifan Zha
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.
[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio
directly access.
Signed-off-by: Yifan Zha
Reviewed-by:
From: Yifan Zha
[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.
[How]
Do not set any cg/pg flag bit at early init under sriov.
Signed-off-by: Yifan Zha
Revie
From: Horace Chen
SR-IOV may need to load different firmwares for different ASIC inside
VF.
So create a new function in amdgpu_virt to check whether FW load needs
to be skipped.
Signed-off-by: Horace Chen
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/a
From: Jane Jian
These structures are basically ported from MMSCH v3_0,
besides, added RB and RB4 enablement flag to support
unified queue
Signed-off-by: Jane Jian
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmsch_v4_0.h | 140
From: Yifan Zha
[Why]
VF do not need to handle SMU IRQ state.
L1 Policy will block VF access THM_THERMAL_INT_CTRL and MP1_SMN_IH_SW_INT/CNTL.
[How]
Skip smu_v13 init register_irq_handler under SRIOV VF.
And add irq_src check in enable/disable thermal alert
to avoid thermal alert enable/disable f
From: Yifan Zha
[Why]
As VF cannot read MMMC_VM_FB_OFFSET with L1 Policy(read 0x).
It leads to driver get the incorrect vram base offset.
[How]
Since SR-IOV is dGPU only, skip reading this register and set the
fb_offest to 0.
Signed-off-by: Yifan Zha
Signed-off-by: Horace Chen
Reviewe
From: Yifan Zha
[Why]
As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register,
L1 would block this register for VF access.
[How]
VF do not program it.
Signed-off-by: Yifan Zha
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 ++-
1 file c
From: Jane Jian
Previously since vcn0/vcn1 are not enabled, loading firmware
is skipped. Now add firmware loading back since vcn0/vcn1
has already been enabled on sriov
Signed-off-by: Jane Jian
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.
From: Jane Jian
For sriov, CG and MG are controlled from hypervisor side,
no need to manage them again in ip init
Signed-off-by: Jane Jian
Reviewed-by: Sonny Jiang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +
1 file changed, 5 inser
From: Jane Jian
Enable unified queue support for sriov, abandon all previous
multi-queue settings
Signed-off-by: Jane Jian
Reviewed-by: Ruijing Dong
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 13 +
On 2022-08-11 11:48, Rodrigo Siqueira wrote:
> This patchset introduces some new AMDGPU documentation. You will find:
>
> 1. A CSV table that maps which component version is part of some ASIC
> families. This can be useful to narrow down bugs;
> 2. Some explanation about AMD Display Pipeline;
>
Applied. Thanks!
Alex
On Tue, Aug 30, 2022 at 4:32 AM wrote:
>
> From: ye xingchen
>
> Return the value sdma_v4_0_start() directly instead of storing it in
> another redundant variable.
>
> Reported-by: Zeal Robot
> Signed-off-by: ye xingchen
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |
Hi all,
This series aims to address the following warnings, which are visible
when building x86_64 allmodconfig with clang after commit 3876a8b5e241
("drm/amd/display: Enable building new display engine with KCOV
enabled").
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer created at the
top of dml32_ModeSupportAndSystemConfigurationFull(). This reduces the
total amount of stack space that
dml32_ModeSupportAndSystemConfigurationFull() uses
Several of the arguments are identical between the two call sites and
they can be accessed through the 'struct vba_vars_st' pointer. This
reduces the total amount of stack space that
dml32_ModeSupportAndSystemConfigurationFull() uses by 208 bytes with
LLVM 16 (1936 -> 1728), helping clear up the fo
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
dml31_ModeSupportAndSystemConfigurationFull() uses by 240 bytes with
LLVM 16 (2216 -> 1976), helping clear up the follo
Most of the arguments are identical between the two call sites and they
can be accessed through the 'struct vba_vars_st' pointer. This reduces
the total amount of stack space that
dml31_ModeSupportAndSystemConfigurationFull() uses by 112 bytes with
LLVM 16 (1976 -> 1864), helping clear up the follo
This function consumes a lot of stack space and it blows up the size of
dml30_ModeSupportAndSystemConfigurationFull() with clang:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3542:6:
error: stack frame size (2200) exceeds limit (2048) in
'dml30_ModeSupportAndSystem
On Fri, Aug 26, 2022 at 10:31:34AM -0400, Alex Deucher wrote:
> On Thu, Aug 25, 2022 at 6:34 PM Nathan Chancellor wrote:
> >
> > Hi AMD folks,
> >
> > Top posting because it might not have been obvious but I was looking for
> > your feedback on this message (which can be viewed on lore.kernel.org
On 2022-08-29 10:30, Jonathan Kim wrote:
The debugger must be notified by any debugger subscribed exception
that comes from hardware interrupts.
Debugger notification must be scheduled as HW state may be unknown
when receiving an exception that could require an immediate process
eviction.
I
Document missing parameter.
Fixes: 8889a13f99e5 ("drm/amd/display: Add some extra kernel doc to amdgpu_dm")
Reported-by: Stephen Rothwell
Signed-off-by: Alex Deucher
Cc: Rodrigo Siqueira
Cc: Harry Wentland
---
v2: fix aconnector too.
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
On 2022-08-29 10:29, Jonathan Kim wrote:
Introduce the GPU debug operations interface.
For ROCm-GDB to extend the GNU Debugger's ability to inspect the AMD GPU
instruction set, provide the necessary interface to allow the debugger
to HW debug-mode set and query exceptions per HSA queue, proces
[Public]
OK, that's a better solution.
Best Regards,
Yifan
-Original Message-
From: Alex Deucher
Sent: Tuesday, August 30, 2022 11:31 PM
To: Zhang, Yifan
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Huang, Tim ; Xiao, Jack
; Du, Xiaojian
Subject: Re: [PATCH] drm/amdgpu/
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
engine exists and map/unmap SDMA queues to the non-existent engine.
Signed-off-by: Yifan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +++
1 file
[AMD Official Use Only - General]
Reviewed-by: Tim Huang
Best Regards,
Tim Huang
-Original Message-
From: Zhang, Yifan
Sent: Wednesday, August 31, 2022 8:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Tim ; Deucher, Alexander
; Du, Xiaojian ; Xiao, Jack
; Zhang, Yifan
Subject:
There are duplicated declarations of i, remove one of those.
Signed-off-by: Asher Song
---
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
b/drivers/gpu/drm/amd/display/
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