Hi, this is your Linux kernel regression tracker speaking.
On 21.01.22 03:13, James Turner wrote:
>
> I finished the bisection (log below). The issue was introduced in
> f9b7f3703ff9 ("drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)").
FWIW, that was:
> drm/amdgpu/acpi: make ATPX/ATCS st
On Wed, 2022-01-19 at 16:00 -0500, Steven Rostedt wrote:
> On Wed, 19 Jan 2022 21:25:08 +0200
> Andy Shevchenko wrote:
>
> > > I say keep it one line!
> > >
> > > Reviewed-by: Steven Rostedt (Google)
> >
> > I believe Sakari strongly follows the 80 rule, which means...
>
> Checkpatch says "
NULL pointer check has guarded it already.
calltrace:
amdgpu_ttm_gart_bind+0x49/0xa0 [amdgpu]
amdgpu_ttm_alloc_gart+0x13f/0x180 [amdgpu]
amdgpu_bo_create_reserved+0x139/0x2c0 [amdgpu]
? amdgpu_ttm_debugfs_init+0x120/0x120 [amdgpu]
amdgpu_bo_create_kernel+0x17/0x80 [amdgpu]
amdgpu_ttm_init+0x542/0x
Implementation of register trace dump function on the AMD GPU resets
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 8
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 53 ++-
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
3 files cha
Register dump call on NV ASIC reset on AMD GPU reset
Signed-off-by: Somalapuram Amaranath
---
drivers/gpu/drm/amd/amdgpu/nv.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 2ec1ffb36b1f..b57017
On 1/21/2022 1:14 PM, Evan Quan wrote:
As it has exactly the same value as the 'enabled' member and also do
the same thing.
I believe the original intention is different. We need to cache the
features which are really supported by PMFW on that device on init. When
a request comes through
[AMD Official Use Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, January 21, 2022 4:52 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Chen, Guchun
> ; Huang, Ray
> Subject: Re: [PATCH 3/7] drm/amd/pm: drop the redundant 'supported'
> memb
Pmfw read ecc info registers in the following order,
umc0: ch_inst 0, 1, 2 ... 7
umc1: ch_inst 0, 1, 2 ... 7
The position of the register value stored in eccinfo
table is calculated according to the below formula,
channel_index = umc_inst * channel_in_umc + ch_inst
Driver directly us
On 1/21/2022 2:56 PM, Quan, Evan wrote:
[AMD Official Use Only]
-Original Message-
From: Lazar, Lijo
Sent: Friday, January 21, 2022 4:52 PM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Chen, Guchun
; Huang, Ray
Subject: Re: [PATCH 3/7] drm/amd/pm: drop
Am 21.01.22 um 09:47 schrieb Guchun Chen:
NULL pointer check has guarded it already.
calltrace:
amdgpu_ttm_gart_bind+0x49/0xa0 [amdgpu]
amdgpu_ttm_alloc_gart+0x13f/0x180 [amdgpu]
amdgpu_bo_create_reserved+0x139/0x2c0 [amdgpu]
? amdgpu_ttm_debugfs_init+0x120/0x120 [amdgpu]
amdgpu_bo_create_kernel
[AMD Official Use Only]
> -Original Message-
> From: Stanley.Yang
> Sent: Friday, January 21, 2022 5:35 PM
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Ziya, Mohammad zafar
> ; Clements, John
> ; Zhou1, Tao
> Cc: Yang, Stanley
> Subject: [PATCH Review 1/1] drm/amdgpu: fix c
The S2idle suspend/resume process seems also depends on the CONFIG_SUSPEND.
Moreover, why this check function still return true even when BIOS/AMDPMC not
configured correctly? You know we still looking into some S0ix abort issue and
system will run into such problem when mark those misconfigured
On 19/01/2022 11:37, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation a
On 19/01/2022 11:37, Arunpravin wrote:
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver
Clean the following coccicheck warning:
./drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c:7035:2-4: WARNING: possible
condition with no effect (if == else).
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +
1 file changed, 1 insertion(+)
It is to meet the requirement for memory allocation
optimization on MI50.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
b/drivers/gpu/drm/amd/amdkfd/kfd_charde
On Fri, Jan 21, 2022 at 3:35 AM Thorsten Leemhuis
wrote:
>
> Hi, this is your Linux kernel regression tracker speaking.
>
> On 21.01.22 03:13, James Turner wrote:
> >
> > I finished the bisection (log below). The issue was introduced in
> > f9b7f3703ff9 ("drm/amdgpu/acpi: make ATPX/ATCS structures
[Public]
It just changes the limit for when we use msleep vs udelay, not the units.
Alex
From: Chen, Guchun
Sent: Thursday, January 20, 2022 8:49 PM
To: Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: RE: [PATCH 1/2] drm/amdg
[Public]
> The S2idle suspend/resume process seems also depends on the
> CONFIG_SUSPEND. Moreover, why this check function still return true even
> when BIOS/AMDPMC not configured correctly? You know we still looking into
> some S0ix abort issue and system will run into such problem when mark thos
[Public]
Please provide a link to the proposed userspace branch that makes use of this.
Alex
From: amd-gfx on behalf of Philip Yang
Sent: Thursday, January 20, 2022 6:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Philip ; Kuehling, Felix
Subject: [PATCH v
On 2022-01-21 06:26, Yongzhi Liu wrote:
> [why]
> Resource release is needed on the error handling path
> to prevent memory leak.
>
> [how]
> Fix this by adding kfree on the error handling path.
>
> Signed-off-by: Yongzhi Liu
Reviewed-by: Harry Wentland
Harry
> ---
> .../drm/amd/display/amd
Earlier chips only had two performance levels, but newer
ones potentially had more. The message is harmless. Drop the
message to avoid spamming the log.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1874
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
We need to set the APU flag from IP discovery before
we evaluate this code.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 13 -
2 files changed, 15 insertions(+), 13 deletions(-)
diff --g
Use the IP versions to set the APU flag when necessary.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
Extend secondary function handling for runtime pm beyond audio
to USB and UCSI.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 30 +++--
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drive
Seems more logical to enable runtime pm at the end of
the init sequence so we don't end up entering runtime
suspend before init is finished.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 65 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 69 +---
Check IP versions rather than asic types.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_displ
From 8144e60d9f80941dd9f8a53e4b468582aaa849b4 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 21 Jan 2022 17:23:41 +0100
Subject: [PATCH 1/4] drm: add a new drm event for GPU reset
This patch adds a DRM uevent to indicate GPU reset event. A
userspace can register to this event and do s
From 1c5c552eeddaffd9fb3e7d45ece1b2b28fccc575 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:10 +0530
Subject: [PATCH 3/4] drm/amdgpu: add reset register trace dump function for
gfx_v10_0
Implementation of register trace dump function on the AMD GPU resets
Si
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:42 +0530
Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler
This patch adds a GPU reset handler for Navi ASIC family, which
typically dumps some of the regi
From c598dd586dd15fc5ae0a883a2e6f4094ec024085 Mon Sep 17 00:00:00 2001
From: Shashank Sharma
Date: Fri, 21 Jan 2022 17:33:10 +0100
Subject: [PATCH 2/4] drm/amdgpu: add work function for GPU reset
This patch adds a new work function, which will get scheduled
in event of a GPU reset, and will send
On Fri, Jan 21, 2022 at 2:45 AM Christian König
wrote:
>
> Am 21.01.22 um 06:28 schrieb Xin Xiong:
> > This issue takes place in an error path in
> > amdgpu_cs_fence_to_handle_ioctl(). When `info->in.what` falls into
> > default case, the function simply returns -EINVAL, forgetting to
> > decremen
Applied. Thanks!
Alex
On Fri, Jan 21, 2022 at 6:48 AM Jiapeng Chong
wrote:
>
> Clean the following coccicheck warning:
>
> ./drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c:7035:2-4: WARNING: possible
> condition with no effect (if == else).
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Cho
[Public]
Applied. Thanks!
From: Wentland, Harry
Sent: Friday, January 21, 2022 2:03 PM
To: Yongzhi Liu ; Li, Sun peng (Leo) ;
Siqueira, Rodrigo ; Deucher, Alexander
; Koenig, Christian ; Pan,
Xinhui ; airl...@linux.ie ;
dan...@ffwll.ch ; Lipski, Mikita ; Lin,
Previous implementation of print_clocks required return of bytes written
to calling function via return value. Passing this value in by reference
allows us now to pass back error codes up the calling stack.
(v1)
- Errors from get_current_clk_freq, get_dpm_level_count & get_dpm_freq
now
(v1)
- new power management function emit_clk_levels implemented by
navi10_emit_clk_levels()
This function currently duplicates the functionality of
navi10_print_clk_levels, where
snprintf is used write to the sysfs buffer. The first implementation to
use sysfs_emit
was
(v1)
Use new API function emit_clock_levels to display to overclocking values,
with a fallback
to the print_clock_levels if the first call fails.
(v2)
Update to apply on commit 801771de03
adjust printing of empty carriage return only if size == 0
== Test ==
LOGFILE=pp_clk.t
== Description ==
Scnprintf use within the kernel is not recommended, but simple sysfs_emit
replacement has
not been successful due to the page alignment requirement of the function. This
patch
set implements a new api "emit_clock_levels" to facilitate passing both the
base and
offset to the dev
[AMD Official Use Only]
Hi James,
Could you provide the pp_dpm_* values in sysfs with and without the patch?
Also, could you try forcing PCIE to gen3 (through pp_dpm_pcie) if it's not in
gen3 when the issue happens?
For details on pp_dpm_*, please check
https://dri.freedesktop.org/docs/drm/gp
On 1/22/2022 2:04 AM, Sharma, Shashank wrote:
From 899ec6060eb7d8a3d4d56ab439e4e6cdd74190a4 Mon Sep 17 00:00:00 2001
From: Somalapuram Amaranath
Date: Fri, 21 Jan 2022 14:19:42 +0530
Subject: [PATCH 4/4] drm/amdgpu/nv: add navi GPU reset handler
This patch adds a GPU reset handler for Navi
40 matches
Mail list logo
