On 8/20/2021 11:02 AM, Joseph Greathouse wrote:
Give every process at most one queue from each SDMA engine.
Previously, we allocated all SDMA engines and queues on a first-
come-first-serve basis. This meant that it was possible for two
processes racing on their allocation requests to each end
[AMD Official Use Only]
Hi Evans
I'm sorry but I don't suggest you manually control the standalone voltage
because it's predefined with the clock value.
A decrease of voltage could hit the hardware critical path. You may need to
change the clock and voltage together, we call it dpm level change.
[AMD Official Use Only]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, August 20, 2021 10:23 PM
> To: Quan, Evan
> Cc: Lazar, Lijo ; Zhu, James ;
> amd-gfx@lists.freedesktop.org; Liu, Leo ; Deucher,
> Alexander ; Chen, Guchun
> ; Pan, Xinhui
> Subject: Re: [PATCH] drm/amdgp
[AMD Official Use Only]
Have to drop this patch as the following errors were observed with it.
[ 87.420822] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying
to reset the VCPU!!!
[ 88.443029] [drm:uvd_v6_0_start [amdgpu]] *ERROR* UVD not responding, trying
to reset the VCPU!!!
This is a supplement for commit below:
"drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend".
Change-Id: I7ff5692fd0c3e880ec8e55a7329469a67e5a1363
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 24
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
As those _sw_fini() APIs follow just after _suspend() APIs.
And the cancel_delayed_work_sync was already called in latter.
Change-Id: I7f092e39242a1ffbc3c29e1fcd7bf31b769b0ef5
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |
[Public]
Series is:
Reviewed-by: Guchun Chen
As we have rooted cause this issue, shall we revert former patch "drm/amdgpu:
disable BACO support for 699F:C7 polaris12 SKU temporarily"?
Regards,
Guchun
-Original Message-
From: Quan, Evan
Sent: Monday, August 23, 2021 4:35 PM
To: amd-g
Adding name filed back to ras_common_if to work around error
injection failure with amdgpuras tool.
Change-Id: I9d181a4153b055e22ac6adeb3b51a521c8c2793b
Signed-off-by: Candice Li
Reviewed-by: John Clements
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 +
1 file changed, 1 insertion(+)
diff -
[Public]
> -Original Message-
> From: Chen, Guchun
> Sent: Monday, August 23, 2021 4:44 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Lazar, Lijo
> ; Zhu, James ; Liu, Leo
> ; Pan, Xinhui
> Subject: RE: [PATCH V2 1/3] drm/amdgpu: add missing cleanups fo
Perform proper cleanups on UVD/VCE suspend: powergate enablement,
clockgating enablement and dpm disablement. This can fix some hangs
observed on suspending when UVD/VCE still using(e.g. issue
"pm-suspend" when video is still playing).
Change-Id: I36f39d9731e0a9638b52d5d92558b0ee9c23a9ed
Signed-of
Change-Id: I779f4fb52ecc661c25c42ced487719f08f3d875d
Signed-off-by: Candice Li
Reviewed-by: John Clements
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 142 +++-
1 file changed, 43 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers
Hi Kenneth,
I understand that changing voltage 'standalone' is not a good idea. In that
case, would it be possible to change the voltage table so that it would
give a lower clock on certain voltage?
For example, I would like to change
sclk 900, vddc: 1050
to
sclk 800, vddc: 1050
Thanks
On Mo
Fixed warnings regarding SPDX license, using "unsigned" instead
of "unsigned int", wrong function parameter name for the
documentation and a space between the function name and "(".
Signed-off-by: Liviu Cheru
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +
1 file changed, 5 inserti
From: Luo penghao
The first assignment is not used. In order to keep the code style
consistency of the whole file, the first 'data' assignment should be
deleted.
The clang_analyzer complains as follows:
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:2608:10: warning:
Although the value storedto 'offset'
Hi,
Le 21/08/2021 à 04:08, CGEL a écrit :
From: Luo penghao
The first assignment is not used. In order to keep the code style
consistency of the whole file, the first 'data' assignment should be
deleted.
The clang_analyzer complains as follows:
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:2608:10:
The wrappers in include/linux/pci-dma-compat.h should go away.
The patch has been generated with the coccinelle script below.
It has been compile tested.
@@
@@
-PCI_DMA_BIDIRECTIONAL
+DMA_BIDIRECTIONAL
@@
@@
-PCI_DMA_TODEVICE
+DMA_TO_DEVICE
@@
@@
-PCI_DMA_FROMDEVICE
+DM
On Mon, Aug 23, 2021 at 1:21 AM Jim Cromie wrote:
>
> DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
> allows users to define a drm.debug style (bitmap) sysfs interface, and
> to specify the desired mapping from bits[0-N] to the format-prefix'd
> pr_debug()s to be controlled.
On Mon, Aug 23, 2021 at 3:59 AM Quan, Evan wrote:
>
> [AMD Official Use Only]
>
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Friday, August 20, 2021 10:23 PM
> > To: Quan, Evan
> > Cc: Lazar, Lijo ; Zhu, James ;
> > amd-gfx@lists.freedesktop.org; Liu, Leo ; Deucher,
> > Al
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p
60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI),
1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD
On August 22, 2021 11:28:54 PM PDT, "Christian König"
wrote:
>
>
>Am 19.08.21 um 22:14 schrieb Kees Cook:
>> [...]
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 96e895d6be35..4605934a4fb7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu
On Sat, Aug 21, 2021 at 4:46 AM Liviu Cheru wrote:
>
> Fixed warnings regarding SPDX license, using "unsigned" instead
> of "unsigned int", wrong function parameter name for the
> documentation and a space between the function name and "(".
>
In general, please split these up by the type of chang
On 2021-08-23 2:50 a.m., Christian König wrote:
Good mornings guys,
Andrey has a rather valid concern here, but I think we need to
approach this from a more high level view.
When hw_fini is called we should make sure that the scheduler can't
submit any more work to the hardware, because th
Am 2021-08-23 um 3:08 a.m. schrieb Lazar, Lijo:
>
>
> On 8/20/2021 11:02 AM, Joseph Greathouse wrote:
>> Give every process at most one queue from each SDMA engine.
>> Previously, we allocated all SDMA engines and queues on a first-
>> come-first-serve basis. This meant that it was possible for two
Applied. Thanks!
Alex
On Mon, Aug 23, 2021 at 2:17 AM Christian König
wrote:
>
> Am 22.08.21 um 23:23 schrieb Christophe JAILLET:
> > The wrappers in include/linux/pci-dma-compat.h should go away.
> >
> > The patch has been generated with the coccinelle script below.
> >
> > It has been compile
kfd_chardev.c contains the ioctl API, but not the whole implementation
of everything. I think it would make sense to move the criu_dump_queue*
functions into kfd_process_queue_manager.c.
Regards,
Felix
Am 2021-08-19 um 9:37 a.m. schrieb David Yat Sin:
> Add support to existing CRIU ioctl's to
Am 2021-08-19 um 9:37 a.m. schrieb David Yat Sin:
> When re-creating queues during CRIU restore, restore the queue with the
> same queue id value used during CRIU dump. Adding a new private
> structure queue_restore_data to store queue restore information.
The sentence about the queue_restore_data
On Mon, Aug 23, 2021 at 12:41 AM Andy Shevchenko
wrote:
>
> On Mon, Aug 23, 2021 at 1:21 AM Jim Cromie wrote:
> >
> > DEFINE_DYNAMIC_DEBUG_CATEGORIES(name, var, bitmap_desc, @bit_descs)
> > allows users to define a drm.debug style (bitmap) sysfs interface, and
> > to specify the desired mapping f
Am 2021-08-19 um 9:37 a.m. schrieb David Yat Sin:
> Add support to existing CRIU ioctl's to save and restore events during
> criu checkpoint and restore.
>
> Signed-off-by: David Yat Sin
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 130 +++-
> drivers/gpu/drm/amd/amdkfd/kfd_events
Am 2021-08-19 um 9:36 a.m. schrieb David Yat Sin:
> From: Rajneesh Bhardwaj
>
> Checkpoint-Restore in userspace (CRIU) is a powerful tool that can
> snapshot a running process and later restore it on same or a remote
> machine but expects the processes that have a device file (e.g. GPU)
> associ
Am 2021-08-19 um 9:37 a.m. schrieb David Yat Sin:
> When doing a restore on a different node, the gpu_id's on the restore
> node may be different. But the user space application will still refer
> use the original gpu_id's in the ioctl calls. Adding code to create a
> gpu id mapping so that kfd c
[Public]
> -Original Message-
> From: Koenig, Christian
> Sent: Monday, August 23, 2021 3:02 PM
> To: Kees Cook ; Lazar, Lijo
>
> Cc: Pan, Xinhui ; David Airlie ;
> Daniel Vetter ; Zhang, Hawking
> ; Xu, Feifei ; Gao, Likun
> ; Gu, JiaWei (Will) ; Quan,
> Evan ; amd-gfx@lists.freedesktop
On Mon, Aug 23, 2021 at 3:43 PM Borislav Petkov wrote:
>
> Hi folks,
>
> I'm seeing this:
>
> ERROR: modpost: "pm_suspend_target_state"
> [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
> make[1]: *** [scripts/Makefile.modpost:150: modules-only.symvers] Error 1
> make[1]: *** Deleting file 'mod
You haven't implemented objects_index_start yet. I think this is only
important later on for dumping BOs with dmabuf handles to avoid
exhausting the file-descriptor limit. For now, there should at least be
a check for objects_index_start == 0. We can fail if it's not 0 and
implement that support la
On Mon, Aug 23, 2021 at 03:49:39PM -0400, Alex Deucher wrote:
> Maybe fixed with this patch?
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5706cb3c910cc8283f344bc37a889a8d523a2c6d
Nope, this one is already in:
$ git tag --contains 5706cb3c910cc8283f344bc37a889a8d
On Mon, Aug 23, 2021 at 4:27 PM Borislav Petkov wrote:
>
> On Mon, Aug 23, 2021 at 03:49:39PM -0400, Alex Deucher wrote:
> > Maybe fixed with this patch?
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5706cb3c910cc8283f344bc37a889a8d523a2c6d
>
> Nope, this one is
Am 23.08.21 um 16:23 schrieb Kees Cook:
On August 22, 2021 11:28:54 PM PDT, "Christian König"
wrote:
Am 19.08.21 um 22:14 schrieb Kees Cook:
[...]
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 96e895d6be35..4605934a4fb7 100644
--- a/drivers/gp
On Mon, Aug 23, 2021 at 4:46 PM Borislav Petkov wrote:
>
> On Mon, Aug 23, 2021 at 04:31:42PM -0400, Alex Deucher wrote:
> > Thanks. I think that should do the trick. Care to send that as a
> > formal patch?
>
> Sure, but let me run it through the randconfigs tests first to make sure
> nothing els
On Mon, Aug 23, 2021 at 04:31:42PM -0400, Alex Deucher wrote:
> Thanks. I think that should do the trick. Care to send that as a
> formal patch?
Sure, but let me run it through the randconfigs tests first to make sure
nothing else breaks. It is late here so if I don't manage now I'll send
you a fo
On systems with multiple SH per SE compute_static_thread_mgmt_se#
is split into independent masks, one for each SH, in the upper and
lower 16 bits. We need to detect this and apply cu masking to each
SH. The cu mask bits are assigned first to each SE, then to
alternate SHs, then finally to higher
Add driver cap firmware code path for SRIOV guest driver
Add a new function psp_init_sriov_microcode to make the
code flow more smooth instead of calling amdgpu_sriov_vf()
all over the place
remove the sriov check in psp_v11_0 navi asic since
it is redundant
Change-Id: I42bc8a2f92f09fccf795345e8
On systems with multiple SH per SE compute_static_thread_mgmt_se#
is split into independent masks, one for each SH, in the upper and
lower 16 bits. We need to detect this and apply cu masking to each
SH. The cu mask bits are assigned first to each SE, then to
alternate SHs, then finally to higher
From: Kenneth Feng
[ Upstream commit 2fd31689f9e44af949f60ff4f8aca013e628ab81 ]
This reverts commit 0979d43259e13846d86ba17e451e17fec185d240.
Revert this because it does not apply to all the cards.
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-
From: Kenneth Feng
[ Upstream commit 93c5701b00d50d192ce2247cb10d6c0b3fe25cd8 ]
change the workload type for some cards as it is needed.
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/pm/powerplay/hwmgr/vega
From: Kenneth Feng
[ Upstream commit 2fd31689f9e44af949f60ff4f8aca013e628ab81 ]
This reverts commit 0979d43259e13846d86ba17e451e17fec185d240.
Revert this because it does not apply to all the cards.
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-
From: Kenneth Feng
[ Upstream commit 93c5701b00d50d192ce2247cb10d6c0b3fe25cd8 ]
change the workload type for some cards as it is needed.
Signed-off-by: Kenneth Feng
Reviewed-by: Hawking Zhang
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/drm/amd/pm/powerplay/hwmgr/vega
[AMD Official Use Only]
Got it, Evans.
Since HAINAN is very different, need some further confirmation.
Thanks.
From: amd-gfx On Behalf Of Evans Jahja
Sent: Monday, August 23, 2021 6:40 PM
To: amd-gfx@lists.freedesktop.org
Subject: RE: Voltage control on Southern Island GPU using radeon
[CAUTIO
[AMD Official Use Only]
Hi Evans,
I think you can refer to the code in r600_parse_clk_voltage_dep_table.
And print the value in radeon_table->entries[i].clk(sclk in each level), then
override it to a lower value.
Thanks.
From: Feng, Kenneth
Sent: Tuesday, August 24, 2021 8:26 AM
To: Evans Jahja
On 8/23/2021 10:34 PM, Felix Kuehling wrote:
Am 2021-08-23 um 3:08 a.m. schrieb Lazar, Lijo:
On 8/20/2021 11:02 AM, Joseph Greathouse wrote:
Give every process at most one queue from each SDMA engine.
Previously, we allocated all SDMA engines and queues on a first-
come-first-serve basis.
Adding a new priority level DRM_SCHED_PRIORITY_VERY_HIGH
Signed-off-by: Satyajit Sahu
---
include/drm/gpu_scheduler.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index d18af49fd009..d0e5e234da5f 100644
--- a/include/drm/gpu_schedu
Am 24.08.21 um 07:55 schrieb Satyajit Sahu:
There are multiple rings available in VCE. Map each ring
to different priority.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 15 +++
2 files
I haven't followed the previous discussion, but that looks like this
change is based on a misunderstanding.
Those here are the software priorities used in the scheduler, but what
you are working on are the hardware priorities.
That are two completely different things which we shouldn't mix up
There are multiple rings available in VCN encode. Map each ring
to different priority.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 14 ++
2 files changed, 28 insertions(+)
diff --git a/driver
Adding a new priority level DRM_SCHED_PRIORITY_VERY_HIGH
Signed-off-by: Satyajit Sahu
---
include/drm/gpu_scheduler.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index d18af49fd009..d0e5e234da5f 100644
--- a/include/drm/gpu_schedu
Map UMD priority level to properly to drm sched priorrity.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index b
Schedule the encode job properly in the VCE/VCN encode
rings based on the priority set by UMD.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++--
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 +
There are multiple rings available in VCE. Map each ring
to different priority.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 14 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 15 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/
Am 24.08.21 um 07:55 schrieb Satyajit Sahu:
Schedule the encode job properly in the VCE/VCN encode
rings based on the priority set by UMD.
Signed-off-by: Satyajit Sahu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++--
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4
> -Original Message-
> From: Lazar, Lijo
> Sent: Monday, August 23, 2021 11:37 PM
> To: Kuehling, Felix ; Greathouse, Joseph
> ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH 1/3] drm/amdkfd: Allocate SDMA engines more fairly
>
> On 8/23/2021 10:34 PM, Felix Kuehling wrote:
> >
[AMD Official Use Only]
Please add a dev_warn in default case to let users know they might issue a
wrong query operation. Other than that, the patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Clements, John
Sent: Tuesday, August 24, 2021 14:49
To: amd-gfx@lists.freedesktop.org; Zha
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