s/than/then/
Signed-off-by: Christophe JAILLET
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 89ebbf363e27..1476236f5c7c 100644
--- a/drivers/gpu
remove no need variable, just return the DC_OK
Signed-off-by: Bernard Zhao
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn1
[AMD Official Use Only - Internal Distribution Only]
Submitting patch to disable PSP FW attestation support on APU
Thank you,
John Clements
0001-drm-amdgpu-Update-psp-fw-attestation-support-list.patch
Description: 0001-drm-amdgpu-Update-psp-fw-attestation-support-list.patch
Hi John,
I think it's better to replace
if (adev->flags & AMD_IS_APU)
with
if (adev->asic_type >= CHIP_VANGOGH)
As you say, rembrandt should support this feature.
BR,
Changfeng.
From: Clements, John
Sent: Monday, June 7, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Changfeng
Subje
if (adev->asic_type == CHIP_VANGOGH)
BR,
Changfeng.
From: amd-gfx On Behalf Of Zhu,
Changfeng
Sent: Monday, June 7, 2021 11:24 AM
To: Clements, John ; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: Update psp fw attestation support list
Hi John,
I think it's better to replace
Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update
psp fw attestation support list".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update
psp fw attestation support list".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On Fri, 4 Jun 2021 19:17:21 +0200
Werner Sembach wrote:
> Add a new general drm property "active bpc" which can be used by graphic
> drivers
> to report the applied bit depth per pixel back to userspace.
>
> While "max bpc" can be used to change the color depth, there was no way to
> check
>
Am 07.06.21 um 09:40 schrieb Maxime Ripard:
Hi,
On Fri, Jun 04, 2021 at 07:17:21PM +0200, Werner Sembach wrote:
Add a new general drm property "active bpc" which can be used by graphic drivers
to report the applied bit depth per pixel back to userspace.
Just a heads up, we'll need an open so
On Mon, 7 Jun 2021 09:48:05 +0200
Maxime Ripard wrote:
> I've started to implement this for the raspberrypi some time ago.
>
> https://github.com/raspberrypi/linux/pull/4201
>
> It's basically two properties: a bitmask of the available output pixel
> encoding to report both what the display and
Zhu, Changfeng would like to recall the message, "[PATCH] drm/amdgpu: Update
psp fw attestation support list".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Hi John,
As talked offline, the patch fine with apu at present.
Reviewed-by: Changfeng
BR,
Changfeng.
From: Clements, John
Sent: Monday, June 7, 2021 11:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Changfeng
Subject: [PATCH] drm/amdgpu: Update psp fw attestation support list
[AMD Offi
Am 07.06.21 um 09:52 schrieb Pekka Paalanen:
On Fri, 4 Jun 2021 19:17:21 +0200
Werner Sembach wrote:
Add a new general drm property "active bpc" which can be used by graphic drivers
to report the applied bit depth per pixel back to userspace.
While "max bpc" can be used to change the color
The NV12 and VEGA10 share the same interface W/RREG32_SOC15*,
the callback functions in these macros may not be defined,
so NULL pointer must be checked but not in
macro __WREG32_SOC15_RLC__, fixing the lock of NULL pointer check.
Signed-off-by: Peng Ju Zhou
---
drivers/gpu/drm/amd/amdgpu/gfx_v9
Am 05.06.21 um 11:06 schrieb Christophe JAILLET:
s/than/then/
Signed-off-by: Christophe JAILLET
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/
[AMD Official Use Only]
> -Original Message-
> From: Lazar, Lijo
> Sent: Friday, June 4, 2021 8:24 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial
> Dstate
>
>
>
> On 6/4/2021 3
Why: Previously hw fence is alloced separately with job.
It caused historical lifetime issues and corner cases.
The ideal situation is to take fence to manage both job
and fence's lifetime, and simplify the design of gpu-scheduler.
How:
We propose to embed hw_fence into amdgpu_job.
1. We cover the
[AMD Official Use Only]
Hi Lijo,
I got your concern. However, the problem is what amdgpu_smu.c can see is
SMU_FEATURE_x_BIT(e.g. SMU_FEATURE_BACO_BIT) related.
While the bit mask stored in feature->enabled is FEATURE_x_BIT(e.g.
FEATURE_BACO_BIT which is asic specific) related.
So, a SMU
[Public]
What about separating to smu_cmn_utils.c/smu_utils.c or similar which is meant
for software based common/util functions? In general, it will have sw based
common funcs (not ASIC specific) and may be used outside (for ex: in
amdgpu_smu.c). smu_cmn continues to have the hw based common/
[AMD Official Use Only]
Hi Alex
The following patch series were ported from amd-staging-dkms to fix VCN IB test
fail.
Can you help to review it?
[PATCH 1/2] drm/amd/amdgpu: Use IP discovery data to determine VCN enablement
instead of MMSCH
[PATCH 2/2] drm/amd/amdgpu: add instance_number check i
[Public]
Thanks, that explains.
You may modify the comment to something like " amdgpu_get_audio_func() makes a
PMFW-aware D-state transition to update audio dev's D-state in PMFW" (now it
gives the impression that function makes audio dev to stay in D0 state).
> > +* Via amdgpu_g
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Monday, June 7, 2021 4:19 PM
> To: Quan, Evan ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: RE: [PATCH V2 3/5] drm/amdgpu: correct the audio function initial
> Dstate
>
> [Public]
>
> Thanks, that explain
[AMD Official Use Only]
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Peng Ju
>Zhou
>Sent: Monday, June 7, 2021 1:55 PM
>To: amd-gfx@lists.freedesktop.org
>Subject: [PATCH] drm/amdgpu: Fixing "Indirect register access for Navi12 sriov"
>for vega10
>
>The NV12 a
Reviewed-by: Nirmoy Das
On 6/5/2021 4:51 PM, Christian König wrote:
For GTT allocations with a GART address the res contains the VMID0
addresses and can't be used for VM handling.
So ignore the res when the pages array is given or we fill the page
tables with nonsense.
Signed-off-by: Christia
From: Colin Ian King
There are two spelling mistakes in dml_print messages, fix these and
clear up checkpatch warning on overly wide line length.
Signed-off-by: Colin Ian King
---
.../drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 10 ++
1 file changed, 6 insertions(+), 4 deletio
Clean up the following includecheck warning:
./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:
dce110_hw_sequencer.h is included more than once.
No functional change.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequenc
Hi,
On Wed, May 12, 2021 at 02:06:56PM +0200, Werner Sembach wrote:
> Hello,
>
> In addition to the existing "max bpc", and "Broadcast RGB/output_csc"
> drm properties I propose 4 new properties: "preferred pixel encoding",
> "active color depth", "active color range", and "active pixel
> encodin
Hi,
On Fri, Jun 04, 2021 at 07:17:21PM +0200, Werner Sembach wrote:
> Add a new general drm property "active bpc" which can be used by graphic
> drivers
> to report the applied bit depth per pixel back to userspace.
Just a heads up, we'll need an open source project that has accepted it
before m
[Public]
Series is
Reviewed-by: Lijo Lazar
-Original Message-
From: Powell, Darren
Sent: Sunday, June 6, 2021 10:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren
Subject: [PATCH v3 0/6] Modify smu_get_power_limit to implement Powerplay API
=== Description ===
modify smu_g
On Mon, Jun 7, 2021 at 8:30 AM Christian König wrote:
>
> Am 07.06.21 um 14:27 schrieb Tiezhu Yang:
> > radeon_suspend_kms() puts the hw in the suspend state (all asics),
> > it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
> > this is a normal cleanup process to avoid more ope
Am 07.06.21 um 16:21 schrieb Eric Huang:
Add the parameter table_freed description on function description.
Signed-off-by: Eric Huang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/
On Fri, Jun 4, 2021 at 4:17 PM Harry Wentland wrote:
>
>
>
> On 2021-06-04 1:01 p.m., Mark Yacoub wrote:
> > From: Mark Yacoub
> >
> > For each CRTC state, check the size of Gamma and Degamma LUTs so
> > unexpected and larger sizes wouldn't slip through.
> >
> > TEST: IGT:kms_color::pipe-invalid
From: Jiansong Chen
[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]
1. eliminate potential array index out of bounds.
2. return meaningful value for failure.
Signed-off-by: Jiansong Chen
Reviewed-by: Jack Gui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/d
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non z
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After this
From: Roman Li
[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]
[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.
[How]
Allocate memory for the DC wrapper t
From: Victor Zhao
[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]
[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.
[How]
Use a psp wptr cache machanism to aovid the change made by attack.
v2: unify chang
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non z
From: Jiansong Chen
[ Upstream commit 5cfc912582e13b05d71fb7acc4ec69ddfa9af320 ]
1. eliminate potential array index out of bounds.
2. return meaningful value for failure.
Signed-off-by: Jiansong Chen
Reviewed-by: Jack Gui
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../gpu/d
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After this
From: Roman Li
[ Upstream commit c5699e2d863f58221044efdc3fa712dd32d55cde ]
[Why]
On resume we perform DMUB hw_init which allocates memory:
dm_resume->dm_dmub_hw_init->dc_dmub_srv_create->kzalloc
That results in memory leak in suspend/resume scenarios.
[How]
Allocate memory for the DC wrapper t
From: Victor Zhao
[ Upstream commit 2370eba9f552eaae3d8aa1f70b8e9eec5c560f9e ]
[Why]
When some tools performing psp mailbox attack, the readback value
of register can be a random value which may break psp.
[How]
Use a psp wptr cache machanism to aovid the change made by attack.
v2: unify chang
From: Bindu Ramamurthy
[ Upstream commit ba8e59773ae59818695d1e20b8939282da80ec8c ]
[Why]
Bandwidth calculations are triggered for non zero streams, and
in case of 0 streams, these calculations were skipped with
pstate status not being updated.
[How]
As the pstate status is applicable for non z
From: Rodrigo Siqueira
[ Upstream commit 33f409e60eb0c59a4d0d06a62ab4642a988e17f7 ]
A few weeks ago, we saw a two cursor issue in a ChromeOS system. We
fixed it in the commit:
drm/amd/display: Fix two cursor duplication when using overlay
(read the commit message for more details)
After this
Am 07.06.21 um 14:27 schrieb Tiezhu Yang:
radeon_suspend_kms() puts the hw in the suspend state (all asics),
it should always call radeon_suspend_kms() in radeon_pci_shutdown(),
this is a normal cleanup process to avoid more operations on radeon,
just remove #ifdef CONFIG_PPC64 and the related co
Kernel test robot throws warning ->
>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
warning: variable 'member_type' is used uninitialized whenever switch
default is taken [-Wsometimes-uninitialized]
default:
^~~
drivers/gpu/drm/amd/amdgpu/../pm/s
From: Wyatt Wood
[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow
From: Evgenii Krasnikov
[WHY]
Currently there is no way to visually identify if there is one or more
layers presented fullscreen on the display
[HOW]
Add new visual confirm colors in get_surface_visual_confirm_color for
planes with layer_index > 0
Signed-off-by: Evgenii Krasnikov
Reviewed-by:
From: Po-Ting Chen
[Why]
To support a new visual confirm mode: swizzle to show the specific
color at the screen border according to different surface swizzle mode.
Currently we only support the Linear mode with red color.
Signed-off-by: Po-Ting Chen
---
.../drm/amd/display/dc/core/dc_hw_sequen
On Sat, Jun 5, 2021 at 8:31 AM Bernard Zhao wrote:
>
> remove no need variable, just return the DC_OK
>
> Signed-off-by: Bernard Zhao
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 6:27 AM Jiapeng Chong
wrote:
>
> Clean up the following includecheck warning:
>
> ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c:
> dce110_hw_sequencer.h is included more than once.
>
> No functional change.
>
> Reported-by: Abaci Robo
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 6:46 AM Christian König
wrote:
>
> Am 05.06.21 um 11:06 schrieb Christophe JAILLET:
> > s/than/then/
> >
> > Signed-off-by: Christophe JAILLET
>
> Acked-by: Christian König
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
> > 1 file
Applied. Thanks!
Alex
On Mon, Jun 7, 2021 at 7:58 AM Colin King wrote:
>
> From: Colin Ian King
>
> There are two spelling mistakes in dml_print messages, fix these and
> clear up checkpatch warning on overly wide line length.
>
> Signed-off-by: Colin Ian King
> ---
> .../drm/amd/display/dc/
Am 2021-06-04 um 10:54 p.m. schrieb Wan Jiabing:
> kfd_svm.h is included duplicately in commit 42de677f7
> ("drm/amdkfd: register svm range").
>
> After checking possible related header files,
> remove the former one to make the code format more reasonable.
>
> Signed-off-by: Wan Jiabing
Rev
That won't work either.
We still need to initialize the control registers and tell the hardware
that we have properly setup the ring buffers.
Just add the error message to psp_reg_program() instead of duplicating
that over and over again.
Christian.
Am 07.06.21 um 19:33 schrieb Khaire, Roh
Defines smu_cmn_get_indep_throttler_status which performs ASIC
independent translation given a corresponding lookup table.
Signed-off-by: Graham Sider
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 13 +
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4
2 files changed, 17 insertions(+
This patch set adds support for a new ASIC independant u64 throttler
status field (indep_throttle_status). Piggybacks off the
gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to
v2_2) to add field.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/include/kgd_pp_interface.h|
Perform dependent to independent throttle status translation
for navi1x.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/p
Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Seperated
into four 16-bit types: power throttlers, current throttlers,
temperature, other.
Signed-off-by: Grah
Perform dependent to independent throttle status translation
for arcturus.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 ---
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/d
Perform dependent to independent throttle status translation
for aldebaran.
Signed-off-by: Graham Sider
---
.../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 27 +++
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
b
Perform dependent to independent throttle status translation
for sienna cichlid.
Signed-off-by: Graham Sider
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 ---
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichli
Perform dependent to independent throttle status translation
for vangogh.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/dri
Perform dependent to independent throttle status translation
for renoir.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
b/drive
[AMD Official Use Only]
You can call psp_init_ta_microcode directly in sriov vf case so you don't need
to initialize unnecessary psp firmware structures.
Regards,
Hawking
-Original Message-
From: amd-gfx On Behalf Of Luo, Zhigang
Sent: Thursday, June 3, 2021 23:32
To: Liu, Shaoyun ; am
[Public]
Okay. I will update the change as you suggested.
Thanks,
Zhigang
-Original Message-
From: Zhang, Hawking
Sent: June 7, 2021 9:52 AM
To: Luo, Zhigang ; Liu, Shaoyun ;
amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 4/5] drm/amdgpu: add psp microcode init for arcturus and
ald
Add the parameter table_freed description on function description.
Signed-off-by: Eric Huang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index b4f189ab672e..9db1b64
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm
Hey, MR created at
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/172, please
help review.
Andrey
On 2021-06-03 10:26 p.m., Alex Deucher wrote:
Code review happens on gitlab now for libdrm.
Alex
On Thu, Jun 3, 2021 at 6:02 PM Grodzovsky, Andrey
wrote:
Is libdrm on gitlab ? I was
Why are the ring 1&2 enabled on SRIOV in the first place?
Christian.
Am 07.06.21 um 16:23 schrieb Rohit Khaire:
This is similar to IH_RB_CNTL programming in
navi10_ih_toggle_ring_interrupts
Signed-off-by: Rohit Khaire
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
1
On 6/7/2021 7:14 PM, Graham Sider wrote:
Perform dependent to independent throttle status translation
for vangogh.
Signed-off-by: Graham Sider
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 38 ++-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers
Great, thanks for all the feedback Lijo. Out of the new bit definitions in
amdgpu_smu.h are there any that currently exist that are more applicable for
these mappings? *_THM_GFX and *_THM_SOC only exist in VanGogh and Renoir. With
the expansion of the MEM and LIQUID bits there is not enough room
[Public]
Acked-by: Alex Deucher
From: amd-gfx on behalf of Xiaomeng Hou
Sent: Monday, June 7, 2021 8:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Hou, Xiaomeng (Matthew)
; Wang, Kevin(Yang)
Subject: [PATCH] drm/amd/pm: fix warning reported by ker
[AMD Public Use]
We don't need RING1 and RING2 functionality for SRIOV afaik.
But looking at the description of the original commit message it affects RING0
too?
" drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)
outstanding log reaches threshold will trigger IH r
Do you have the hash for this commit?
Thanks,
Christian.
Am 07.06.21 um 17:30 schrieb Khaire, Rohit:
[AMD Public Use]
We don't need RING1 and RING2 functionality for SRIOV afaik.
But looking at the description of the original commit message it affects RING0
too?
" drm/amdgpu: add timeout fl
[AMD Public Use]
The hash is 5ea6f9c
Rohit
-Original Message-
From: Koenig, Christian
Sent: June 7, 2021 11:58 AM
To: Khaire, Rohit ; amd-gfx@lists.freedesktop.org;
Deucher, Alexander ; Zhang, Hawking
; Deng, Emily ; Liu, Monk
; Zhou, Peng Ju ; Chen, Horace
Cc: Ming, Davis
Subjec
That's a workaround for bare metal and as far as I know doesn't apply to
SRIOV.
We only need the additional IH rings for page fault handling or log
handling and as far as I know that is incompatible with SRIOV for the
moment. But Felix might have some more updates on this.
So as long as we d
Am 07.06.21 um 08:47 schrieb Werner Sembach:
Am 04.06.21 um 19:30 schrieb Ville Syrjälä:
On Fri, Jun 04, 2021 at 07:17:23PM +0200, Werner Sembach wrote:
This commits implements the "active bpc" drm property for the Intel
GPU driver.
Signed-off-by: Werner Sembach
---
drivers/gpu/drm/i915/d
With SRIOV, the interrupt routing is setup by the hypervisor driver. We
need the secondary IH rings in case the hypervisor enabled rerouting of
page fault interrupts. I'm not sure what the hypervisor driver does today.
Regards,
Felix
Am 2021-06-07 um 12:29 p.m. schrieb Christian König:
> That'
Ah, good point. In this case we should probably rather save than sorry.
Then I suggest to clean up this patch, repeating the psp_reg_program()
and error message is pretty horrible coding style.
Christian.
Am 07.06.21 um 18:36 schrieb Felix Kuehling:
With SRIOV, the interrupt routing is setup
From: Jake Wang
[Why]
During DCC on/off, stutter period is calculated before DCC has fully
transitioned.
This results in incorrect stutter period calculation.
[How]
Trigger a full update when DCC changes between on/off.
Signed-off-by: Jake Wang
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
--
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* DC v3.2.139
* FW v0.0.69
* Improvements across DP, eDP, DMUB, MPO, etc
--
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.68
Aric Cyr (4):
drm/amd/display: Change default policy for MPO with mul
From: Mikita Lipski
[why]
Updating PSR interfaces to allow PSR enablement
per eDP panel.
[how]
- Copying PSR command structures to DC
- Changing function interfaces to pass panel instance
- Communicating with DMUB per link instead of assuming
to use a single one
-Iterating through all PSR capable
From: Jimmy Kizito
[Why & How]
Add support for transmitting training pattern sequences for links whose
encoders have been dynamically assigned.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 ++-
1 fi
From: Nikola Cornij
[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.
From: Wenjing Liu
[why]
Some DPRX will issue CP_IRQ when user disconnects a display
that has been authenticated.
Since display is being disconnecting dpcd read will fail.
This will cause us to attempt HDCP retry on disconnection.
We are adding a 100ms delay before retry.
So we will only start ret
From: "JinZe.Xu"
[Why]
This disablement would be specific for Nav10 and shouldn’t be propagated to the
other programs.
[How]
Power gating is controlled by driver.
Signed-off-by: JinZe.Xu
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../drm/amd/display/dc/dcn302/dcn302_hwseq.c | 34 +
From: Ilya Bakoulin
[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Sung Lee
Acked-by: Stylon Wang
---
.../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 78 +++
.../drm/amd/display/dc/dcn21/d
From: Meenakshikumar Somasundaram
[Why & How]
SET_CONFIG transactions with DMUB is not used and removed.
Signed-off-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4
1 file changed, 4 deletions(-)
diff --
From: Jayendran Ramani
[How]
Add call to get the last used VTOTAL from DC
Signed-off-by: Jayendran Ramani
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 42 +++
drivers/gpu/drm/amd/display/dc/dc_stream.h| 4 ++
.../dc/d
From: Vladimir Stempen
[why]
When OS overrides training link training parameters
for MST device to SST mode, MST resources are not
released and leak of the resource may result crash and
incorrect MST discovery during following hot plugs.
[how]
Retaining sink object to be reused by SST link and
r
From: Mikita Lipski
[why]
Allow specifying which panel to take PSR Residency
measurements from.
[how]
Pass panel instance to DMUB through GPINT in the upper
8 bits of the parameter.
Signed-off-by: Mikita Lipski
Reviewed-by: Nicholas Kazlauskas
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/di
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/d
From: Jimmy Kizito
[Why & How]
Add functionality useful for DP equalization phase of link training to
public interface.
Signed-off-by: Jimmy Kizito
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 22 +--
.../gpu/drm/amd/display/d
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index c0fbcbd4cbfc..356e15c
From: Roman Li
[Why]
We update scaling settings when scaling mode has been changed.
However when changing mode from native resolution the scaling mode previously
set gets ignored.
[How]
Perform scaling settings update on modeset.
Signed-off-by: Roman Li
Reviewed-by: Nicholas Kazlauskas
Acked-
From: Aric Cyr
[Why]
Rearranging pipes with multiple displays and multiple planes cannot be
done atomically and requires a much improved sequence to deal with it.
[How]
To workaround such issues, prefer avoid pipe-split policy for
multidisplay scenarios.
Signed-off-by: Aric Cyr
Reviewed-by: Kr
From: Wesley Chalmers
[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.
Signed-off-by: Wesley Chalmers
Reviewed-by: Dmytro Laktyushkin
Acked-by: Stylon Wang
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 +++
.../gpu/drm/amd/di
From: Roy Chan
[Why]
Found a use case (IPKVM) that DP-VGA active dongle does
not return any EDID and the mentioned commit broke it.
[How]
This reverts "Disconnect non-DP with no EDID"
Signed-off-by: Roy Chan
Reviewed-by: Chris Park
Acked-by: Stylon Wang
---
drivers/gpu/drm/amd/display/dc/co
From: Fangzhi Zuo
[Why & How]
Add debugfs entry to force dsc decoding at PCON when DSC capable
external RX is connected. In such case, it is free to test DSC
decoding at external RX or at PCON.
Signed-off-by: Fangzhi Zuo
Reviewed-by: Hersen Wu
Acked-by: Stylon Wang
---
.../gpu/drm/amd/displa
1 - 100 of 133 matches
Mail list logo
