Re: [PATCH] drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZE

Am 14.05.21 um 08:40 schrieb Huacai Chen: From: Yi Li When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Signed-off-by: Yi Li Signed-off-

Re: [PATCH v3] drm/amdgpu: flush TLB if valid PDE turns into PTE

Am 13.05.21 um 19:19 schrieb Felix Kuehling: Am 2021-05-13 um 12:58 p.m. schrieb Philip Yang: Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read

Re: [PATCH 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Am 13.05.21 um 18:58 schrieb Philip Yang: Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Using a define for the flush type instead of magic numbers would be really nic

Re: [PATCH 1/2] drm/amdgpu: free resources on fence usage query

Am 13.05.21 um 20:00 schrieb Alex Deucher: On Thu, May 13, 2021 at 1:45 PM David M Nieto wrote: Free the resources if the fence needs to be ignored during the ratio calculation Signed-off-by: David M Nieto Series is: Reviewed-by: Alex Deucher Reviewed-by: Christian König Will push it m

[PATCH v4 03/16] drm/amdgpu: Indirect register access for Navi12 sriov - RLC interface

Change RLCG/SOC15 register access interface to triage GC/MMHUB access from MMIO to RLCG. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/soc15_common.h | 46 ++- 2 files changed, 20 insertions(+), 27 deletions(-) d

[PATCH v4 01/16] drm/amdgpu: Indirect register access for Navi12 sriov - new internal macro

Change RLCG/SOC15 register access interface to triage GC/MMHUB access from MMIO to RLCG. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdg

[PATCH v4 04/16] drm/amdgpu: Indirect register access for Navi12 sriov - GFX v10

Change RLCG/SOC15 register access interface to triage GC/MMHUB access from MMIO to RLCG. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 - 2 files changed, 39 insertions(+), 43 deletions(-) di

[PATCH v4 06/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 42 +-- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/am

[PATCH v4 07/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/a

[PATCH v4 02/16] drm/amdgpu: Indirect register access for Navi12 sriov - SOC15 macro

Change RLCG/SOC15 register access interface to triage GC/MMHUB access from MMIO to RLCG. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 31 --- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.

[PATCH v4 05/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10*

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 32 +- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gf

[PATCH v4 09/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c

[PATCH v4 08/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5*

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 78 ++ 1 file changed, 42 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sd

[PATCH v4 15/16] drm/amdgpu: Refine the error report when flush tlb.

there are 2 hubs to flush in the gmc, to make it easier to debug when hub flush failed, refine the logs. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gp

[PATCH v4 10/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c

In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 25 + 2 files changed, 24 insertions(+), 10

[PATCH v4 13/16] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV

KMD should not program these registers, the value were defined in the host, so skip them in the SRIOV environment. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmh

[PATCH v4 12/16] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

use psp to program IH_RB_CNTL* if indirect access for ih enabled in SRIOV environment. Signed-off-by: Victor Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +-- drivers/gpu/drm/amd/amdgpu/nv.c| 2 +- 2 files changed, 18 insertions(+), 3 dele

[PATCH v4 11/16] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2*

From: pengzhou In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Signed-off-by: pengzhou --- drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 37 + 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/

[PATCH v4 14/16] drm/amdgpu: Skip the program of GRBM_CAM* in SRIOV

KMD should not the program these registers, so skip them in the SRIOV environment. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index

[PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface

the interface on gfx v10 updated, the gfx v9 and v10 share the same interface, update v9's interface. Signed-off-by: Peng Ju Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 + 2 files changed, 6 insertions(+), 5 deletions(-) dif

Re: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors

Am 13.05.21 um 21:37 schrieb Luben Tuikov: On 2021-05-13 3:56 a.m., Christian König wrote: Am 12.05.21 um 19:03 schrieb Luben Tuikov: On QUERY2 IOCTL don't query counts of correctable and uncorrectable errors, since when RAS is enabled and supported on Vega20 server boards, this takes insurmo

Re: [PATCH 2/2] drm/amdgpu: Poll of RAS errors asynchronously

Am 13.05.21 um 21:34 schrieb Luben Tuikov: On 2021-05-13 4:00 a.m., Christian König wrote: Am 12.05.21 um 19:03 schrieb Luben Tuikov: When using Vega 20 with RAS support and RAS is enabled, the system interactivity is extremely slow, to the point of being unusable. After debugging, it was deter

[PATCH 2/6] drm/amdgpu: switch to cached fw flags for gpu virt cap

Check cached firmware_flags to determine if gpu virtualization is supported in vbios Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 25 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 +- drivers/gpu/d

[PATCH 3/6] drm/amdgpu: switch to cached fw flags for sram ecc cap

Check cached firmware_flags to determine whether sram ecc is supported or not. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 28 ++-- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/dr

[PATCH 1/6] drm/amdgpu: add atomfirmware helper function to query fw cap

Fimware capability was changed from 16 bits to 32 bits for atomfirmware. add helper funciton to query firmware capability and cache the value at early stage. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 3 ++ drivers/gpu/drm/amd/

[PATCH 5/6] drm/amdgpu: add helper function to query dynamic boot config cap

Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 16 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 1 + drivers/gpu/drm/amd/incl

[PATCH 4/6] drm/amdgpu: switch to cached fw flags for mem training cap

Check cached firmware_flags to determin whether two stage mem training is supported or not. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 66 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 2 +- driver

[PATCH 6/6] drm/amdgpu: query boot config cap before issue psp cmd

Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/driver

RE: [PATCH 6/6] drm/amdgpu: query boot config cap before issue psp cmd

[AMD Official Use Only - Internal Distribution Only] Series is: Reviewed-by: John Clements -Original Message- From: Hawking Zhang Sent: Friday, May 14, 2021 3:43 PM To: amd-gfx@lists.freedesktop.org; Deucher, Alexander ; Clements, John Cc: Zhang, Hawking Subject: [PATCH 6/6] drm/amd

RE: [PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface

[AMD Official Use Only - Internal Distribution Only] Hi Felix/Christian As we discussed before, we should access GC registers by RLCG by default in full access time. Using RLCG interface if needed when access other IPs' registers. The patches in the below(have been sent out) are the implementati

[PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

Initialize unique_id from PF2VF under virtualization. V2: skip smu_get_unique_id() under virtualization Signed-off-by: Jiawei Gu --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a

[PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

From: changzhu From: Changfeng There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87 Signed-off-by: Changfeng --- drivers/gpu/drm/amd/amdgpu

RE: [PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[AMD Public Use] Reviewed-by: Chen, Horace horace.c...@amd.com From: Deucher, Alexander Sent: Thursday, May 13, 2021 10:12 PM To: Wang, YuBiao ; amd-gfx@lists.freedesktop.org Cc: Grodzovsky, Andrey ; Quan, Evan ; Chen, Horace ; Tuikov, Luben ; Koenig, Christian ; Xi

Re: [PATCH] drm/amdgpu/nv: remove unused variable

Reviewed-by: Nirmoy Das On 5/13/21 8:41 PM, Alex Deucher wrote: Remove it. Fixes: b8d598968950 ("drm/amdgpu: Complete multimedia bandwidth interface") Signed-off-by: Alex Deucher Cc: Bokun Zhang --- drivers/gpu/drm/amd/amdgpu/nv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers

[PATCH] drm/amd/display: Fix overlay validation by considering cursors

A few weeks ago, we saw a two cursor issue in a ChromeOS system. We fixed it in the commit: drm/amd/display: Fix two cursor duplication when using overlay (read the commit message for more details) After this change, we noticed that some IGT subtests related to kms_plane and kms_plane_scaling s

RE: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

[AMD Official Use Only - Internal Distribution Only] > -Original Message- > From: Borislav Petkov > Sent: Friday, May 14, 2021 3:06 AM > To: Joshi, Mukul > Cc: amd-gfx@lists.freedesktop.org; Kasiviswanathan, Harish > ; x86-ml ; lkml ker...@vger.kernel.org> > Subject: Re: [PATCH] drm/a

[PATCH] drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZE

From: Yi Li When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Signed-off-by: Yi Li Signed-off-by: Huacai Chen --- drivers/gpu/drm/amd/am

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 11:10:34PM +, Joshi, Mukul wrote: > That's probably not the best example to look at. Oh, it is the *perfect* example but... > smca_get_long_name() is used in drivers/edac/mce_amd.c and this file > doesn't get compiled when CONFIG_X86_MCE_AMD is not defined. > > And amd

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Thu, May 13, 2021 at 11:14:30PM +, Joshi, Mukul wrote: > Are you OK with a new MCE priority (MCE_PRIO_ACCEL) or do you want us to use > something else? I still don't know why a separate priority is needed. Maybe this still needs answering: > It is a deferred interrupt that generates an MCE

Re: [PATCH] drm/amdgpu: Fill adev->unique_id with data from PF2VF msg

On Fri, May 14, 2021 at 4:17 AM Jiawei Gu wrote: > > Initialize unique_id from PF2VF under virtualization. > > V2: skip smu_get_unique_id() under virtualization > > Signed-off-by: Jiawei Gu Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 ++ > drivers/gpu/drm/amd/

Re: [PATCH 1/2] drm/amdgpu: free resources on fence usage query

On Fri, May 14, 2021 at 3:26 AM Christian König wrote: > > Am 13.05.21 um 20:00 schrieb Alex Deucher: > > On Thu, May 13, 2021 at 1:45 PM David M Nieto wrote: > >> Free the resources if the fence needs to be ignored > >> during the ratio calculation > >> > >> Signed-off-by: David M Nieto > > Ser

Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

On Fri, May 14, 2021 at 4:20 AM wrote: > > From: changzhu > > From: Changfeng > > There is problem with 3DCGCG firmware and it will cause compute test > hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid > compute hang. > > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87

Re: [PATCH v7 05/16] drm/amdgpu: Handle IOMMU enabled case.

Ping Andrey On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote: Handle all DMA IOMMU gropup related dependencies before the group is removed. v5: Drop IOMMU notifier and switch to lockless call to ttm_tt_unpopulate v6: Drop the BO unamp list v7: Drop amdgpu_gart_fini In amdgpu_ih_ring_fini do u

Re: [PATCH v7 12/16] drm/amdgpu: Fix hang on device removal.

Ping Andrey On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote: If removing while commands in flight you cannot wait to flush the HW fences on a ring since the device is gone. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 16 ++-- 1 file change

[PATCH v2 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- drivers/gp

Re: [PATCH v7 16/16] drm/amdgpu: Unmap all MMIO mappings

Ping Andrey On 2021-05-12 10:26 a.m., Andrey Grodzovsky wrote: Access to those must be prevented post pci_remove v6: Drop BOs list, unampping VRAM BAR is enough. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++--- drivers/gpu/drm/am

Re: [PATCH v2 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Am 14.05.21 um 16:42 schrieb Philip Yang: Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang Reviewed-by: Christian

RE: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

[AMD Public Use] The tests that failed previously for me were: amdgpu/amd_plane -> mpo-swizzle-toggle kms_atomic -> plane-overlay-legacy kms_plane -> plane-position-covered-pipe-a-planes kms_plane -> plane-position-covered-pipe-c-planes kms_plane -> plane-position-hole-dpms-pipe-a-planes kms_plane

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On 2021-05-14 7:47 a.m., Rodrigo Siqueira wrote: > A few weeks ago, we saw a two cursor issue in a ChromeOS system. We > fixed it in the commit: > > drm/amd/display: Fix two cursor duplication when using overlay > (read the commit message for more details) > > After this change, we noticed that

Re: [PATCH] drm/amdgpu: Register bad page handler for Aldebaran

On Fri, May 14, 2021 at 01:06:33PM +, Joshi, Mukul wrote: > We have RAS functionality in other ASICs that is not dependent on > CONFIG_X86_MCE_AMD. So, I don't think we would want to do that just > for one ASIC. Lemme try again: you said that those errors do get reported through a deferred int

Re: [PATCH v2 2/2] drm/amdkfd: heavy-weight flush TLB after unmap

Am 2021-05-14 um 11:14 a.m. schrieb Christian König: > Am 14.05.21 um 16:42 schrieb Philip Yang: >> Need do a heavy-weight TLB flush to make sure we have no more dirty data >> in the cache for the unmapped pages. >> >> Define enum TLB_FLUSH_TYPE, add flush_type parameter to >> amdgpu_amdkfd_flush_g

Re: [PATCH v7 05/16] drm/amdgpu: Handle IOMMU enabled case.

Maybe this patch needs a better explanation how the GART and IH changes relate to IOMMU or what's the problem this is meant to fix. Just looking at the patch I don't see the connection. Looks like just a bunch of refactoring to me. Regards,   Felix Am 2021-05-14 um 10:41 a.m. schrieb Andrey Grod

Re: [PATCH v7 05/16] drm/amdgpu: Handle IOMMU enabled case.

Makes sense - will update. Andrey On 2021-05-14 12:25 p.m., Felix Kuehling wrote: Maybe this patch needs a better explanation how the GART and IH changes relate to IOMMU or what's the problem this is meant to fix. Just looking at the patch I don't see the connection. Looks like just a bunch of

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On Fri, May 14, 2021 at 12:31 PM Mark Yacoub wrote: > > On Fri, May 14, 2021 at 11:28 AM Harry Wentland > wrote: > > > > On 2021-05-14 7:47 a.m., Rodrigo Siqueira wrote: > > > A few weeks ago, we saw a two cursor issue in a ChromeOS system. We > > > fixed it in the commit: > > > > > > drm/amd/d

RE: [PATCH 00/20] DC Patches May 17, 2021

[AMD Public Use] Hi all,   This week this patchset was tested on the following systems: HP Envy 360, with Ryzen 5 4500U, on the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)  

Re: [PATCH v4 15/16] drm/amdgpu: Refine the error report when flush tlb.

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > there are 2 hubs to flush in the gmc, to make it easier > to debug when hub flush failed, refine the logs. > > Signed-off-by: Peng Ju Zhou Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- > 1 file changed,

Re: [PATCH v4 12/16] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > use psp to program IH_RB_CNTL* if indirect access > for ih enabled in SRIOV environment. > > Signed-off-by: Victor > Signed-off-by: Peng Ju Zhou This seems unrelated to the other patches in this group. > --- > drivers/gpu/drm/amd/amdgpu

Re: [PATCH v4 14/16] drm/amdgpu: Skip the program of GRBM_CAM* in SRIOV

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > KMD should not the program these registers, > so skip them in the SRIOV environment. > > Signed-off-by: Peng Ju Zhou Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > dif

Re: [PATCH v4 13/16] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > KMD should not program these registers, the value were > defined in the host, so skip them in the SRIOV environment. > > Signed-off-by: Peng Ju Zhou Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10 +

Re: [RFC PATCH 0/3] A drm_plane API to support HDR planes

On 2021-04-30 6:39 a.m., Shashank Sharma wrote: > Hello Pekka, > > On 30/04/21 15:13, Pekka Paalanen wrote: >> On Wed, 28 Apr 2021 13:24:27 +0530 >> Shashank Sharma wrote: >> >>> Assuming these details, A compositor will look for DRM color properties >>> like these: >>> >>> 1. Degamma plane pr

[PATCH 1/2] drm/amdgpu/pm: Update metrics table

expand metrics table with voltages and frequency ranges Signed-off-by: David M Nieto Change-Id: I2a8d63d0abf613a616518c1d7caf9f5da693e920 --- .../gpu/drm/amd/include/kgd_pp_interface.h| 99 +++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 3 + 2 files changed, 102 inserti

[PATCH 2/2] drm/amdgpu/pm: add new fields for Navi1x

Fill voltage and frequency ranges fields Signed-off-by: David M Nieto Change-Id: I07f926dea46e80a96e1c972ba9dbc804b812d503 --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 434 +- 1 file changed, 417 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu

Re: [RFC PATCH 1/3] drm/color: Add RGB Color encodings

On 2021-04-30 8:53 p.m., Sebastian Wick wrote: > On 2021-04-26 20:56, Harry Wentland wrote: >> On 2021-04-26 2:07 p.m., Ville Syrjälä wrote: >>> On Mon, Apr 26, 2021 at 01:38:50PM -0400, Harry Wentland wrote: From: Bhawanpreet Lakha Add the following color encodings - RGB ver

Re: [RFC PATCH 0/3] A drm_plane API to support HDR planes

On 2021-04-27 10:50 a.m., Pekka Paalanen wrote: > On Mon, 26 Apr 2021 13:38:49 -0400 > Harry Wentland wrote: > >> ## Introduction >> >> We are looking to enable HDR support for a couple of single-plane and >> multi-plane scenarios. To do this effectively we recommend new >> interfaces to drm_plan

Re: [PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > the interface on gfx v10 updated, the gfx v9 and v10 > share the same interface, update v9's interface. > > Signed-off-by: Peng Ju Zhou This should be squashed with patch 4 to avoid a build breakage. > --- > drivers/gpu/drm/amd/amdgpu/amd

[RFC PATCH v2 0/6] A drm_plane API to support HDR planes

We are looking to enable HDR support for a couple of single-plane and multi-plane scenarios. To do this effectively we recommend new interfaces to drm_plane. The first patch gives a bit of background on HDR and why we propose these interfaces. v2: * Moved RFC from cover letter to kernel doc (Dani

[RFC PATCH v2 1/6] drm/doc: Color Management and HDR10 RFC

Use the new DRM RFC doc section to capture the RFC previously only described in the cover letter at https://patchwork.freedesktop.org/series/89506/ Update the RFC based on feedback received: * don't use color_encoding property to define color space * expand on reason for SDR luminance definition

[RFC PATCH v2 2/6] drm/color: Add transfer functions for HDR/SDR on drm_plane

From: Bhawanpreet Lakha Due to the way displays and human vision work it is most effective to encode luminance information in a non-linear space. For SDR this non-linear mapping is assumed to roughly use a gamma 2.2 curve. This was due to the way CRTs worked and was fine for SDR content with a l

[RFC PATCH v2 4/6] drm/color: Add sdr boost property

From: Bhawanpreet Lakha SDR is typically mastered at 200 nits and HDR is mastered at up to 10,000 nits. Due to this luminance range difference if we blend a SDR and HDR plane together, we can run into problems where the HDR plane is too bright or the SDR plane is too dim A common solution to thi

[RFC PATCH v2 3/6] drm/color: Add output transfer function to crtc

We currently have 1D LUTs to define output transfer function but using a 1D LUT is not always the best way to define a transfer function for HW that has ROMs for certain transfer functions, or for HW that has complex PWL definition for accurate LUT definitions. For this reason we're introducing na

[RFC PATCH v2 5/6] drm/color: Add color space plane property

From: Bhawanpreet Lakha Add color space definitions for BT601, BT709, BT2020, and DCI-P3. Default to BT709, the sRGB color space. Signed-off-by: Bhawanpreet Lakha Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../gpu/drm/arm/display/komeda/komeda_pla

[RFC PATCH v2 6/6] drm/amd/display: reformat YCbCr-RGB conversion matrix

Show the CSC matrixes in a 4x3 format. Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 28 + 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dp

Re: [PATCH v4 01/16] drm/amdgpu: Indirect register access for Navi12 sriov - new internal macro

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou wrote: > > Change RLCG/SOC15 register access interface to triage > GC/MMHUB access from MMIO to RLCG. > > Signed-off-by: Peng Ju Zhou I think patches 1-4, 16 need to be squashed together to avoid breaking the build. Please also provide a description

Re: [PATCH] drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZE

Applied. Thanks! Alex On Fri, May 14, 2021 at 3:18 AM Christian König wrote: > > Am 14.05.21 um 08:40 schrieb Huacai Chen: > > From: Yi Li > > > > When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB > > entries which need to update in amdgpu_map_buffer() should be multiplied

Re: [PATCH] drm/amd/display: Fix overlay validation by considering cursors

On Fri, May 14, 2021 at 11:28 AM Harry Wentland wrote: > > On 2021-05-14 7:47 a.m., Rodrigo Siqueira wrote: > > A few weeks ago, we saw a two cursor issue in a ChromeOS system. We > > fixed it in the commit: > > > > drm/amd/display: Fix two cursor duplication when using overlay > > (read the com

Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios

1) Mesa doesn't plan to use this VBIOS query. 2) The patch is changing uapi, which is forbidden. Marek On Tue, May 11, 2021 at 12:35 PM Nieto, David M wrote: > [AMD Public Use] > > The point of having the device ID in the structure is because we are > reading it from the VBIOS header, not the