Hi Alex,
first of all accessing the underlying page of an exported DMA-buf is
illegal! So I'm not 100% sure what you're intentions are here, please
explain further.
Then the reason for TTM not using compound pages is that we can't
guarantee that they are mapped as a whole to userspace.
The
[Why]
When overlay plane is in use and external display
is connected, atomic check will fail.
[How]
Disable overlay plane on multi-monitor scenario
by tying it to single crtc.
Signed-off-by: Pratik Vishwakarma
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
1 file changed, 1 inser
On 2020-10-01 5:06 a.m., Pratik Vishwakarma wrote:
[Why]
When overlay plane is in use and external display
is connected, atomic check will fail.
[How]
Disable overlay plane on multi-monitor scenario
by tying it to single crtc.
Signed-off-by: Pratik Vishwakarma
This will break overlay usage o
We need to schedule the smu AC/DC interrupt ack to avoid
potentially sleeping if the smu message mutex is contended.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
drivers/gpu/drm/amd/
So we can schedule work from interrupts. This might include
long tasks or things that could sleep.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/d
[AMD Public Use]
@@ -2388,6 +2388,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
.deep_sleep_control = smu_v11_0_deep_sleep_control,
.get_fan_parameters = arcturus_get_fan_parameters,
+ .interrupt_work = smu
> that change, the NULL pointer dereference does not occur:
* Please provide a proper tag “Signed-off-by”.
* How do you think about to add the tag “Fixes” to the commit message?
* Would another imperative wording become helpful for the change description?
* Would you like to choose an other pat
On 2020-10-01 9:06 a.m., Kazlauskas, Nicholas wrote:
On 2020-10-01 5:06 a.m., Pratik Vishwakarma wrote:
[Why]
When overlay plane is in use and external display
is connected, atomic check will fail.
[How]
Disable overlay plane on multi-monitor scenario
by tying it to single crtc.
Signed-off-b
On Thu, Oct 1, 2020 at 9:35 AM Zhang, Hawking wrote:
>
> [AMD Public Use]
>
> @@ -2388,6 +2388,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
> .deep_sleep_control = smu_v11_0_deep_sleep_control,
> .get_fan_para
On Wed, Sep 30, 2020 at 4:46 PM Dirk Gouders wrote:
>
> Commit c1cf79ca5ced46 (drm/amdgpu: use IP discovery table for renoir)
> introduced a NULL pointer dereference when booting with
> amdgpu.discovery=0.
>
> For amdgpu.discovery=0 that commit effectively removed the call of
> vega10_reg_base_ini
Save first_wave bit from exec_hi to ttmp1. This allows the high bits
of exec_lo/exec_hi (which hold a 48-bit address) to be cleared in a
follow-up patch.
Signed-off-by: Jay Cornwall
Cc: Laurent Morichetti
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 596 +-
.../amd/amdkfd
ATC and MTYPE fields do not exist in gfx9 or later.
Signed-off-by: Jay Cornwall
Cc: Laurent Morichetti
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 93 ++-
.../amd/amdkfd/cwsr_trap_handler_gfx10.asm| 28 +-
.../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 30 +-
Trap temporary GPRs are not currently saved/restored on ASICs
without scalar store instructions. They contain data useful to a
user-mode debugger.
Use vector store instructons to save TTMPs on these ASICs.
Signed-off-by: Jay Cornwall
Cc: Laurent Morichetti
---
.../gpu/drm/amd/amdkfd/cwsr_trap_
IB_STS bits are saved/restored in both PC and ttmp11 along different
code paths. Use ttmp11 on both paths to remove redundant code.
Signed-off-by: Jay Cornwall
Cc: Laurent Morichetti
---
.../gpu/drm/amd/amdkfd/cwsr_trap_handler.h| 764 +-
.../amd/amdkfd/cwsr_trap_handler_gfx
The series is
Acked-by: Felix Kuehling
I'm hoping Laurent can give it a more through and informed R-b.
Thanks,
Felix
Am 2020-10-01 um 2:24 p.m. schrieb Jay Cornwall:
> ATC and MTYPE fields do not exist in gfx9 or later.
>
> Signed-off-by: Jay Cornwall
> Cc: Laurent Morichetti
> ---
> .../
Hi Christian,
On Thu, 1 Oct 2020, Christian König wrote:
> Hi Alex,
>
> first of all accessing the underlying page of an exported DMA-buf is
> illegal! So I'm not 100% sure what you're intentions are here, please
> explain further.
We have some mapping requirements that I was hoping I could add
[AMD Official Use Only - Internal Distribution Only]
I reviewed and tested the patch series.
Tested-by: Laurent Morichetti
On 10/1/20, 11:34 AM, "Kuehling, Felix" wrote:
The series is
Acked-by: Felix Kuehling
I'm hoping Laurent can give it a more through and informed R-b.
Commit c1cf79ca5ced46 (drm/amdgpu: use IP discovery table for renoir)
introduced a NULL pointer dereference when booting with
amdgpu.discovery=0, because it removed the call of vega10_reg_base_init()
for that case.
Fix this by calling that funcion if amdgpu_discovery == 0 in addition to
the case t
Alex Deucher writes:
> On Wed, Sep 30, 2020 at 4:46 PM Dirk Gouders wrote:
>>
>> Commit c1cf79ca5ced46 (drm/amdgpu: use IP discovery table for renoir)
>> introduced a NULL pointer dereference when booting with
>> amdgpu.discovery=0.
>>
>> For amdgpu.discovery=0 that commit effectively removed th
Dirk Gouders writes:
> Commit c1cf79ca5ced46 (drm/amdgpu: use IP discovery table for renoir)
> introduced a NULL pointer dereference when booting with
> amdgpu.discovery=0, because it removed the call of vega10_reg_base_init()
> for that case.
>
> Fix this by calling that funcion if amdgpu_discov
On Thu, Oct 1, 2020 at 4:33 PM Dirk Gouders wrote:
>
> Dirk Gouders writes:
>
> > Commit c1cf79ca5ced46 (drm/amdgpu: use IP discovery table for renoir)
> > introduced a NULL pointer dereference when booting with
> > amdgpu.discovery=0, because it removed the call of vega10_reg_base_init()
> > for
Recent laptops with dual AMD GPUs fail to suspend the discrete GPU, thus
causing lockups on system sleep and high power consumption at runtime.
The discrete GPU would normally be suspended to D3cold by turning off
ACPI _PR3 Power Resources of the Root Port above the GPU.
However on affected system
Hi Alex,
adding Daniel as well.
Am 01.10.20 um 20:45 schrieb Alex Goins:
Hi Christian,
On Thu, 1 Oct 2020, Christian König wrote:
Hi Alex,
first of all accessing the underlying page of an exported DMA-buf is
illegal! So I'm not 100% sure what you're intentions are here, please
explain furth
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