[AMD Public Use]
Hi Tianci,
My point is, as in the new patch, one new local adev variable is introduced,
then in the same function, for others where smu->adev is used should be replace
by the new local adev as well.
Otherwise, it looks not perfect from coding style's perspective.
Regards,
Guch
Fall back to retrieving the EDID via the ACPI _DDC method, when present
for notebook internal panels, when retrieving BIOS-embedded EDIDs.
Signed-off-by: Daniel Dadap
---
drivers/gpu/drm/radeon/radeon_combios.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
Fall back to retrieving the EDID via the ACPI _DDC method, when present
for notebook internal panels, when EDID retrieval via the standard EDID
paths is unsuccessful.
Signed-off-by: Daniel Dadap
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 6 ++
1 file changed, 6 insertions(+)
diff --g
Fall back to retrieving the EDID via the ACPI _DDC method, when present
for notebook internal panels, when EDID retrieval via the standard EDID
paths is unsuccessful.
Signed-off-by: Daniel Dadap
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-
drivers/gpu/drm/i915/display/intel_lvds.c
Some notebook computer systems expose the EDID for the internal
panel via the ACPI _DDC method. On some systems this is because
the panel does not populate the hardware DDC lines, and on some
systems with dynamic display muxes, _DDC is implemented to allow
the internal panel's EDID to be read at an
Some notebook systems provide the EDID for the internal panel via the
_DDC method in ACPI, instead of or in addition to providing the EDID via
DDC on LVDS/eDP. Add a DRM helper to search for an ACP _DDC method under
the ACPI namespace for each VGA/3D controller, and return the first EDID
successful
bad_page_threshold could be configured to enable/disable the
associated bad page retirement feature in RAS.
When it's -1, ras will use typical bad page failure value to
handle bad page retirement.
When it's 0, disable bad page retirement, and no bad page
will be recorded and saved.
For other val
Bad page threshold value should be valid in the range between
-1 and max records length of eeprom. It could determine when
saved bad pages exceed threshold value, and proceed corresponding
actions.
v2: When using the default typical value, it should be min
value between typical value and eeprom ma
Once the bad page saved to eeprom reaches the configured
threshold, ras recovery will be issued to notify user.
v2: Fix spelling typo.
Signed-off-by: Guchun Chen
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 37 ++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --g
When retrieving bad gpu tag from eeprom, GPU init should
fail as the GPU needs to be retired for further check.
v2: Fix spelling typo, correct the condition to detect
bad gpu tag and refine error message.
v3: Refine function argument name.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd
The series is to enable/disable bad page feature and apply different
bad page reservation strategy by different bad page threshold
configurations.
When the saved bad pages written to eeprom reach the threshold,
one ras recovery will be issued immediately and the recovery will
fail to tell user tha
RAS flags needs to be cleaned as well when user requires
one clean eeprom.
v2: RAS flags shall be restored after eeprom reset succeeds.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drive
When GPU executes recovery and retriving bad GPU tag
from external eerpom device, the recovery will be broken
and error message is printed as well for user's awareness.
v2: Refine warning message in threshold reaching case, and
fix spelling typo.
v3: Fix explicit calling of bad gpu.
v4: Rena
Bad page information should not be exposed by sysfs when
bad page retirement is disabled, so decouple it from ras
sysfs group creating, and add one guard before creating.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 71 -
1 file changed, 46 ins
This tag will be hired for bad gpu detection in eeprom's access.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
i
During driver's probe, when it hits bad gpu tag in eeprom i2c
init calling(the tag was set when reported bad page reaches
bad page threshold in last driver's working loop), there are
some strategys to deal with the cases:
1. when the module parameter amdgpu_bad_page_threshold = 0,
that means page
Once the ras recovery is issued from eeprom write itself,
bad page reservation should be ignored, otherwise, recursive
calling of writting to eeprom would happen.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 14
When amdgpu_bad_page_threshold = 0, bad page reservation stuffs
are skipped in either UMC ECC irq or page retirement calling of
sync flood isr.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 5 +++--
2 files changed, 6
Add one definition for the RAS module's FS name. It's used
in both debugfs and sysfs case.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/g
Am 28.07.20 um 09:49 schrieb Guchun Chen:
Add one definition for the RAS module's FS name. It's used
in both debugfs and sysfs case.
Maybe better do this with a "static const char*".
Christian.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 -
1
[AMD Public Use]
Thanks Christian. Your suggestion looks better, let me improve it.
Regards,
Guchun
-Original Message-
From: Koenig, Christian
Sent: Tuesday, July 28, 2020 3:55 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Zhang, Hawking ;
Li, Dennis ; Gro
what:
the MQD's save and restore of KCQ (kernel compute queue)
cost lots of clocks during world switch which impacts a lot
to multi-VF performance
how:
introduce a paramter to control the number of KCQ to avoid
performance drop if there is no kernel compute queue needed
notes:
this paramter only
The patch looks totally mangled to me, e.g. some spaces and new lines
are missing.
Probably because it was forwarded.
Christian.
Am 28.07.20 um 10:59 schrieb Liu, Monk:
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Monk Liu
Sent: Tuesday, July 28, 202
On Mon, Jul 27, 2020 at 10:49:48PM -0400, Kazlauskas, Nicholas wrote:
> On 2020-07-27 5:32 p.m., Daniel Vetter wrote:
> > On Mon, Jul 27, 2020 at 11:11 PM Mazin Rezk wrote:
> > >
> > > On Monday, July 27, 2020 4:29 PM, Daniel Vetter wrote:
> > >
> > > > On Mon, Jul 27, 2020 at 9:28 PM Christian
[AMD Official Use Only - Internal Distribution Only]
I repeated the patch broadcast through git-send-email
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: Koenig, Christian
Sent: Tuesday, July 28, 2020 5:04 PM
To: Liu, Monk ; amd-...
[AMD Official Use Only - Internal Distribution Only]
Hi, Guchun,
Please see my below comments.
Best Regards
Dennis Li
-Original Message-
From: Chen, Guchun
Sent: Tuesday, July 28, 2020 3:49 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Li, Dennis
;
Define ring structure to access the cpu/gpu address of rptr/wptr/fence
instead of dynamic calculation.
Cc: Christian König
Suggested-by: Christian König
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 ++
1 fi
Use ring structure to access the cpu/gpu address of rptr/wptr.
v2: merge gfx10/sdma5/sdma5.2 patches
Signed-off-by: Jack Xiao
Reviewed-by: Christian König
Reviewed-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 37 +++
assign the cpu/gpu address of fence for the normal or mes ring
from ring structure.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/dr
Initialize the cpu/gpu address of rptr/wptr/fence.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 37
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_rin
[AMD Public Use]
Series is Reviewed-by: Le Ma
Regards,
Ma Le
-Original Message-
From: Xiao, Jack
Sent: Tuesday, July 28, 2020 6:22 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Zhang, Hawking ; Koenig,
Christian ; Ma, Le
Cc: Xiao, Jack ; Koenig, Christian
Subject: [PA
Am 28.07.20 um 12:21 schrieb Jack Xiao:
Initialize the cpu/gpu address of rptr/wptr/fence.
Signed-off-by: Jack Xiao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 37
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rin
Am 28.07.20 um 12:21 schrieb Jack Xiao:
assign the cpu/gpu address of fence for the normal or mes ring
from ring structure.
Signed-off-by: Jack Xiao
Reviewed-by: Hawking Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 4 ++--
1 file changed, 2 insertions(+),
It's in accordance with pmfw 65.5.0 for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: I984a1147030264adbc02230e2e1dd416d4ad63b0
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11
On Monday, July 27, 2020 5:32 PM, Daniel Vetter wrote:
> On Mon, Jul 27, 2020 at 11:11 PM Mazin Rezk wrote:
> >
> > On Monday, July 27, 2020 4:29 PM, Daniel Vetter wrote:
> >
> > > On Mon, Jul 27, 2020 at 9:28 PM Christian König
> > > wrote:
> > > >
> > > > Am 27.07.20 um 16:05 schrieb Kazlaus
On Monday, July 27, 2020 4:29 PM, Daniel Vetter wrote:
> On Mon, Jul 27, 2020 at 9:28 PM Christian König
> wrote:
> >
> > Am 27.07.20 um 16:05 schrieb Kazlauskas, Nicholas:
> > > On 2020-07-27 9:39 a.m., Christian König wrote:
> > >> Am 27.07.20 um 07:40 schrieb Mazin Rezk:
> > >>> This patch fi
On Monday, July 27, 2020 7:42 PM, Mazin Rezk wrote:
> On Monday, July 27, 2020 5:32 PM, Daniel Vetter wrote:
>
> > On Mon, Jul 27, 2020 at 11:11 PM Mazin Rezk wrote:
> > >
> > > On Monday, July 27, 2020 4:29 PM, Daniel Vetter wrote:
> > >
> > > > On Mon, Jul 27, 2020 at 9:28 PM Christian König
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kenneth Feng
在 2020/7/28 下午7:21，“Jiansong Chen” 写入:
It's in accordance with pmfw 65.5.0 for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: I984a1147030264adbc02230e2e1dd416d4ad63b0
---
drivers/gpu
[AMD Public Use]
Hi Dennis,
Please check my response after yours.
Regards,
Guchun
-Original Message-
From: Li, Dennis
Sent: Tuesday, July 28, 2020 5:43 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Deucher,
Alexander ; Zhang, Hawking ;
Grodzovsky, Andrey ; Zhou1, Tao ;
Cleme
[AMD Public Use]
Would it be better to put this code into amdgpu_gfx_off_ctrl()? Then we'll
handle this in all cases where we disable gfx off.
Alex
From: Tianci Yin
Sent: Tuesday, July 28, 2020 3:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Deu
Am 2020-07-28 um 5:00 a.m. schrieb Monk Liu:
> what:
> the MQD's save and restore of KCQ (kernel compute queue)
> cost lots of clocks during world switch which impacts a lot
> to multi-VF performance
>
> how:
> introduce a paramter to control the number of KCQ to avoid
> performance drop if there i
Dear Linux folks,
Am 25.07.20 um 07:20 schrieb Mazin Rezk:
On Saturday, July 25, 2020 12:59 AM, Duncan wrote:
On Sat, 25 Jul 2020 03:03:52 + Mazin Rezk wrote:
Am 24.07.20 um 19:33 schrieb Kees Cook:
There was a fix to disable the async path for this driver that
worked around the bug t
Use the same case as sienna_cichlid
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index d488d250805d..e16874f30d5d
On Tue, Jul 28, 2020 at 11:43 AM Bhawanpreet Lakha
wrote:
>
> Use the same case as sienna_cichlid
>
> Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gp
On 2020-07-28 5:22 a.m., Paul Menzel wrote:
Dear Linux folks,
Am 25.07.20 um 07:20 schrieb Mazin Rezk:
On Saturday, July 25, 2020 12:59 AM, Duncan wrote:
On Sat, 25 Jul 2020 03:03:52 + Mazin Rezk wrote:
Am 24.07.20 um 19:33 schrieb Kees Cook:
There was a fix to disable the async path
Thanks for removing the braces.
On 2020-07-27 10:29 p.m., Liu ChengZhe wrote:
> the block->status.hw = false assignment will overwrite PSP's previous
^^
You want to start a sentence here. Capitalize "The".
Also don't use future tense in commit descriptions (and commit titles).
Simply use prese
Thanks for this patch.
On 2020-07-28 1:12 a.m., Liu ChengZhe wrote:
> From: root
You should fix your Git setup to show proper user name,
not "root". I've prepared a Confluence page which shows
a way to do it, and a few other things along the way:
http://confluence.amd.com/display/~ltuikov/Git+S
On 2020-07-28 1:36 a.m., Liu ChengZhe wrote:
> 1. For Navi12, CHIP_SIENNA_CICHLID, skip tmr load operation;
> 2. Check pointer before release firmware.
>
> v2: use CHIP_SIENNA_CICHLID instead
> v3: remove local "bool ret"; fix grammer issue
> v4: use my name instead of "root"
>
VMAs with a pg_offs that's offset from the start of the vma_node need
to adjust the offset within the BO accordingly. This matches the
offset calculation in ttm_bo_vm_fault_reserved.
Signed-off-by: Felix Kuehling
Tested-by: Laurent Morichetti
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 4 +++-
1 file
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
Use present tense:... " are lost after "
> reconfiguration is needed. Make the configuration code as an interface for
Add "so a reconfigurati
On 2020-07-28 1:27 a.m., Tianci Yin wrote:
> From: "Tianci.Yin"
>
> On Navi1x, the SPM golden settings will be lost after GFXOFF enter/exit,
" are lost "
> reconfigure the golden settings after GFXOFF exit.
" so reconfigure ..."
>
> Change-Id: I9358ba9c65f241c36f8a35916170b19535148ee9
> Sign
On 2020-07-28 2:04 p.m., Luben Tuikov wrote:
> Thanks for removing the braces.
>
> On 2020-07-27 10:29 p.m., Liu ChengZhe wrote:
>> the block->status.hw = false assignment will overwrite PSP's previous
> ^^
> You want to start a sentence here. Capitalize "The".
> Also don't use future tense in
Compiler leaves a 4-byte hole near the end of `dev_info`, causing
amdgpu_info_ioctl() to copy uninitialized kernel stack memory to userspace
when `size` is greater than 356.
In 2015 we tried to fix this issue by doing `= {};` on `dev_info`, which
unfortunately does not initialize that 4-byte hole.
On 7/28/20 1:50 AM, Christian König wrote:
Am 27.07.20 um 22:53 schrieb Daniel Dadap:
Fall back to retrieving the EDID via the ACPI _DDC method, when present
for notebook internal panels, when retrieving BIOS-embedded EDIDs.
Signed-off-by: Daniel Dadap
---
drivers/gpu/drm/radeon/radeon_comb
On Tue, Jul 28, 2020 at 01:07:13PM -0400, Kazlauskas, Nicholas wrote:
> On 2020-07-28 5:22 a.m., Paul Menzel wrote:
> > Dear Linux folks,
> >
> >
> > Am 25.07.20 um 07:20 schrieb Mazin Rezk:
> > > On Saturday, July 25, 2020 12:59 AM, Duncan wrote:
> > >
> > > > On Sat, 25 Jul 2020 03:03:52 +
This will allow us to split the allocation for systems
where we have to keep the stolen memory around to avoid
S3 issues. This way we don't waste as much memory and
still avoid any screen artifacts during the bios to
driver transition.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/
Should be functionally the same since nothing else is
allocated at that point, but let's be exact.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/driver
I suspect the only reason this was set was to avoid touching
the display related registers on arcturus. Someone should
double check this on arcturus with S3.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/dr
The new helper centralizes the logic in one place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 28ddb41a78c8..95
This adds a new gmc callback to get the size reserved by the pre-OS
console and provides a helper function for use by gmc IP drivers.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 43 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +++
2 files
The new helper centralizes the logic in one place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 8e3763ec268f.
Rather than leaving this as a gmc v9 specific hack.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 -
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 +++
3 files changed, 12 insertions(+), 9 deletions(-)
Split the allocations into two so we can still support the S3
workarounds required on some platforms while also avoiding
any artifacts when transitioning from bios to driver.
In the future we could integrate handling of the ip discovery
data and other vbios allocations into this helper function
to
The new helper centralizes the logic in one place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 57 +++---
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_
The new helper centralizes the logic in one place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 112 +-
1 file changed, 38 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.
Just return early to match other bo_create functions.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ac7b5561475..1
We never use them.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ec975251b171..3df9d5a53741 100
Since that is where we store the other data related to
the stolen vga memory.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
Rather than open coding it everywhere.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
The new helper centralizes the logic in one place.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 8b8ecbb99d84.
Am 2020-07-28 um 6:46 p.m. schrieb Alex Deucher:
> I suspect the only reason this was set was to avoid touching
> the display related registers on arcturus. Someone should
> double check this on arcturus with S3.
Sounds reasonable, given that the other offenders here are all APUs.
AFAIK, we haven
Am 2020-07-28 um 6:45 p.m. schrieb Alex Deucher:
> Just return early to match other bo_create functions.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Jiansong Chen
> Sent: Tuesday, July 28, 2020 7:21 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Feng, Kenneth
> ; Chen, Jiansong (Simon)
> Subject: [PATCH] drm/amd/powerp
[AMD Public Use]
Hi Alex,
amdgpu_gfx_off_ctrl() invoked by a few other functions, like
amdgpu_info_ioctl() ,
putting the code into amdgpu_gfx_off_ctrl() will cost more meaningless time on
SPM golden reconfiguration.
amdgpu_gfx_off_ctrl(adev, false);
amdgpu_asic_read_register(adev, se_num, sh_nu
[AMD Official Use Only - Internal Distribution Only]
Thanks very much Luben!
Regards,
Rico
From: Tuikov, Luben
Sent: Wednesday, July 29, 2020 2:29
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Hawking
; Xu, Feifei ; Hes
[AMD Official Use Only - Internal Distribution Only]
Thanks very much Lunben and Guchun!
Regards,
Rico
From: Tuikov, Luben
Sent: Wednesday, July 29, 2020 2:44
To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhang, Hawking
; Xu,
Once the ras recovery is issued from eeprom write itself,
bad page reservation should be ignored, otherwise, recursive
calling of writting to eeprom would happen.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 14
This tag will be hired for bad gpu detection in eeprom's access.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
i
The series is to enable/disable bad page feature and apply different
bad page reservation strategy by different bad page threshold
configurations.
When the saved bad pages written to eeprom reach the threshold,
one ras recovery will be issued immediately and the recovery will
fail to tell user tha
bad_page_threshold could be configured to enable/disable the
associated bad page retirement feature in RAS.
When it's -1, ras will use typical bad page failure value to
handle bad page retirement.
When it's 0, disable bad page retirement, and no bad page
will be recorded and saved.
For other val
When GPU executes recovery and retriving bad GPU tag
from external eerpom device, the recovery will be broken
and error message is printed as well for user's awareness.
v2: Refine warning message in threshold reaching case, and
fix spelling typo.
v3: Fix explicit calling of bad gpu.
v4: Rena
Bad page threshold value should be valid in the range between
-1 and max records length of eeprom. It could determine when
saved bad pages exceed threshold value, and proceed corresponding
actions.
v2: When using the default typical value, it should be min
value between typical value and eeprom ma
Once the bad page saved to eeprom reaches the configured
threshold, ras recovery will be issued to notify user.
v2: Fix spelling typo.
Signed-off-by: Guchun Chen
---
.../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 37 ++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --g
When retrieving bad gpu tag from eeprom, GPU init should
fail as the GPU needs to be retired for further check.
v2: Fix spelling typo, correct the condition to detect
bad gpu tag and refine error message.
v3: Refine function argument name.
v4: Fix missing check of returning value of i2c
Add one definition for the RAS module's FS name. It's used
in both debugfs and sysfs cases.
v2: Use static variable instead of macro definition.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git
During driver's probe, when it hits bad gpu tag in eeprom i2c
init calling(the tag was set when reported bad page reaches
bad page threshold in last driver's working loop), there are
some strategys to deal with the cases:
1. when the module parameter amdgpu_bad_page_threshold = 0,
that means page
RAS flags needs to be cleaned as well when user requires
one clean eeprom.
v2: RAS flags shall be restored after eeprom reset succeeds.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drive
Bad page information should not be exposed by sysfs when
bad page retirement is disabled, so decouple it from ras
sysfs group creating, and add one guard before creating.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 71 -
1 file changed, 46 ins
When amdgpu_bad_page_threshold = 0, bad page reservation stuffs
are skipped in either UMC ECC irq or page retirement calling of
sync flood isr.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 5 +++--
2 files changed, 6
Update GC golden setting for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: Ia7e82616b0be48f397c73b015823ac10ef907f08
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/d
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou
> -Original Message-
> From: Jiansong Chen
> Sent: Wednesday, July 29, 2020 12:02 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao ; Chen, Jiansong (Simon)
>
> Subject: [PATCH] drm/amdgpu: update GC golde
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