[AMD Official Use Only - Internal Distribution Only]
Then why we don't handle it directly in smu_cmn_send_smc_msg_with_param where
is more near to the source of the problem.
And there is similar logic already.
if (index < 0)
return index == -EACCES ? 0 : index;
Regards,
Jiansong
-Original Me
It's in accordance with pmfw 65.3.0 for navy_flounder.
Signed-off-by: Jiansong Chen
Change-Id: I97b0a28e280c3ac5c63f9c17a47c08b2c9b7d65e
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel) wrote:
> Hi,
>
> On 7/9/20 2:33 PM, Daniel Vetter wrote:
> > Comes up every few years, gets somewhat tedious to discuss, let's
> > write this down once and for all.
> >
> > What I'm not sure about is whether the text should be mor
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel) wrote:
Hi,
On 7/9/20 2:33 PM, Daniel Vetter wrote:
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once and for all.
What I'm not sure about is whet
Not sure whether there have any case that need to deal with that situation if
some msg not found except the set mp1 state message. If handle it in
smu_cmn_send_smc_msg_with_param all the message not found will be skipped.
And the logic return index == -EACCES ? 0 : index; only skipped the bad ret
[AMD Official Use Only - Internal Distribution Only]
Commit : 81a5f33903a30574 has already contains this change, not sure why it
disappear in current branch.
And does it make sense to set valid_in_vf to be true? Mode1 reset shouldn't be
supported in vf mode I think.
Brs
Wenhui
-Original
From: Likun Gao
Set valid_in_vf to false for the message not support in vf mode on
sienna cichlid.
Signed-off-by: Likun Gao
Change-Id: Ib07fe7522eea39a14131945bb76be0b0935598ae
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 70 +--
1 file changed, 35 insertions(+), 35 dele
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
wrote:
Hi,
On 7/9/20 2:33 PM, Daniel Vetter wrote:
Comes up every few years, gets somewhat tedious to discuss, let's
write this down once
Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
wrote:
Hi,
On 7/9/20 2:33 PM, Daniel Vetter wrote:
Comes up every few years, gets
To accommodate VCN instances variance, otherwise it may trigger
smu response error for configuration with less instances.
Signed-off-by: Jiansong Chen
Change-Id: I0bfe31f1f5638d539ac6ded3bffee8f57574bafa
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 68 +++
1 file changed,
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Tao Zhou
-Original Message-
From: Jiansong Chen
Sent: Tuesday, July 21, 2020 3:39 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Chen,
Jiansong (Simon)
Subject: [PATCH] drm/amd/powerplay: update d
On Tue, Jul 21, 2020 at 10:55 AM Christian König
wrote:
>
> Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
> >
> > On 7/21/20 9:45 AM, Christian König wrote:
> >> Am 21.07.20 um 09:41 schrieb Daniel Vetter:
> >>> On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
> >>> wrot
[AMD Official Use Only - Internal Distribution Only]
With my comment below fixed, the patch is:
Reviewed-by: Tao Zhou
-Original Message-
From: Jiansong Chen
Sent: Tuesday, July 21, 2020 5:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Chen,
Jiansong (Simon)
On Tue, Jul 21, 2020 at 11:16 AM Daniel Vetter wrote:
>
> On Tue, Jul 21, 2020 at 10:55 AM Christian König
> wrote:
> >
> > Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
> > >
> > > On 7/21/20 9:45 AM, Christian König wrote:
> > >> Am 21.07.20 um 09:41 schrieb Daniel Vetter:
> > >>> On M
On 7/21/20 10:55 AM, Christian König wrote:
Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
wrote:
Hi,
On 7/9/20 2:33 PM, Daniel
On Tue, Jul 21, 2020 at 11:38 AM Thomas Hellström (Intel)
wrote:
>
>
> On 7/21/20 10:55 AM, Christian König wrote:
> > Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
> >>
> >> On 7/21/20 9:45 AM, Christian König wrote:
> >>> Am 21.07.20 um 09:41 schrieb Daniel Vetter:
> On Mon, Jul 20
Reviewed-by: Likun Gao
Regards,
Likun
-邮件原件-
发件人: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] 代表 Jiansong Chen
发送时间: 2020年7月21日 17:01
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou1, Tao ; Feng, Kenneth ; Chen,
Jiansong (Simon)
主题: [PATCH] drm/amd/powerplay: retrieve VCN dpm ta
[AMD Public Use]
Added support for dedicated 64bit read/write reg support for sienna chichlid
0001-drm-amdgpu-expand-sienna-chichlid-reg-access-support.patch
Description: 0001-drm-amdgpu-expand-sienna-chichlid-reg-access-support.patch
___
amd-gfx maili
[AMD Public Use]
Submitting patch to enable RAS EEPROM support for sienna chichlid
0001-drm-amdgpu-add-RAS-EEPROM-support-for-sienna-chichli.patch
Description: 0001-drm-amdgpu-add-RAS-EEPROM-support-for-sienna-chichli.patch
___
amd-gfx mailing list
amd
GMC v10 includes gc and mmhub header files. It's not good to support multiple
versions of gfxhub and mmhub. Because it may bring up the register mismatches.
So this cleanup is to remove gc and mmhub headers in gmc_v10.c and introduce
vmhub funcs helper to move all programming and accessing to the
This patch is to move get_invalidate_req into gfxhub/mmhub level. It will avoid
mismatch of the different gfxhub/mmhub register offsets and fields in the same
gmc block.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 21 ++
This patch adds a member in vmhub structure to store the vm fault interrupt
masks for different version gfxhubs/mmhubs.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 ++
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 8
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c |
This patch is to introduce vmhub funcs helper to add following callback
(print_l2_protection_fault_status). Each GC/MMHUB register specific programming
should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 7 +++
drivers/gpu/drm/amd/amdgpu/
This patch is to add set_vm_fault_masks helper to amdgpu_gmc to refine the
original programming.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 20 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 +++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 53 +++
All gc/mmhub register access and operation should be in gfxhub/mmhub level.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index a1798ec2..19
On 7/21/20 11:50 AM, Daniel Vetter wrote:
On Tue, Jul 21, 2020 at 11:38 AM Thomas Hellström (Intel)
wrote:
On 7/21/20 10:55 AM, Christian König wrote:
Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vette
Hi Andrey,
Am Mittwoch, den 12.02.2020, 11:33 -0500 schrieb Andrey Grodzovsky:
> On 2/11/20 7:53 PM, Luben Tuikov wrote:
> > On 2020-02-11 4:27 p.m., Andrey Grodzovsky wrote:
> > > On 2/11/20 10:55 AM, Andrey Grodzovsky wrote:
> > > > On 2/10/20 4:50 PM, Luben Tuikov wrote:
> > > > > Hi Lucas,
> >
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Clements, John
Sent: Tuesday, July 21, 2020 17:54
To: amd-gfx list ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: expand sienna chichlid reg access support
[AMD Public Use]
Added support for dedicated 64bit read/write reg su
[AMD Public Use]
- if (adev->asic_type != CHIP_VEGA20 && adev->asic_type !=
CHIP_ARCTURUS)
+ if (adev->asic_type != CHIP_VEGA20 &&
+ adev->asic_type != CHIP_ARCTURUS &&
+ adev->asic_type != CHIP_SIENNA_CICHLID)
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Tuesday, July 21, 2020 16:43
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Sheng, Wenhui
; Quan, Evan ; Gao, Likun
Subject: [PATCH] drm/amd/powerplay: correct smu message
Lucas, Luben picked the work on this a few month ago as I was diverted to a
different project.
Luben, can you update Lucas please ?
Andrey
On 7/21/20 7:03 AM, Lucas Stach wrote:
It seems we all dropped the ball on this one. I believe this is still
an open issue. Has there been any progress fr
Luben had a good idea how to tackle the whole job handling.
Andrey/Lucas can you work with Luben to get this cleaned up because
there are a lot of requirements on this which not only come from AMD.
Thanks,
Christian.
Am 21.07.20 um 15:36 schrieb Andrey Grodzovsky:
Lucas, Luben picked the work
Christian, I would want this very much but unfortunately I am on a strict
schedule for an internal project currently and hence will not be able to
actively participate. I will do my best to answer any questions Luben might have
about current implementation.
Andrey
On 7/21/20 9:39 AM, Christia
Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
On 7/21/20 11:50 AM, Daniel Vetter wrote:
On Tue, Jul 21, 2020 at 11:38 AM Thomas Hellström (Intel)
wrote:
On 7/21/20 10:55 AM, Christian König wrote:
Am 21.07.20 um 10:47 schrieb Thomas Hellström (Intel):
On 7/21/20 9:45 AM, Christian
Dear Kees, dear Andrew,
No idea, if you are aware of it yet, but three people verified that
commit 3202fa62fb (slub: relocate freelist pointer to middle of object)
causes a regression on AMD hardware [1].
It’d be great, if you took a look, and advised if this commit (and
follow-ups) should
In certain kernels using GCC 8.2, we get compilation errors saying:
-mpreferred-stack-boundary=3 is not between 4 and 12
Explicitly set -mpreferred-stack-boundary=4 in the Display Makefiles,
even when SSE2 is enabled
Change-Id: Ic7c4637e2e521af2d0444d3b5886f710131c80ca
Signed-off-by: Kent Russell
On 2020-07-21 11:38 a.m., Kent Russell wrote:
In certain kernels using GCC 8.2, we get compilation errors saying:
-mpreferred-stack-boundary=3 is not between 4 and 12
Explicitly set -mpreferred-stack-boundary=4 in the Display Makefiles,
even when SSE2 is enabled
Change-Id: Ic7c4637e2e521af2d0444
Am 2020-07-21 um 11:38 a.m. schrieb Kent Russell:
> In certain kernels using GCC 8.2, we get compilation errors saying:
> -mpreferred-stack-boundary=3 is not between 4 and 12
> Explicitly set -mpreferred-stack-boundary=4 in the Display Makefiles,
> even when SSE2 is enabled
As I understand it, -mp
On 2020-07-21 12:03 p.m., Felix Kuehling wrote:
Am 2020-07-21 um 11:38 a.m. schrieb Kent Russell:
In certain kernels using GCC 8.2, we get compilation errors saying:
-mpreferred-stack-boundary=3 is not between 4 and 12
Explicitly set -mpreferred-stack-boundary=4 in the Display Makefiles,
even wh
On Mon, Jul 20, 2020 at 4:22 AM Harvey wrote:
>
> Hello,
>
> this is my first post to this list so please be patient with me ;)
>
> The facts:
>
> it is now one week that I own a new laptop, a MSI Bravo 17 A4DDR/MS-17FK
> with Ryzen 7 4800U and hybrid graphics on a Radeon RX 5500M. I installed
> m
We expose the actual memory controller clock rate in Linux,
not the effective memory clock of the DRAMs. To translate
it, it follows the following formula:
Clock conversion (Mhz):
HBM: effective_memory_clock = memory_controller_clock * 1
G5: effective_memory_clock = memory_controller_clock * 1
G
The driver uses it for EEPROM access, but it's just an i2c bus.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 60 ++--
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
b/drivers/gpu/drm/
The driver uses it for EEPROM access, but it's just an i2c bus.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 52 +--
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h| 4 +-
.../drm/amd/powerplay/smumgr/vega20_smumgr.c | 4 +-
3 files changed, 3
Enable SMU i2c bus access for sienna_cichlid asics.
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 239 ++
1 file changed, 239 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/powerplay/sienna_c
There is no longer a ras dependency so it's safe to expose
on all boards.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
b/d
Enable SMU i2c bus access for navi1x asics.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index ead135f39c7e..56267e6c600e
It's not really ras related. It's just a lock for the
bus in general. This removes the ras dependency from
the smu i2c bus.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 1 -
drivers/gpu/drm/amd/amdgpu/s
[AMD Official Use Only - Internal Distribution Only]
Ignore this. Sent out the wrong version.
Alex
From: Alex Deucher
Sent: Tuesday, July 21, 2020 12:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 5/6] drm/amdgpu/navi1x: add SMU
Looks like same code as arcturus - should we make it common helper code and
reuse in both ?
Andrey
On 7/21/20 12:52 PM, Alex Deucher wrote:
Enable SMU i2c bus access for sienna_cichlid asics.
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 239 ++
[AMD Official Use Only - Internal Distribution Only]
I tried that at first, but the smu i2c interface structures are different per
asic.
Alex
From: Grodzovsky, Andrey
Sent: Tuesday, July 21, 2020 1:01 PM
To: Alex Deucher ; amd-gfx@lists.freedesktop.org
Cc: De
Applied. Thanks!
Alex
On Fri, Jul 17, 2020 at 8:23 AM Qiu Wenbo wrote:
>
> Avoid kernel crash when vddci_control is SMU7_VOLTAGE_CONTROL_NONE and
> vddci_voltage_table is empty. It has been tested on Intel Hades Canyon
> (i7-8809G).
>
> Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208489
>
Applied. Thanks!
Alex
On Sun, Jul 19, 2020 at 12:22 PM Paweł Gronowski wrote:
>
> NULL dereference occurs when string that is not ended with space or
> newline is written to some dpm sysfs interface (for example pp_dpm_sclk).
> This happens because strsep replaces the tmp with NULL if the delim
declarations after statements. Trivial.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f16909989c0d..350f1bf06
On 2020-07-21 15:59, Christian König wrote:
Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
...
Yes, we can't do magic. As soon as an indefinite batch makes it to
such hardware we've lost. But since we can break out while the batch
is stuck in the scheduler waiting, what I believe we *
Reviewed-by: Andrey Grodzovsky
Andrey
On 7/21/20 1:22 PM, Alex Deucher wrote:
declarations after statements. Trivial.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
Series besides patch 5/6 which you said is the wrong version is Reviewed-by:
Andrey Grodzovsky
Andrey
On 7/21/20 12:52 PM, Alex Deucher wrote:
Enable SMU i2c bus access for sienna_cichlid asics.
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 239 ++
[Why]
Currently navy_flounder is using sienna_cichlid_dmcub.bin.
[How]
Create a seperate define so navy_flounder will use its own firmware.
Signed-off-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --
The driver uses it for EEPROM access, but it's just an i2c bus.
Reviewed-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c| 52 +--
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h| 4 +-
.../drm/amd/powerplay/smumgr/vega20_smumg
The driver uses it for EEPROM access, but it's just an i2c bus.
v2: change the callback name as well.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 4 +-
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 60 +--
.../gpu/drm/amd/powerplay/inc/amdg
It's not really ras related. It's just a lock for the
bus in general. This removes the ras dependency from
the smu i2c bus.
Reviewed-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 1
Enable SMU i2c bus access for sienna_cichlid asics.
v2: change callback name
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 239 ++
1 file changed, 239 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
b/drivers/gpu/
Enable SMU i2c bus access for navi1x asics.
v2: add missing implementation
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 239 +
1 file changed, 239 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/po
There is no longer a ras dependency so it's safe to expose
on all boards.
Reviewed-by: Andrey Grodzovsky
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/power
On Tue, Jul 21, 2020 at 2:07 PM Bhawanpreet Lakha
wrote:
>
> [Why]
> Currently navy_flounder is using sienna_cichlid_dmcub.bin.
>
> [How]
> Create a seperate define so navy_flounder will use its own firmware.
>
> Signed-off-by: Bhawanpreet Lakha
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/d
Series is Reviewed-by: Andrey Grodzovsky
Andrey
On 7/21/20 2:08 PM, Alex Deucher wrote:
Enable SMU i2c bus access for sienna_cichlid asics.
v2: change callback name
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c| 239 ++
1 file changed, 239
On Tue, Jul 21, 2020 at 7:46 PM Thomas Hellström (Intel)
wrote:
>
>
> On 2020-07-21 15:59, Christian König wrote:
> > Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
> ...
> >> Yes, we can't do magic. As soon as an indefinite batch makes it to
> >> such hardware we've lost. But since we can
Alex,
tnak you so much - you're my hero!
Am 21.07.20 um 18:17 schrieb Alex Deucher:
On Mon, Jul 20, 2020 at 4:22 AM Harvey wrote:
Hello,
this is my first post to this list so please be patient with me ;)
The facts:
it is now one week that I own a new laptop, a MSI Bravo 17 A4DDR/MS-17FK
w
Hi Lucas,
Thank you for following up on this. Some things have slowed down,
given the world pandemic we've been experiencing this year.
I've had the design ready and half of it implemented and committed
into a branch. Just as per what I wrote earlier this year on this thread.
I need to finish th
On Tue, Jul 21, 2020 at 04:55:12PM +0200, Paul Menzel wrote:
> No idea, if you are aware of it yet, but three people verified that commit
> 3202fa62fb (slub: relocate freelist pointer to middle of object) causes a
> regression on AMD hardware [1].
Hi, thanks for emailing; I don't get bugzilla noti
Add support for reporting thermal throttling events through SMI.
Also, add a counter to count the number of throttling interrupts
observed and report the count in the SMI event message.
Signed-off-by: Mukul Joshi
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 4 ++
drivers/gpu/drm/amd/amdg
On Tue, Jul 21, 2020 at 5:19 PM Pierre-Loup A. Griffais
wrote:
>
> It's otherwise properly supported, just needs exposing to userspace.
>
> Signed-off-by: Pierre-Loup A. Griffais
Already applied:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-5.9&id=ecc874a6e7cb398b363b4e078fca4c09
>
> >> That's also why I'm not positive on the "no hw preemption, only
> >> scheduler" case: You still have a dma_fence for the batch itself,
> >> which means still no userspace controlled synchronization or other
> >> form of indefinite batches allowed. So not getting us any closer to
> >> enablin
Am 2020-07-21 um 5:01 p.m. schrieb Mukul Joshi:
> Add support for reporting thermal throttling events through SMI.
> Also, add a counter to count the number of throttling interrupts
> observed and report the count in the SMI event message.
>
> Signed-off-by: Mukul Joshi
> ---
> drivers/gpu/drm/a
On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
wrote:
>
>
> On 7/21/20 9:45 AM, Christian König wrote:
> > Am 21.07.20 um 09:41 schrieb Daniel Vetter:
> >> On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
> >> wrote:
> >>> Hi,
> >>>
> >>> On 7/9/20 2:33 PM, Daniel Vetter
On Fri, Jun 26, 2020 at 7:11 PM Manasi Navare wrote:
>
> From: Bhanuprakash Modem
>
> v3:
> * Rebase (Manasi)
> v2:
> * Rebase (Manasi)
>
> As both VRR min and max are already part of drm_display_info,
> drm can expose this VRR range for each connector.
>
> Hence this logic should move to core DR
Series is:
Reviewed-by: Alex Deucher
On Tue, Jul 21, 2020 at 6:29 AM Huang Rui wrote:
>
> All gc/mmhub register access and operation should be in gfxhub/mmhub level.
>
> Signed-off-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --
It's otherwise properly supported, just needs exposing to userspace.
Signed-off-by: Pierre-Loup A. Griffais
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/d
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c: In function vcn_v3_0_start_sriov:
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:1235:3:
warning: variable direct_poll set but not used [-Wunused-but-set-variable]
It is never used, so can remove it.
Signed-off-by: YueHaibing
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_
On Mon, Jul 20, 2020 at 6:00 AM Mauro Rossi wrote:
>
> Hi Christian,
>
> On Mon, Jul 20, 2020 at 11:00 AM Christian König
> wrote:
> >
> > Hi Mauro,
> >
> > I'm not deep into the whole DC design, so just some general high level
> > comments on the cover letter:
> >
> > 1. Please add a subject lin
bad_page_threshold could be specified to detect and retire
bad GPU if faulty bad pages exceed it.
When it's -1, ras will use typical bad page failure value.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 11 +++
2
Ras flags needs to be cleaned as well when user requires
one clean eeprom.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 818d415
Bad page threshold value should be valid in the range between
-1 and max records length of eeprom. It could determine when
the GPU should be retired.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 43 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
The series is to enable the feature of GPU RMA(Return Merchandise
Authorization) which is trigged when bad pages detected by RAS ECC
exceed the threshold value.
When the saved bad pages written to eeprom reach the threshold,
one ras recovery will be issued immediately and the recovery will
fail to
Use sizeof to get actual size.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 96b63c026b
During boot up, when init eeprom, RAS will check if the BAD
GPU tag is saved or not. And will break boot up and notify user
to RMA it.
At the meanwhile, when saved bad page count to eeprom exceeds
threshold, one ras recovery will be triggered immediately, and
bad gpu check will be executed and res
On 2020-07-22 00:45, Dave Airlie wrote:
On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel)
wrote:
On 7/21/20 9:45 AM, Christian König wrote:
Am 21.07.20 um 09:41 schrieb Daniel Vetter:
On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel)
wrote:
Hi,
On 7/9/20 2:33 PM, Dan
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