Re: [PATCH] drm/amdgpu: return an error for hw access in INFO ioctl when in reset

Am 03.07.20 um 08:05 schrieb Felix Kuehling: Am 2020-07-01 um 10:34 a.m. schrieb Li, Dennis: [AMD Official Use Only - Internal Distribution Only] Hi, Christian and Alex Not only amdgpu ioctls, but amdkfd ioctls also have the same issue. Most KFD ioctls don't access HW directly. The only

Re: [PATCH v5 01/12] iommu: Change type of pasid to u32

Hi, Felix, Thomas, Joerg and maintainers, On Tue, Jun 30, 2020 at 10:12:38PM -0400, Felix Kuehling wrote: > Am 2020-06-30 um 7:44 p.m. schrieb Fenghua Yu: > You didn't change the return types of amdgpu_pasid_alloc and > kfd_pasid_alloc. amdgpu_pasid_alloc returns int, because it can return > negat

Re: [PATCH 1/2] moduleparams: Add hex type parameter

On Thu, Jul 2, 2020 at 7:42 AM Christian König wrote: > > I'm just not sure how well this is received upstream because it only > covers u32 > > On the other hand that is probably also the most used. Not necessarily true. I'd argue that "unsigned long" is equally possible for some bit mask (or ot

[PATCH 05/14] drm/amd/powerplay: add new UMD pstate data structure

This is used to cache the clock frequencies for all UMD pstates. So that we do not need to calculate from scratch on every UMD pstate switch. Change-Id: I3f2ef5ee2e6e433518f726988bbe5970848b99c8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 15 +++ 1 f

[PATCH 02/14] drm/amd/powerplay: update Arcturus default dpm table setting

Preparing for coming code sharing around performance level setting. Change-Id: Ie32b6af39f22d05c08096959bab0e02e53856170 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 +++--- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 + drivers/gpu/drm/amd

[PATCH 06/14] drm/amd/powerplay: update UMD pstate clock settings

Preparing for coming code sharing around performance level setting. Change-Id: I51b1536b62995f0fecd51b91f238793f57485aa9 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 6 +- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 47 ++--- drivers/gpu/drm/amd/powerplay

[PATCH 03/14] drm/amd/powerplay: update Navi10 default dpm table setup

Cache all clocks levels for every dpm table. They are needed by other APIs. Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 182 ++--- 1 file changed, 158 insertions(+), 24 deletions(-) diff --git a/d

[PATCH 07/14] drm/amd/powerplay: update the common API for performance level setting

So that it can be more widely shared around SMU v11 ASICs. Change-Id: Ie110edf2ec519699448d3ff3215188ba243d2415 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 91 +++ 1 file changed, 77 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH 12/14] drm/amd/powerplay: drop unnecessary wrappers

By calling the target APIs directly. Change-Id: I0f24f603d2fcb94d2078a35c405a1406093ba5e3 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.

[PATCH 11/14] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range

Use the common smu_v11_0_set_soft_freq_limited_range. Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 20 ++- drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 - drivers/gpu/drm/amd/powerplay/smu_

[PATCH 10/14] drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs

As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Change-Id: I04c810859794b07ce8905a8df797ed6b5ae116a8 Signed-off-by: Evan Quan --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 178 +- 1 file changed, 1 insertion(+), 177

[PATCH 01/14] drm/amd/powerplay: add more members for dpm table

These members can help to cache the clock frequencies for all dpm levels. Then simplifying the code for dpm level switching is possible. Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +-- 1 file ch

[PATCH 09/14] drm/amd/powerplay: drop unnecessary Navi1x specific APIs

As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Change-Id: I2c8831b9d00618c6578ee42b34e26892c5dba515 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 248 + 1 file changed, 1 insertion(+), 247

[PATCH 04/14] drm/amd/powerplay: update Sienna Cichlid default dpm table setup

Cache all clocks levels for every dpm table. They are needed by other APIs. Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd Signed-off-by: Evan Quan --- .../drm/amd/powerplay/sienna_cichlid_ppt.c| 234 -- 1 file changed, 211 insertions(+), 23 deletions(-) diff --git a/d

[PATCH 08/14] drm/amd/powerplay: drop unnecessary Arcturus specific APIs

As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Change-Id: Icd96ce42218d78d670dd0c1f88663fd42108b311 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 170 --- 1 file changed, 170 deletions(-) di

[PATCH 13/14] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper

By moving the implemention to renoir_ppt.c considering it's really ASIC specific. Change-Id: I6f7a594235dffdf75b56d1de5b9dc6d49833d7e8 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 - drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 172 ++ drive

[PATCH 14/14] drm/amd/powerplay: drop unused APIs and parameters

Leftover of previous performance level setting cleanups. Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++-- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++-- drivers/gpu/drm/amd/powerpla

[PATCH] drm/amd/powerplay: correct the .get_workload_type() pointer

This seemed a typo. Change-Id: I1e4da590829395617e90d0d43562f934a1ae0234 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu

[PATCH 1/2] drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting

This can also help to maintain clear code layer. Change-Id: I9bf6a7bb93112ae40bd549ee4d7afb42a968aacf Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 33 ++- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 - .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h

[PATCH 2/2] drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount

The LCLK dpm table setup should be performed in .update_pcie_parameters(). Otherwise, the updated GenSpeed and LaneCount information will be lost. Change-Id: I028c26ca0e54098cb93d9e9266719f1762ba2d7e Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 17 +++---

[PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving

This can help to maintain clear code layer. Change-Id: I9c95dd70273ab56c1ddb40592574ed283a34737f Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 33 +++ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 ++ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h

[PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings

These are needed for temp1/2/3 related hwmon interfaces. Change-Id: I4fe04dc65ba2153bbb9c507769a9d8ddeac66094 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 +- drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 drivers/gpu/drm/amd/powerplay/navi10_ppt.

[PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid temperature limit settings

These are needed for temp1/2/3 related hwmon interfaces. Change-Id: I76ec427aaae67a0dd257e2b1d7908990eb79a5b2 Signed-off-by: Evan Quan --- .../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/po

[PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp

As it's needed in the succeeding thermal irq setting. Change-Id: Iee34fb6515a88a684c7f1214e40edb7e65245f8d Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.

[PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting

Leftover of previous cleanups. Change-Id: I36a018349647125513e47edda66db2005bd8b0c5 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 32 --- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 -- drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 32 -

[PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting

Put the common code in smu_v11_0.c instead of having one copy each. Change-Id: I6d0c27c5810ebc3273ef8b4fae07ac6dbed2715c Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/am

Re: [PATCH v2 1/2] moduleparams: Add hexint type parameter

Am 03.07.20 um 15:49 schrieb Paul Menzel: For bitmasks printing values in hex is more convenient. Prefix with `0x` to make it clear, that it’s a hex value, and pad it out. Using the helper for `amdgpu.ppfeaturemask`, it will look like below. Before: $ more /sys/module/amdgpu/parameters/p

Re: [PATCH v3 3/3] drm/amdgpu: Change type of module param `ppfeaturemask` to hexint

Am 03.07.20 um 16:29 schrieb Paul Menzel: The newly added hexint helper is more convenient for bitmasks. Before: $ more /sys/module/amdgpu/parameters/ppfeaturemask 4294950911 After: $ more /sys/module/amdgpu/parameters/ppfeaturemask 0xbfff Cc: amd-gfx@lists.freedeskto

[PATCH 8/8] drm/amd/display: Add logger for SMU msg

From: Wesley Chalmers [WHY] We want to be able to see SMU messages sent and their responses Signed-off-by: Wesley Chalmers Reviewed-by: Joshua Aberback Acked-by: Eryk Brol Acked-by: Rodrigo Siqueira --- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 65 ++- .../drm/amd/disp

[PATCH 7/8] drm/amd/display: Request PHYCLK adjustment on PHY enable/disable

From: Joshua Aberback [Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - rem

[PATCH 1/8] drm/amd/display: Add diags scaling log by default

From: Dmytro Laktyushkin Print scaling parameters as they are calculated in diags. Signed-off-by: Dmytro Laktyushkin Reviewed-by: Eric Bernstein Acked-by: Eryk Brol Acked-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 39 --- .../drm/amd/display/inc

[PATCH 3/8] drm/amd/display: Send VSIF on unsupported modes on DAL

From: Jaehyun Chung [Why] Current DAL behaviour is to not send VSIF if mode does not support VRR (ie. FS range is < 10Hz). However, we should still set FS Native Color Active bit in some unsupported mode cases. [How] Remove check for if VRR is supported before building infopacket. Signed-off-by

[PATCH 6/8] drm/amd/display: 3.2.93

From: Anthony Koo Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Eryk Brol Acked-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/

[PATCH 5/8] drm/amd/display: [FW Promotion] Release 0.0.23

From: Anthony Koo [Header Changes] - Drop unused firmware SCRATCH bits from interface Signed-off-by: Anthony Koo Reviewed-by: Anthony Koo Acked-by: Eryk Brol Acked-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h| 18 ++ 1 file changed, 6 insertions(+

[PATCH 0/8] DC Patches July 03, 2020

This DC patchset brings improvements in multiple areas. In summary, we have: * SMU logger messages * DMCU improvements * Bug fixes Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.23 drm/amd/display: 3.2.93 Dmytro Laktyushkin (1): drm/amd/display: Add diags scaling log by defaul

[PATCH 2/8] drm/amd/display: Register init

From: Igor Kravchenko [Why] Driver re-initialize registers already set in FW [How] Transfer init to FW Signed-off-by: Igor Kravchenko Reviewed-by: Tony Cheng Acked-by: Eryk Brol Acked-by: Rodrigo Siqueira --- .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 58 +++ 1 file ch

[PATCH 4/8] drm/amd/display: Remove VSC infoframe dep on DMCU

From: Roman Li [Why] VSC infoframe is needed for PSR. Previously only DMCU controller supported PSR. Now DMUB also implements PSR. [How] Remove VSC infoframe dependency on DMCU. Signed-off-by: Roman Li Reviewed-by: Rodrigo Siqueira Acked-by: Eryk Brol --- .../gpu/drm/amd/display/amdgpu_dm/a