Add Felix and Shaoyun
-Original Message-
From: Yintian Tao
Sent: 2020年4月22日 12:42
To: Koenig, Christian ; Liu, Monk
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian
Subject: [PATCH] drm/amdgpu: refine kiq access register
According to the current kiq access register method, there will b
BUG_ON(in_interrupt());
That won't work like this. The KIQ is also used in interrupt context in
the driver, that's why we used spin_lock_irqsave().
And I would either say that we should use the trick with the NOP to
reserve space on the ring buffer or call amdgpu_device_wb_get() for each
read
Am 22.04.20 um 02:56 schrieb 赵军奎:
发件人："Christian König"
发送日期：2020-04-21 22:53:47
收件人："赵军奎"
抄送人：Alex Deucher ,"David (ChunMing) Zhou" ,David Airlie
,Daniel Vetter ,Tom St Denis ,Ori Messinger
,Sam Ravnborg
,amd-gfx@lists.freedesktop.org,dri-de...@lists.freedesktop.org,linux-ker...@vger.kernel
Hi Christian
> BUG_ON(in_interrupt());
That won't work like this. The KIQ is also used in interrupt context in the
driver, that's why we used spin_lock_irqsave().
[yttao]: According to the current drm-next code, I have not find where to
access register through KIQ.
And you need
Am 22.04.20 um 09:35 schrieb Tao, Yintian:
Hi Christian
BUG_ON(in_interrupt());
That won't work like this. The KIQ is also used in interrupt context in the
driver, that's why we used spin_lock_irqsave().
[yttao]: According to the current drm-next code, I have not find where to
access regis
Hi Christian
Please see inline comments.
-Original Message-
From: Christian König
Sent: 2020年4月22日 15:40
To: Tao, Yintian ; Koenig, Christian
; Liu, Monk ; Liu, Shaoyun
; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access register
Am
Am 22.04.20 um 09:49 schrieb Tao, Yintian:
Hi Christian
Please see inline comments.
-Original Message-
From: Christian König
Sent: 2020年4月22日 15:40
To: Tao, Yintian ; Koenig, Christian ; Liu, Monk
; Liu, Shaoyun ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH
Hi Christian
Please see inline comments
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 15:54
To: Tao, Yintian ; Liu, Monk ; Liu,
Shaoyun ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access register
Am 22.04.20 um 09:49
Am 22.04.20 um 10:06 schrieb Tao, Yintian:
Hi Christian
Please see inline comments
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 15:54
To: Tao, Yintian ; Liu, Monk ; Liu, Shaoyun
; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refin
Hi Christian
Please see inline comments.
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 16:23
To: Tao, Yintian ; Liu, Monk ; Liu,
Shaoyun ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access register
Am 22.04.20 um 10:06
According to the current kiq access register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 thro
Am 22.04.20 um 11:29 schrieb Yintian Tao:
According to the current kiq access register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the
Hi Christian
Can you help answer the questions below? Thanks in advance.
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 19:03
To: Tao, Yintian ; Liu, Monk ; Kuehling,
Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access register
Am
Am 22.04.20 um 13:49 schrieb Tao, Yintian:
Hi Christian
Can you help answer the questions below? Thanks in advance.
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 19:03
To: Tao, Yintian ; Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH]
Hi Christian
Please see inline commetns.
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 19:57
To: Tao, Yintian ; Liu, Monk ; Kuehling,
Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access register
Am 22.04.20 um 13:49 schrieb Tao, Y
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
Am 22.04.20 um 14:20 schrieb Tao, Yintian:
Hi Christian
Please see inline commetns.
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 19:57
To: Tao, Yintian ; Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: refine kiq access r
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
Hi Christian
Thanks, I got it. I will send another patch for the KIQ overrun problem
Best Regards
Yintian Tao
-Original Message-
From: Koenig, Christian
Sent: 2020年4月22日 20:33
To: Tao, Yintian ; Liu, Monk ; Kuehling,
Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/am
Am 22.04.20 um 14:36 schrieb Yintian Tao:
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the se
On Wed, Apr 22, 2020 at 08:03:29AM +0200, Christoph Hellwig wrote:
>
>
> On Tue, Apr 21, 2020 at 09:21:46PM -0300, Jason Gunthorpe wrote:
> > +void nouveau_hmm_convert_pfn(struct nouveau_drm *drm, struct hmm_range
> > *range,
> > +u64 *ioctl_addr)
> > {
> > unsigned
For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
the amdgpu will expose pp_num_states to the /sys directory.
In this moment, read the pp_num_states file will excute the
amdgpu_get_pp_num_states func. In our case, the data hasn't
been initialized, so the kernel will access some ilegal
On Tue, Apr 21, 2020 at 10:42 PM Evan Quan wrote:
>
> At default, the autosuspend delay of audio controller is 3S. If the
> gpu reset is triggered within 3S(after audio controller idle),
> the audio controller may be unable into suspended state. Then
> the sudden gpu reset will cause some audio er
On 2020-04-21 7:34 p.m., Randy Dunlap wrote:
> From: Randy Dunlap
>
> Fix help text: indent one tab + 2 spaces; end a sentence with a
> period; and collapse short lines of text to one line.
>
> Fixes: 23c61b4599c4 ("drm/amd: Fix Kconfig indentation")
> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc di
Wait for the oldest to be signaled to make sure
there will be no kiq overrun.
Signed-off-by: Yintian Tao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 8 -
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 8 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 30 +++
[AMD Official Use Only - Internal Distribution Only]
Hi ,Yintian & Christian
I still don't understand why we need this complicated change here . Why can
not just allocate few more extra space in the ring for each read and use the
space to store the output value ?
Regards
Shaoyun.liu
Wait for the oldest sequence on the kiq ring
to be signaled in order to make sure there
will be no kiq overrun.
v2: remove unused the variable and correct
kiq max_sub_num value
Signed-off-by: Yintian Tao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 6
.../gpu/drm/amd/amdgpu/amd
Hi Shaoyun,
the ring buffer is usually filled with command and not read results.
Allocating extra space would only work if we use the special NOP command
and that is way more complicated and fragile than just using the wb
functions which where made for this stuff.
Regards,
Christian.
Am 22.
[AMD Official Use Only - Internal Distribution Only]
I think each kiq operation will call ring_alloc for the package space , why
not just check whether this allocation is succeed or not ?
Shaoyun.liu
-Original Message-
From: amd-gfx On Behalf Of Yintian Tao
Sent: Wednesday, Apri
The amdgpu_ring_alloc() function checks if the requested number of DW
don't exceed the maximum submission size.
It does NOT check if there is enough room on the ring. That would
require MMIO access and that is what we want to avoid.
Regards,
Christian.
Am 22.04.20 um 16:54 schrieb Liu, Shaoy
[AMD Official Use Only - Internal Distribution Only]
Usually doesn't means we can not do it . I feel this proposal is the
simplest and clean . But anyway this is just my suggestion.
Regards
Shaoyun.liu
-Original Message-
From: Koenig, Christian
Sent: Wednesday, April 22, 2020 10:5
Hi Shaoyun
There is one rare corner case which will raise problem when using ring buffer
to store value.
It is assumed there are only total four slots at KIQ ring buffer.
And these four slots are fulfilled with command to read registers. Slot-A
Slot-B Slot-C Slot-D
And they are waiting for
Yeah, we discussed that approach as well. But both Yintian and I agreed
that this is the simpler solution.
Regards,
Christian.
Am 22.04.20 um 16:59 schrieb Liu, Shaoyun:
[AMD Official Use Only - Internal Distribution Only]
Usually doesn't means we can not do it . I feel this proposal is th
[AMD Official Use Only - Internal Distribution Only]
This is the issue you try to solve with your second patch (protect kiq
overrun) . For current patch , if you store the output value in each ring
buffer itself , each kiq operation will be atomic and self contain .
Shaoyun.liu
-Origin
Hi Shaoyun
No, the second patch can't solve this rare case because only Slot-D is signaled
and the Slot-A can be overwritten.
The second patch think the sequence is signaled the Slot-A buffer can be freed.
if you store the output value in each ring buffer itself , each kiq operation
will b
[AMD Official Use Only - Internal Distribution Only]
I always has an impression for each submission, once the ring be allocated ,
before the fence be signed , this ring space will always be reserved . If this
can not be guaranteed , it sound a big issue to me . Can't we check the
rptr wr
Add more
Especially for the multi-VF environment, we have to wait through msleep()
instead udeay.
Because the max udelay time is 15VF * 6ms(world-switch) = 90ms.
-Original Message-
From: amd-gfx On Behalf Of Tao, Yintian
Sent: 2020年4月22日 23:43
To: Liu, Shaoyun ; Koenig, Christian
; L
[AMD Official Use Only - Internal Distribution Only]
OK, I see, the submission it self be signaled so the ring space for this
submission will be re-use by other submission , but the CPU still not read the
out put value yet.
Thanks
Shaoyun.liu
-Original Message-
From: Tao, Yintian
>-Original Message-
>From: dri-devel On Behalf Of
>Bernard Zhao
>Sent: Tuesday, April 21, 2020 7:17 AM
>To: Alex Deucher ; Christian König
>; David (ChunMing) Zhou
>; David Airlie ; Daniel Vetter
>; Tom St Denis ; Ori Messinger
>; Sam Ravnborg ; Bernard
>Zhao ; amd-gfx@lists.freedesktop.or
Hi Shaoyun
Yes, you are right. It is the rare corner case.
Best Regards
Yintian Tao
-Original Message-
From: Liu, Shaoyun
Sent: 2020年4月22日 23:51
To: Tao, Yintian ; Koenig, Christian
; Liu, Monk ; Kuehling, Felix
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amdgpu: re
[+Philip Yang]
Am 2020-04-21 um 8:21 p.m. schrieb Jason Gunthorpe:
> From: Jason Gunthorpe
>
> Presumably the intent here was that hmm_range_fault() could put the data
> into some HW specific format and thus avoid some work. However, nothing
> actually does that, and it isn't clear how anything a
Am 22.04.20 um 17:51 schrieb Ruhl, Michael J:
-Original Message-
From: dri-devel On Behalf Of
Bernard Zhao
Sent: Tuesday, April 21, 2020 7:17 AM
To: Alex Deucher ; Christian König
; David (ChunMing) Zhou
; David Airlie ; Daniel Vetter
; Tom St Denis ; Ori Messinger
; Sam Ravnborg ; Berna
Can't we check the rptr write back to determine the available room in the
ring_alloc ?
We removed that a couple of years ago.
One reason for this is that checking the rptr each time is quite a huge
overhead since it is an MMIO register.
The other reason is that the rptr is no longer a sec
Am 22.04.20 um 16:50 schrieb Yintian Tao:
Wait for the oldest sequence on the kiq ring
to be signaled in order to make sure there
will be no kiq overrun.
v2: remove unused the variable and correct
kiq max_sub_num value
First of all this should probably be added to the fence handling code
On 4/21/20 5:21 PM, Jason Gunthorpe wrote:
From: Jason Gunthorpe
The API is a bit complicated for the uses we actually have, and
disucssions for simplifying have come up a number of times.
This small series removes the customizable pfn format and simplifies the
return code of hmm_range_fault
On Wed, Apr 22, 2020 at 10:00 AM Harry Wentland wrote:
>
> On 2020-04-21 7:34 p.m., Randy Dunlap wrote:
> > From: Randy Dunlap
> >
> > Fix help text: indent one tab + 2 spaces; end a sentence with a
> > period; and collapse short lines of text to one line.
> >
> > Fixes: 23c61b4599c4 ("drm/amd: F
On Tue, Apr 21, 2020 at 10:34 AM Christian König
wrote:
>
> Am 21.04.20 um 16:33 schrieb Christian König:
> > Am 20.04.20 um 03:50 schrieb Randy Dunlap:
> >> Fix a kernel-doc warning of missing struct field desription:
> >>
> >> ../drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:92: warning: Function
> >>
On Wed, Apr 22, 2020 at 9:13 AM limingyu wrote:
>
> For chip like CHIP_OLAND with si enabled(amdgpu.si_support=1),
> the amdgpu will expose pp_num_states to the /sys directory.
> In this moment, read the pp_num_states file will excute the
> amdgpu_get_pp_num_states func. In our case, the data hasn
This DC patchset brings improvements in multiple areas. In summary, we
hightlight:
* DC version 3.2.83.1
* Enhancements and refactoring in DMUB
* Improvments for DCN2, backlight and others
__
Anthony Koo (1):
drm/amd/display: clean up some header paths
Aric Cyr (4):
drm/amd/display: 3.2.82
From: Anthony Koo
[Why]
Some include paths don't need to have relative paths
And some types missing
[How]
make some changes to headers and modify include path
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 5432ca1657b1..84
From: Sung Lee
[WHY]
If mode is not supported, pipe split should not be disabled.
This may cause more modes to fail.
[HOW]
Check for mode support before disabling pipe split.
This commit was previously reverted as it was thought to
have problems, but those issues have been resolved.
Signed-off
From: Dmytro Laktyushkin
Check before programming the register since it isn't present on
all IPs using this code.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
1 file changed, 2 inserti
From: Nicholas Kazlauskas
[Why]
The new metadata offset is located at the end of the firmware binary
without any additional padding.
Firmware state is currently larger than 1024 bytes so new firmware state
will hang when trying to access any data above 1024 bytes.
[How]
Specify the correct offs
From: Nicholas Kazlauskas
[Why]
We read memory that we shouldn't be touching if the struct isn't
a full union dmub_rb_cmd.
[How]
Fix up all the callers and functions that take in the dmub_cmd_header
to use the dmub_rb_cmd instead.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by: Tony Cheng
Ack
From: Sung Lee
[WHY]
The downspread percentage was copied over from a previous version
of the display_mode_lib spreadsheet. This value has been updated,
and the previous value is too high to allow for such modes as
4K120hz. The new value is sufficient for such modes.
[HOW]
Update the value in dc
From: Yongqiang Sun
[Why & How]
Add panel cntl instance when calling set backlight.
Signed-off-by: Yongqiang Sun
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
Acked-by: Tony Cheng
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++-
drivers/gpu/drm/amd/display/dc/core/dc_li
From: Joshua Aberback
Signed-off-by: Joshua Aberback
Reviewed-by: Dmytro Laktyushkin
Reviewed-by: Jun Lei
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h | 1 +
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 1 +
drivers/gpu/drm/amd/displ
From: Nicholas Kazlauskas
[Why]
Fixes the following scenario:
- Flip has been prepared sometime during the frame, update pending
- Cursor update happens right when VUPDATE would happen
- OPTC lock acquired, VUPDATE is blocked until next frame
- Flip is delayed potentially infinitely
With the ig
From: Joshua Aberback
[Why]
For debugging, it can be useful to be able to modify the dummy
p-state latency, this will make it easier to do so.
Signed-off-by: Joshua Aberback
Reviewed-by: Wesley Chalmers
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 1
From: Sung Lee
[WHY & HOW]
If building scaling parameters fails, validation
should also fail.
Signed-off-by: Sung Lee
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c| 16 ++--
.../drm/amd/display/dc/dcn20/dcn20_reso
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index b4aeb5d8a818..89
From: Krunoslav Kovac
[Why&How]
modules/color calculates various colour operations which are translated
to abstracted HW. DCE 5-12 had almost no important changes, but
starting with DCN1, every new generation comes with fairly major
differences in color pipeline.
We would hack it with some DCN ch
From: Dmytro Laktyushkin
Currently RN SOC bounding box update assumes we will get at least
2 clock states from SMU. This isn't always true and because of special
casing on first clock state we end up with low disp, dpp, dsc and phy
clocks.
This change removes the special casing allowing the firs
From: Yongqiang Sun
[Why & How]
Add set backlight to hw sequencer, dmu communication will
be handled in hw sequencer for new asics.
Signed-off-by: Yongqiang Sun
Reviewed-by: Anthony Koo
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 35 ++-
...
From: Sung Lee
[WHY & HOW]
Viewport limit was set to 16 pixels due to an issue with MPO
on small viewports. This restriction does not apply and the
viewport limit can now be lowered.
Signed-off-by: Sung Lee
Reviewed-by: Dmytro Laktyushkin
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/di
From: Aric Cyr
[Why]
Current locking scheme for cursor can result in a flip missing
its vsync, deferring it for one or more vsyncs. Result is a
potential for stuttering when cursor is moved.
[How]
Use cursor update lock so that flips are not blocked while cursor
is being programmed.
Signed-off
From: Aric Cyr
Update firmware blobs
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
Hi Dave, Daniel,
Fixes for 5.7.
The following changes since commit 4da858c086433cd012c0bb16b5921f6fafe3f803:
Merge branch 'linux-5.7' of git://github.com/skeggsb/linux into drm-fixes
(2020-04-16 15:40:02 +1000)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/li
Track GPU VRAM usage on a per process basis and report it through
sysfs.
v2:
- Handle AMDGPU BO-specific details in
amdgpu_amdkfd_gpuvm_free_memory_of_gpu().
- Return size of VRAM BO being freed from
amdgpu_amdkfd_gpuvm_free_memory_of_gpu().
- Do not consider imported memory
Hi Christian
Ok , I got it. The real max number can be submitted to kiq ring buffer is 1024.
If we use the num_fneces_mask value then the max submission number will be
reduced to 512, do you think whether it is ok?
Best Regards
Yintian Tao
-Original Message-
From: Koenig, Christian
Wait for the oldest sequence on the ring
to be signaled in order to make sure there
will be no command overrun.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdg
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