Hi all,
this series improves the use_mm / unuse_mm interface by better
documenting the assumptions, and my taking the set_fs manipulations
spread over the callers into the core API.
Changes since v1:
- drop a few patches
- fix a comment typo
- cover the newly merged use_mm/unuse_mm caller in v
On Thu, Apr 16, 2020 at 07:31:57AM +0200, Christoph Hellwig wrote:
> Switch the function documentation to kerneldoc comments, and add
> WARN_ON_ONCE asserts that the calling thread is a kernel thread and
> does not have ->mm set (or has ->mm set in the case of unuse_mm).
>
> Also give the function
Switch the function documentation to kerneldoc comments, and add
WARN_ON_ONCE asserts that the calling thread is a kernel thread and
does not have ->mm set (or has ->mm set in the case of unuse_mm).
Also give the functions a kthread_ prefix to better document the
use case.
Signed-off-by: Christop
Some architectures like arm64 and s390 require USER_DS to be set for
kernel threads to access user address space, which is the whole purpose
of kthread_use_mm, but other like x86 don't. That has lead to a huge
mess where some callers are fixed up once they are tested on said
architectures, while o
On Thu, Apr 16, 2020 at 07:31:58AM +0200, Christoph Hellwig wrote:
> Some architectures like arm64 and s390 require USER_DS to be set for
> kernel threads to access user address space, which is the whole purpose
> of kthread_use_mm, but other like x86 don't. That has lead to a huge
> mess where so
These helpers are only for use with kernel threads, and I will tie them
more into the kthread infrastructure going forward. Also move the
prototypes to kthread.h - mmu_context.h was a little weird to start with
as it otherwise contains very low-level MM bits.
Signed-off-by: Christoph Hellwig
Ack
On 2020-04-03 12:20 p.m., Likun Gao wrote:
> From: Likun Gao
>
> Change SH_MEM_CONFIG Alignment mode to Automatic, as:
> 1)OGL fn_amd_compute_shader will failed with unaligned mode.
> 2)The default alignment mode was defined to automatic on gfx10
> specification.
>
> Signed-off-by: Likun Gao
>
Vega20 arbitrates pstate at hive level and not device level. Last peer to
remote buffer unmap could drop P-State while another process is still
remote buffer mapped.
With this fix, P-States still needs to be disabled for now as SMU bug
was discovered on synchronous P2P transfers. This should be f
Update the list with supported Arcturus chips, but disable for now until
final list is confirmed.
Ideally we can poll atombios for FRU support, instead of maintaining
this list of chips, but this will enable serial number reading for
supported ASICs for the time-being.
Signed-off-by: Kent Russell
Hello Bhawanpreet Lakha,
The patch 4c283fdac08a: "drm/amd/display: Add HDCP module" from Aug
6, 2019, leads to the following static checker warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/hdcp/hdcp_msg.c:132
hdmi_14_process_transaction()
error: buffer overflow 'hdcp_i2c_offsets
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: amd-gfx On Behalf Of
> Michel Dänzer
> Sent: Thursday, April 16, 2020 5:57 AM
> To: Gao, Likun ; Marek Olšák ;
> Pierre-Eric Pelloux-Prayer
> Cc: amd-gfx@lists.freedesktop.org; Zhang, Hawking
>
> Subject:
[AMD Public Use]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Kent Russell
Sent: Thursday, April 16, 2020 8:26 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH] drm/amdgpu: Disable FRU read on Arcturus
Update the list with suppo
On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula wrote:
>
>
> Alex, Harry, Christian, can you please eyeball this series and see if it
> makes sense for you?
>
Patches 4, 5 are:
Acked-by: Alex Deucher
Feel free to take them through whichever tree you want.
Alex
> Thanks,
> Jani.
>
>
> On Tue, 07 A
On 2020-04-16 3:25 p.m., Deucher, Alexander wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
>> -Original Message-
>> From: amd-gfx On Behalf Of
>> Michel Dänzer
>> Sent: Thursday, April 16, 2020 5:57 AM
>> To: Gao, Likun ; Marek Olšák ;
>> Pierre-Eric Pelloux-Prayer
>> Cc
When running ras uncorrectable error injection and trigger GPU
reset on sGPU, below issue is observed. It's caused by the list
uninitialized when accessing.
[ 80.047227] BUG: unable to handle page fault for address: c0f4f750
[ 80.047300] #PF: supervisor write access in kernel mode
[
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: John Clements
-Original Message-
From: Chen, Guchun
Sent: Thursday, April 16, 2020 11:48 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li,
Dennis ; Clements, John
Cc: Chen, Guchun
Subject: [PATCH] drm/amdgpu:
[AMD Official Use Only - Internal Distribution Only]
Hi Felix,
You're probably right.
Passing Vega20 system:
[ 56.683273] amdgpu: [vram dbg] addr 3e78, val deadbeef
[ 56.683349] amdgpu: [vram dbg] addr 3efed000, val cafebabe
<- potential misalign access
This reverts commit 3fded222f4bf7f4c56ef4854872a39a4de08f7a8
This is work around for vcn1 only. Currently vcn1 has separate
begin_use and idle work handle.
Signed-off-by: James Zhu
Tested-by: changzhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
1 file changed, 2 deletions(-)
diff --git
[AMD Official Use Only - Internal Distribution Only]
Is this ok for navi1x gfxoff?
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of James Zhu
Sent: Thursday, April 16, 2020 12:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James ; Zhu, Changfeng
Subjec
[AMD Official Use Only - Internal Distribution Only]
Hi,
I will look into it, thanks.
Bhawan
From: Dan Carpenter
Sent: April 16, 2020 9:24 AM
To: Lakha, Bhawanpreet
Cc: amd-gfx@lists.freedesktop.org
Subject: [bug report] drm/amd/display: Add HDCP module
Hello
On Thu, 16 Apr 2020, Alex Deucher wrote:
> On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula wrote:
>>
>>
>> Alex, Harry, Christian, can you please eyeball this series and see if it
>> makes sense for you?
>>
>
> Patches 4, 5 are:
> Acked-by: Alex Deucher
> Feel free to take them through whichever tre
[Why]
Aconnector is not necessary to be NULL in order to read dpcd
successfully.
Actually if we rely on checking aconnector here, we won't be able
to turn off all displays before doing display detection. That will
cause some MST hubs not able to light up.
[How]
Remove aconnector check when turnin
KFD need sto surface the ASIC revision in certain circumstances.
amdgpu already has this floating around, so add in an
amdgpu_amdkfd interface function to pull it over to KFD.
Signed-off-by: Joseph Greathouse
Change-Id: I745196129d65e1d0d4349f8d3b3f828df961a603
---
drivers/gpu/drm/amd/amdgpu/amd
In order to surface the ASIC revision to user level, we want
to put it into the HSA topology. This can be because different
ASIC revisions may require user-level software to do different
things (e.g. patch code for things that are changed in later
hardware revisions).
The ASIC revision from the ha
Mirror what we do for i2c display buses.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 7 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h| 3 ++-
3 files changed
We were registering the aux device in the MST late_register
rather than the regular one.
Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration
(v4)")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgp
Mirror what we do for i2c display buses.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 7 +--
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h| 3 ++-
3 files changed
We were registering the aux device in the MST late_register
rather than the regular one.
v2: handle eDP as well
Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration
(v4)")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100
Signed-off-by: Alex Deucher
---
drivers/g
Thank you Joe.
You can squash the two patches into one. KFD and AMDGPU are really one
component, and separating changes into separate commits is not
necessary. I'd also make amdgpu_amdkfd_get_asic_rev_id a static inline
function in amdgpu_amdkfd.h, since it's just a one-liner.
Other than that, th
On 2020-04-16 3:43 p.m., Alex Deucher wrote:
> Mirror what we do for i2c display buses.
>
> Signed-off-by: Alex Deucher
Series is
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_ty
From: Dale Zhao
[Why]:
Renoir's pipe VM flags are not correctly updated if pipe strategy has
changed during some scenarios. It will result in watermarks mistakenly
calculation, thus underflow and garbage appear.
[How]:
Correctly update pipe VM flags to pipes which have been populated.
Signed-of
From: Wyatt Wood
[Why]
Porting abm from dmcu to dmcub missed one register write.
[How]
Add this register write in the SetBacklightLevel sequence.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 ++
1 file ch
From: Anthony Koo
[Why]
without destroy it is causing a memory leak
[How]
destroy panel on link destruct
Signed-off-by: Anthony Koo
Reviewed-by: Wyatt Wood
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/dri
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 89cce79c950d..f9
From: Nicholas Kazlauskas
[Why]
A NULL ramp is a valid configuration for passing into
mod_color_calculate_degamma_params but we'll hit a NULL pointer if we do
so.
We need this in order to get the right transfer function to do degamma
on NV12 formats where we aren't supplied with a custom user de
From: Paul Hsieh
[Why]
Driver already get display clock from SMU base on MHz, but driver read
again and mutiple 1000 cause wait loop value is overflow.
[How]
remove coding error
Signed-off-by: Paul Hsieh
Reviewed-by: Eric Yang
Acked-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/clk_mgr/dc
From: Wyatt Wood
[Why]
Set backlight calls to firmware are are being prevented by dmcu == null
check. Dmcu is expected to be null in this case.
[How]
Only prevent call if dmcu and abm are null. Also rename variable
'use_smooth_brightness' to 'fw_set_brightness' as it's more appropriate.
Signed
This DC patchset brings improvements in multiple areas. In summary, we
highlight:
* Improvements on:
- DM color management
- Backlight panel
* Fixes on:
- Suspend issues
- Virtual signal dsc setup
- HDR visual confirm
Anthony Koo (4):
drm/amd/display: make all backlight calls link ba
From: Dmytro Laktyushkin
This prevents dpcd access on virtual links.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: Nicholas Kazlauskas
[Why]
We expect to be able to perform immediate flipping without having to
recalculate and update all the watermarks.
There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such
that we get a urgency value of 0 for frac_urg_bw_flip because we're
explicitly pass
From: Anthony Koo
[Why]
Backlight adjustment is tied to a specific display. So make the calls
target a link rather than making it a global state.
[How]
make all backlight calls link based
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
.../amd/display/amdg
From: Wyatt Wood
[Why]
- Driver does not recognize new definitions of psr states.
- Internal tool is required for checking if psr is active.
[How]
- Parse psr state correctly so that driver will recognize psr state.
- Add visual confirmation that psr is active using existing mechanisms.
Signed-
From: Joshua Aberback
[Why]
The HUBBUB watermark registers are in an area that cannot be power
gated, but the HUBP copies of the watermark values are in areas that can
be power gated. When we power on a pipe, it will not automatically take
the HUBBUB values, we need to force propagation by writin
From: Sung Lee
[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.
[HOW]
If the pixel clock is low and some values are high, cap it to the max.
Signed-off-by: Sung Lee
Reviewed-by: Dmyt
From: Jaehyun Chung
[Why]
HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation
were only added to dcn20.
[How]
Add hubp cursor position calculation changes to dcn10.
Signed-off-by: Jaehyun Chung
Reviewed-by: Yongqiang Sun
Acked-by: Rodrigo Siqueira
---
.../gpu/drm/amd
[why]
We have seen a green screen after resume from suspend in a Raven system
connected with two displays (HDMI and DP) on X based system. We noticed
that this issue is related to bad DCC metadata from user space which may
generate hangs and consequently an underflow on HUBP. After taking a
deep lo
From: Xiaodong Yan
[Why]
When link loss happened, monitor can not light up if only re-train the
link.
[How]
Blank all the DP streams on this link before re-train the link, and then
unblank the stream
Signed-off-by: Xiaodong Yan
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/
From: Aurabindo Pillai
[why]
Organizational Unit Identifier register is optional, and its
presence is published via Down Stream Port Count register.
Writing this register when not available will result in errors
[how]
Read this register and continue writing OUI only if the panel
has the support
From: Wenjing Liu
[why]
Optc needs to know if timing is enabled with ODM or DSC before computing
crc. Otherwise value computed will be inaccurate. Before this change,
the CRC computed without ODM is not equal to the CRC computed with ODM
for the same timing. This is unexpected as we are driving
From: Sung Lee
[WHY]:
Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead
to a large number causing an assert to get hit. In VBA, this value is 0
when DCC is disabled.
[HOW]:
Set value to 0 to avoid hitting the assert.
Signed-off-by: Sung Lee
Reviewed-by: Dmytro Laktyushki
From: Anthony Koo
[Why]
it doesn't represent panel specifically, it's more like the control
logic for the panel
[How]
change from panel to panel cntl to make it a bit more clear
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/
From: Aric Cyr
Don't skip MPCC tree updates if requested.
Signed-off-by: Aric Cyr
Reviewed-by: Joshua Aberback
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/d
From: Haiyi Zhou
[Why]
Certain displays may experience blanking if infopacket max range does
not equal nominal refresh rate.
[How]
Add additional infopacket versions to program range to full or forced
range in freesync states.
This does not change the vrr logic.
Signed-off-by: Haiyi Zhou
Revie
From: Wyatt Wood
[Why]
Dmcu init fw call has some logic to initialize abm values. Since this
doesn't exist on dmcub, must find a proper place for it in the abm
sequence.
[How]
Move enable fractional pwm call.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Rodrigo Siqueira
---
From: Dmytro Laktyushkin
We need to set up stream even with virtual displays when running
diags.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Eric Bernstein
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-
From: Stylon Wang
[Why]
Plane-level gamut remap is not enabled in DM, which is necessary to
support CTM as a plane-level property.
[How]
Enable gamut remap in DM.
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/amdgpu_dm
From: Sung Lee
[Why]:
Some inputs to dml_ceil have it dividied by int which causes a
truncation. This loss of precision means the ceil function becomes
redundant and does not round up.
[How]:
Cast parameter to float before division.
Signed-off-by: Sung Lee
Reviewed-by: Dmytro Laktyushkin
Acke
From: Wyatt Wood
[Why]
As it stands, psr has feature flags in dm, stream, and link. Most are
not defined well enough, and different dm layers have different uses for
these same flags.
[How]
We define a new structure called psr_settings in dc_link that will hold
the following psr feature flags:
From: Nicholas Kazlauskas
[Why]
On ASIC without ABM support (most dGPU) we run into a null pointer
dereference when attempting to set the backlight level.
[How]
This function requires ABM, so fix up the condition to only allow
DMCU to be optional.
Signed-off-by: Nicholas Kazlauskas
Reviewed-by
From: Aric Cyr
Some cases were incorrectly reporting the wrong visual confirm, even
though they were working as expected.
Signed-off-by: Aric Cyr
Reviewed-by: Krunoslav Kovac
Acked-by: Rodrigo Siqueira
---
.../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 +--
1 file changed
From: Jinze Xu
[Why]
Some mst dock can't translate DP to HDMI properly.
[How]
Bypass YCbCr timings on specific MST device.
Signed-off-by: Jinze Xu
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 1 +
drivers/gpu/drm/amd/display/dc/dc.h
From: Stylon Wang
[Why]
Commit 4ca3f1217e6106779aea9ebabdd09f695d42f2ff is causing regression
from changing the order of call sequence.
[How]
Keep the call sequence and take in extra dm state only if plane-level
color management is enabled.
Signed-off-by: Stylon Wang
Reviewed-by: Nicholas Kazl
From: Nicholas Kazlauskas
[Why]
Color blending for NV12 formats is incorrect because we're using the
predefined SRGB degamma.
[How]
Calculate the correct input transfer function for degamma from the color
module depending on what the actual surface format is.
Signed-off-by: Nicholas Kazlauskas
From: Wyatt Wood
[Why]
Since x86 and dmcub are both little endian, byte swapping isn't
necessary. Dmcu requires byte swapping as it is big endian.
[How]
Add flag to function definitions to determine if byte swapping is
necessary.
Signed-off-by: Wyatt Wood
Reviewed-by: Anthony Koo
Acked-by: Ro
From: Anthony Koo
[Why]
panel power sequencer is currently just sitting in hwseq but it really
it tied to internal panels
[How]
make a new panel struct to contain power sequencer code
Signed-off-by: Anthony Koo
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/displ
From: Yongqiang Sun
[Why]
Since ABM resource is mapped to stream res, all the ABM access should
via stream res.
[How]
Get ABM instance from stream res instead of resource pool.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc
On Wed, Apr 15, 2020 at 11:43:24PM +0800, Liang, Prike wrote:
> When the amdgpu in the suspend/resume loop need notify the dpm disabled,
> otherwise the smu table will be uninitialize and result in resume failed.
>
> Signed-off-by: Prike Liang
> Tested-by: Mengbing Wang
Reviewed-by: Huang Rui
[AMD Public Use]
I would drop this patch unless it only applies to APUs. On Linux, people may
run the driver on big endian systems.
Alex
From: amd-gfx on behalf of Rodrigo
Siqueira
Sent: Thursday, April 16, 2020 7:40 PM
To: amd-gfx@lists.freedesktop.org
Cc:
On Wed, Apr 15, 2020 at 07:20:31PM +0800, Yuxian Dai wrote:
> we should avoid to show the invalid level value when the
> DPM_LEVELS supported number changed
>
> Signed-off-by: Yuxian Dai
> Change-Id: Ib66d0cf34a866fa6f0cedd1d5fc642f59236787d
Please add comment in the commit message to explain so
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
drivers/gpu/drm/amd/p
[AMD Official Use Only - Internal Distribution Only]
On Wed, Apr 15, 2020 at 07:20:31PM +0800, Yuxian Dai wrote:
> we should avoid to show the invalid level value when the DPM_LEVELS
> supported number changed
>
> Signed-off-by: Yuxian Dai
> Change-Id: Ib66d0cf34a866fa6f0cedd1d5fc642f59236787d
Acked-by: Evan Quan
-Original Message-
From: amd-gfx On Behalf Of Kent Russell
Sent: Thursday, April 16, 2020 8:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent
Subject: [PATCH] drm/amdgpu: Disable FRU read on Arcturus
Update the list with supported Arcturus chips, but disable
There are still some concurrency issues. See comments inline.
Regards,
Felix
Am 2020-04-15 um 10:01 p.m. schrieb Amber Lin:
> When the compute is malfunctioning or performance drops, the system admin
> will use SMI (System Management Interface) tool to monitor/diagnostic what
> went wrong. This
Am 2020-04-16 um 7:59 a.m. schrieb Jonathan Kim:
> Vega20 arbitrates pstate at hive level and not device level. Last peer to
> remote buffer unmap could drop P-State while another process is still
> remote buffer mapped.
>
> With this fix, P-States still needs to be disabled for now as SMU bug
> wa
SMU IP needs to be loaded for onevf mode. Otherwise, there
may be accesses without initialization.
V2: added SMU IP for all sriov cases since there is necessary
checks in IP operations(hw_init/fini)
Change-Id: I513aa4140f1169ca048b64985cafe9c7577afca7
Signed-off-by: Evan Quan
---
drivers/gp
On Fri, Apr 17, 2020 at 10:58:59AM +0800, Yuxian Dai wrote:
> for different ASIC support different the number of DPM levels,
> we should avoid to show the invalid level value.
> v1 -> v2:
> follow the suggestion,clarifiy the description for this
> change
> Signed-off-by: Yuxian Dai
> Change-
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
drivers/gpu/drm/amd/p
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
[AMD Official Use Only - Internal Distribution Only]
On Fri, Apr 17, 2020 at 10:58:59AM +0800, Yuxian Dai wrote:
> for different ASIC support different the number of DPM levels, we
> should avoid to show the invalid level value.
> v1 -> v2:
> follow the suggestion,clarifiy the description f
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 throug
for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
drivers/gpu/drm/amd/p
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