Update the smu12_driver_if.h header to follow the pmfw release.
Signed-off-by: Prike Liang
---
.../gpu/drm/amd/powerplay/inc/smu12_driver_if.h| 42 ++
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
b/dr
For Arcturus, forcing clock to some specific level is not supported
with 54.18 and onwards SMU firmware. As according to firmware team,
they adopt new gfx dpm tuned parameters which can cover all the use
case in a much smooth way. Thus setting through driver interface
is not needed and maybe do a d
Incorrect CG sequence will cause gfx timedout,
if we keep switching power profile mode
(enter profile mod such as PEAK will disable CG,
exit profile mode EXIT will enable CG)
when run Vulkan test case(case used for test: vkexample).
Signed-off-by: Chengming Gui
---
drivers/gpu/drm/amd/amdgpu/gfx
[AMD Official Use Only - Internal Distribution Only]
This sequence is confirmed in the design document.
Reviewed-by: Kenneth Feng
-Original Message-
From: Chengming Gui
Sent: Friday, April 3, 2020 3:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ; Yin,
Tianci
Acked-by: Evan Quan
-Original Message-
From: Chengming Gui
Sent: Friday, April 3, 2020 3:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ; Yin,
Tianci (Rico) ; Xu, Feifei ; Zhang,
Hawking ; Gui, Jack
Subject: [PATCH] drm/amd/amdgpu: Correct gfx10's CG sequence
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of Zhou,
>Tiecheng
>Sent: Friday, April 3, 2020 12:42 PM
>To: Zhou, Tiecheng ; amd-
>g...@lists.freedesktop.org
>Cc: Tao, Yintian
>Subject: RE: [PATCH] drm/amd/powe
Reviewed-by: Monk Liu
_
Monk Liu|GPU Virtualization Team |AMD
-Original Message-
From: amd-gfx On Behalf Of Jack Zhang
Sent: Friday, April 3, 2020 1:03 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian)
Subject: [PATCH] drm/amdgpu/sriov add
On Wed, Apr 01, 2020 at 04:04:14PM +, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Daniel Vetter
> >Sent: Wednesday, April 1, 2020 7:35 AM
> >To: Christian König
> >Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> >Subject: Re: [P
On 4/3/20 8:03 AM, Prike Liang wrote:
As the pmfw hasn't exported the interface of SMU feature
mask to APU SKU so just force on all the features to driver
inquired interface at early initial stage.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: Tianci Yin
Sent: 2020年4月3日 13:30
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Hesik, Christopher
; Zhang, Hawking ; Xu, Feifei
; Yin, Tianci (Rico)
Subject: [PATCH] d
ping!
On 3/31/20 3:59 PM, Nirmoy Das wrote:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in stru
Am 31.03.20 um 15:59 schrieb Nirmoy Das:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct a
On 4/3/20 10:55 AM, Christian König wrote:
Am 31.03.20 um 15:59 schrieb Nirmoy Das:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_lis
Am 03.04.20 um 11:09 schrieb Nirmoy:
On 4/3/20 10:55 AM, Christian König wrote:
Am 31.03.20 um 15:59 schrieb Nirmoy Das:
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unneces
> -Original Message-
> From: Huang, Ray
> Sent: Friday, April 3, 2020 2:27 PM
> To: Liang, Prike
> Cc: amd-gfx@lists.freedesktop.org; Quan, Evan ;
> Deucher, Alexander ; Kuehling, Felix
>
> Subject: Re: [PATCH] drm/amdgpu: fix gfx hang during suspend with video
> playback
>
> (+ Felix
On Fri, Apr 03, 2020 at 05:22:28PM +0800, Liang, Prike wrote:
>
> > -Original Message-
> > From: Huang, Ray
> > Sent: Friday, April 3, 2020 2:27 PM
> > To: Liang, Prike
> > Cc: amd-gfx@lists.freedesktop.org; Quan, Evan ;
> > Deucher, Alexander ; Kuehling, Felix
> >
> > Subject: Re: [PAT
From: Likun Gao
Change SH_MEM_CONFIG Alignment mode to Automatic, as:
1)OGL fn_amd_compute_shader will failed with unaligned mode.
2)The default alignment mode was defined to automatic on gfx10
specification.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file ch
On Fri, Apr 03, 2020 at 06:05:55PM +0800, Huang Rui wrote:
> On Fri, Apr 03, 2020 at 05:22:28PM +0800, Liang, Prike wrote:
> >
> > > -Original Message-
> > > From: Huang, Ray
> > > Sent: Friday, April 3, 2020 2:27 PM
> > > To: Liang, Prike
> > > Cc: amd-gfx@lists.freedesktop.org; Quan, E
add indirect access support to registers outside of
mmio bar.
Change-Id: I825c9c67dce8fa010e3072d65e45eae7bbd3b45a
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 18 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 +++---
driver
all the register access through kiq is redirected
to amdgpu_kiq_rreg/amdgpu_kiq_wreg
Change-Id: Ib46637c7095ca0cb9c3200a7ed19347e47cb816d
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
2 files changed, 4
not needed anymore
Change-Id: I26b4b742acda4387ca25b86db83b8c9376ed4f3b
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 8
drivers/gpu/drm/amd/include/cgs_common.h | 1 -
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
those are not needed anymore
Change-Id: I2c2696eaa82ef6777ad518d9333cda9deced0f94
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/
The series refined register access interfaces including:
1. add indirect access support to registers outside of mmio bar
2. remove the inproper workaround leaving in the low level if
3. retire legacy interface RREG32_IDX/WREG32_IDX
4. retire redundant flags AMDGPU_REGS_KIQ/AMDGPU_REGS_IDX
Hawking
the workaround is not needed for soc15 ASICs except
for vega10. it is even not needed with latest vega10
vbios.
Change-Id: Ibcf6f32f756f62004944d5543ff475e508b98a09
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1
all the mmCUR_CONTROL instances are in mmr range and
can be accessd directly by using RREG32/WREG32
Change-Id: I156f760276bddf6dec8936952a371c0255ab1b42
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8
dr
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Gao, Likun
Sent: Friday, April 3, 2020 18:20
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Gao, Likun
Subject: [PATCH] drm/amdgpu: change SH MEM alignment
VCN shared memory needs restore after wake up during S3 test.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 26 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vc
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of James Zhu
Sent: 2020年4月3日 20:52
To: amd-gfx@lists.freedesktop.org
Cc: Li, Pauline ; Zhu, James
Subject: [PATCH] drm/amdgpu/vcn: add shared menory restore after wa
Acked-by: Christian König for patches #1, #2
Reviewed-by: Christian König for patches #3 - #6
Regards,
Christian.
Am 03.04.20 um 12:55 schrieb Hawking Zhang:
The series refined register access interfaces including:
1. add indirect access support to registers outside of mmio bar
2. remove the
Thanks Felix. I'll make changes accordingly but please pay attention to
my last reply inline.
On 2020-04-02 7:51 p.m., Felix Kuehling wrote:
On 2020-04-02 4:46 p.m., Amber Lin wrote:
When the compute is malfunctioning or performance drops, the system
admin
will use SMI (System Management Inter
On 2020-03-01 6:46 a.m., Marek Olšák wrote:
> For Mesa, we could run CI only when Marge pushes, so that it's a strictly
> pre-merge CI.
Thanks for the suggestion! I implemented something like this for Mesa:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4432
--
Earthling Michel Dänz
[AMD Public Use]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, April 3, 2020 3:03 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent ; Deucher, Alexander
; Quan, Evan
Subject: [PATCH] drm/amd/powerplay: error out on forcing clock setting not
su
There are 2 SKUs that do not have the FRU on there, and trying to read
that will cause a hang. For now, check for the gaming SKU until a proper
fix can be implemented. This re-enables serial number reporting for
server cards
Signed-off-by: Kent Russell
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_e
On Fri, Apr 3, 2020 at 1:30 AM Tianci Yin wrote:
>
> From: "Tianci.Yin"
>
> Add RLC_SPM golden settings
>
> Change-Id: I616e127171293d915cb3a05dee02f51cec8d8f6f
> Signed-off-by: Tianci.Yin
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c|9 +
> .../gpu/drm/amd/amdgpu/golden_gc_spm_10_
On Fri, Apr 03, 2020 at 02:28:37PM +0900, Masami Hiramatsu wrote:
> On Thu, 2 Apr 2020 16:13:08 +0200
> Peter Zijlstra wrote:
> > Masami, Boris, is there any semi-sane way we can have insn_is_fpu() ?
> > While digging through various opcode manuals is of course forever fun, I
> > do feel like it
On ARCTURUS and RENOIR, powerplay is not supported yet.
When plug in or unplug power jack, ACPI event will issue.
Then kernel NULL pointer BUG will be triggered.
Check for NULL pointers before calling.
Signed-off-by: Aaron Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
1 file changed, 2
When the node is larger than 4GB we overrun the size calculation.
Fix this by correctly limiting the size to the window as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/a
On Fri, Apr 3, 2020 at 8:52 AM James Zhu wrote:
>
> VCN shared memory needs restore after wake up during S3 test.
How big is the shared memory? It might be better to allocate the
memory once at sw_init and then free it in sw_fini rather than
allocating and freeing in every suspend/resume.
Alex
Further thinking about it, I'll use struct kfd_smi_msg_header. Instead
of using struct kfd_smi_msg_vmfault, it's a description about the event.
This way we make it generic to all events.
On 2020-04-03 9:38 a.m., Amber Lin wrote:
Thanks Felix. I'll make changes accordingly but please pay attenti
[AMD Public Use]
Does this need to be protected by a asic_type check as well or is just the
vbios version enough? Will we have other asics with D360 in the vbios version?
Alex
From: amd-gfx on behalf of Kent Russell
Sent: Friday, April 3, 2020 10:43 AM
To: a
[AMD Public Use]
There's always the possibility. I'll add it for sanity and sensibility.
Kent
From: Deucher, Alexander
Sent: Friday, April 3, 2020 11:53 AM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Re-enable FRU check for most models
[AMD Public Use]
On 2020-04-03 11:37 a.m., Alex Deucher wrote:
On Fri, Apr 3, 2020 at 8:52 AM James Zhu wrote:
VCN shared memory needs restore after wake up during S3 test.
How big is the shared memory? It might be better to allocate the
memory once at sw_init and then free it in sw_fini rather than
allocat
Am 2020-04-03 um 11:21 a.m. schrieb Christian König:
> When the node is larger than 4GB we overrun the size calculation.
>
> Fix this by correctly limiting the size to the window as well.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
> 1 file chang
I'm getting the attached WARNING splats since amdgpu dropped its load
callback. They're from
WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb);
in __drm_mode_object_add.
I'm not sure how to address this, since obj_free_cb is always NULL here,
and I don't think MST connector
There are 2 VG20 SKUs that do not have the FRU on there, and trying to read
that will cause a hang. For now, check for the gaming SKU until a proper
fix can be implemented. This re-enables serial number reporting for
server cards
Signed-off-by: Kent Russell
---
drivers/gpu/drm/amd/amdgpu/amdgpu_
There are 2 VG20 SKUs that do not have the FRU on there, and trying to read
that will cause a hang. For now, check for the gaming SKU until a proper
fix can be implemented. This re-enables serial number reporting for
server cards
v2: Add ASIC check
Signed-off-by: Kent Russell
---
drivers/gpu/dr
Replace dev_warn() with dev_info() and note that they are
optional to avoid confusing users.
The RAS TAs only exist on server boards and the HDCP and DTM
TAs only exist on client boards. They are optional either way.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +
On 4/3/20 6:32 PM, Alex Deucher wrote:
Replace dev_warn() with dev_info() and note that they are
optional to avoid confusing users.
The RAS TAs only exist on server boards and the HDCP and DTM
TAs only exist on client boards. They are optional either way.
Signed-off-by: Alex Deucher
Acke
On Fri, Apr 3, 2020 at 12:30 PM Kent Russell wrote:
>
> There are 2 VG20 SKUs that do not have the FRU on there, and trying to read
> that will cause a hang. For now, check for the gaming SKU until a proper
> fix can be implemented. This re-enables serial number reporting for
> server cards
>
> Si
On Fri, Apr 3, 2020 at 6:30 PM Michel Dänzer wrote:
>
>
> I'm getting the attached WARNING splats since amdgpu dropped its load
> callback. They're from
>
> WARN_ON(!dev->driver->load && dev->registered && !obj_free_cb);
>
> in __drm_mode_object_add.
>
> I'm not sure how to address this, s
5 seconds on irc and I've found the splat ...
drm_properties need to be created at driver load time, upfront. You
can attach them to hotpluggable drm_connector objects later on, but
only before calling drm_connector_register().
The warning exists because i915 had the same bug :-)
-Daniel
On Fri,
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, April 3, 2020 12:36 PM
> To: Russell, Kent
> Cc: amd-gfx list
> Subject: Re: [PATCH] drm/amdgpu: Re-enable FRU check for most models
>
> On Fri, Apr 3, 2020 at 12:30 PM Kent
On Fri, Apr 3, 2020 at 12:41 PM Russell, Kent wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Friday, April 3, 2020 12:36 PM
> > To: Russell, Kent
> > Cc: amd-gfx list
> > Subject: Re: [PATCH] drm/amdgpu: Re-ena
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, April 3, 2020 12:48 PM
> To: Russell, Kent
> Cc: amd-gfx list
> Subject: Re: [PATCH] drm/amdgpu: Re-enable FRU check for most models
>
> On Fri, Apr 3, 2020 at 12:41 PM Russ
There are 2 VG20 SKUs that do not have the FRU on there, and trying to read
that will cause a hang. For now, check for the gaming SKU until a proper
fix can be implemented. This re-enables serial number reporting for
server cards
v2: Add ASIC check
v3: Don't default to true for pre-VG10
Signed-of
Original cgroup v2 eBPF code for filtering device access made it
possible to compile with CONFIG_CGROUP_DEVICE=n and still use the eBPF
filtering. Change
commit 4b7d4d453fc4 ("device_cgroup: Export devcgroup_check_permission")
reverted this, making it required to set it to y.
Since the device fil
Hi (patch author here),
This is my first "real" patch, so looking forward to some feedback! I
am not sure if this behavior is the "best one", or if we should
require CONFIG_CGROUP_DEVICE to be set to yes. In that case we can
just abandon this patch and replace the original "#if
defined(CONFIG_CGRO
Hi (patch author here),
This is my first "real" patch, so looking forward to some feedback! I am
not sure if this behavior is the "best one", or if we should require
CONFIG_CGROUP_DEVICE to be set to yes. In that case we can just abandon
this patch and replace the original "#if defined(CONFIG_CGRO
VCN shared memory needs restore after wake up during S3 test.
v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini.
Signed-off-by: James Zhu
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 28 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_
[AMD Official Use Only - Internal Distribution Only]
So are you saying you'll make the event descriptions text rather than binary?
If you switch to a text format, I wouldn't use a binary header. Rather I'd make
it a text format completely. You could use one line per event, that makes it
easy to
According to the hw architect, pre-ZEN parts support
p2p writes and ZEN parts support both p2p reads and writes.
Add entries for Zen parts Raven (0x15d0) and Renoir (0x1630).
Cc: Christian König
Signed-off-by: Alex Deucher
---
drivers/pci/p2pdma.c | 2 ++
1 file changed, 2 insertions(+)
diff
Please separate the two fixes into separate commits.
I'd like to see a better explanation for the changes in
kgd_hqd_destroy. The GFX9 version already has a return -EIO in case
it's in a GPU reset. I would agree with porting that to GFX10. But why
do we need to return 0 only in the SRIOV case?
R
> When I compile the code in X86,there is a warning about
> "'PixelPTEReqHeightPTES' may be used uninitialized in this function".
Would you like to add the tag “Fixes” to the commit message?
Regards,
Markus
___
amd-gfx mailing list
amd-gfx@lists.freedes
On Fri, Apr 3, 2020 at 11:18 AM Aaron Ma wrote:
>
> On ARCTURUS and RENOIR, powerplay is not supported yet.
> When plug in or unplug power jack, ACPI event will issue.
> Then kernel NULL pointer BUG will be triggered.
> Check for NULL pointers before calling.
>
> Signed-off-by: Aaron Ma
Applied.
On Fri, Apr 3, 2020 at 1:09 PM Kent Russell wrote:
>
> There are 2 VG20 SKUs that do not have the FRU on there, and trying to read
> that will cause a hang. For now, check for the gaming SKU until a proper
> fix can be implemented. This re-enables serial number reporting for
> server cards
>
> v2:
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Alex Deucher
> Sent: Friday, April 3, 2020 4:51 PM
> To: Russell, Kent
> Cc: amd-gfx list
> Subject: Re: [PATCH] drm/amdgpu: Re-enable FRU check for most models v3
>
> On Fri, Apr 3, 2020 at 1:09 PM Kent
On Fri, Apr 3, 2020 at 5:02 PM Russell, Kent wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Friday, April 3, 2020 4:51 PM
> > To: Russell, Kent
> > Cc: amd-gfx list
> > Subject: Re: [PATCH] drm/amdgpu: Re-enable
On Fri, 3 Apr 2020 13:21:13 +0200
Peter Zijlstra wrote:
> On Fri, Apr 03, 2020 at 02:28:37PM +0900, Masami Hiramatsu wrote:
> > On Thu, 2 Apr 2020 16:13:08 +0200
> > Peter Zijlstra wrote:
>
> > > Masami, Boris, is there any semi-sane way we can have insn_is_fpu() ?
> > > While digging through v
68 matches
Mail list logo
