Ping? Xinhui can I get an rb for this?
Thanks,
Christian.
Am 16.03.20 um 14:22 schrieb Christian König:
The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.
To fix t
I wonder if it really fix anything with such small delay. but it should be no
harm anyway.
Reviewed-by: xinhui pan
> 2020年3月18日 15:51，Christian König 写道：
>
> Ping? Xinhui can I get an rb for this?
>
> Thanks,
> Christian.
>
> Am 16.03.20 um 14:22 schrieb Christian König:
>> The problem is t
The key point is that 10ms should be sufficient that either the move or
the update is finished.
One alternative which came to my mind would be to add the exclusive
fence as shared as well in this case.
This way we won't need to block at all.
Christian.
Am 18.03.20 um 09:00 schrieb Pan, Xinh
clang warns:
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
is used uninitialized whenever 'if' condition is
false [-Wsometimes-uninitialized]
if (offset == grbm_cntl || offset == grbm_idx)
^
drivers/gpu/drm/amd/a
Hi Christoph,
Thanks for your comments. I'm also replying here to your comments on the
previous series.
On Tuesday, March 17, 2020 10:28:35 AM EDT Christoph Hellwig wrote:
> Any reason drivers can't just use pci_map_rom insteadἅ which already
> does the right thing?
Some machines don't expose t
On Tue, Mar 17, 2020 at 09:34:33PM -0400, Mikel Rychliski wrote:
> I think the direct access to pdev->rom you suggest makes sense, especially
> because users of the pci_platform_rom() are exposed to the fact that it just
> calls ioremap().
>
> I decided against wrapping the iounmap() with a pci_
[AMD Official Use Only - Internal Distribution Only]
yes, adding excl fence again as shared one is more reliable
From: Christian König
Sent: Wednesday, March 18, 2020 4:03:14 PM
To: Pan, Xinhui
Cc: amd-gfx@lists.freedesktop.org ; Liu, Monk
Subject: Re: [PATCH]
On Tue, Mar 17, 2020 at 03:43:47PM -0700, Ralph Campbell wrote:
>> Obviously no driver cared for that so far. Once we have test cases
>> for that and thus testable code we can add code to fault it in from
>> hmm_vma_handle_pte.
>>
>
> I'm OK with the series. I think I would have been less confused
On Tue, Mar 17, 2020 at 6:24 PM Tristan Vroom wrote:
>
> I don't have a lot of experience reading kernel logs, so I apologize if I
> misread something, but it seems like I'm having some trouble with amdgpu in
> kernel 5.5.9.
>
> Here's the gist of the bug.
Does this patch fix the issue?
https:/
[AMD Official Use Only - Internal Distribution Only]
Submitting patch for review to issue smu cmd disable all features upon baco
entry sequence in arcturus.
This helps resolve issue with I2C controller not being disengaged properly on
GPU reset affecting RAS eeprom stability on re-entry
0001-
[AMD Public Use]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Clements,
John
Sent: Wednesday, March 18, 2020 10:11 AM
To: amd-gfx@lists.freedesktop.org ; Zhang,
Hawking
Subject: [PATCH ] amd/powerplay: arcturus baco reset disable all features
[AMD O
[AMD Public Use]
Submitting patch for review to protect RAS sysfs access' during a RAS event and
to clear the MMHub EDC registers early on in a BACO reset
0001-drm-amdgpu-protect-RAS-sysfs-during-GPU-reset.patch
Description: 0001-drm-amdgpu-protect-RAS-sysfs-during-GPU-reset.patch
_
On Tue, Mar 17, 2020 at 5:25 PM Nathan Chancellor
wrote:
>
> clang warns:
>
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
> is used uninitialized whenever 'if' condition is
> false [-Wsometimes-uninitialized]
> if (offset == grbm_cntl || offset == grbm_idx)
>
On Tue, 2020-03-17 at 17:25 -0700, Nathan Chancellor wrote:
> clang warns:
>
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
> is used uninitialized whenever 'if' condition is
> false [-Wsometimes-uninitialized]
> if (offset == grbm_cntl || offset == grbm_idx)
>
From: Hawking Zhang
[ Upstream commit f1c2cd3f8fb959123a9beba18c0e8112dcb2e137 ]
The ROMC_INDEX/DATA offset was changed to e4/e5 since
from smuio_v11 (vega20/arcturus).
Signed-off-by: Hawking Zhang
Tested-by: Candice Li
Reviewed-by: Candice Li
Signed-off-by: Alex Deucher
Signed-off-by: Sash
From: Martin Leung
[ Upstream commit d5349775c1726ce997b8eb4982cd85a01f1c8b42 ]
[why]
nv14 previously inherited soc bb from generic dcn 2, did not match
watermark values according to memory team
[how]
add nv14 specific soc bb: copy nv2 generic that it was
using from before, but changed num chan
clang warns:
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
is used uninitialized whenever 'if' condition is
false [-Wsometimes-uninitialized]
if (offset == grbm_cntl || offset == grbm_idx)
^
drivers/gpu/drm/amd/a
On Wed, Mar 18, 2020 at 1:28 PM Joe Perches wrote:
>
> On Tue, 2020-03-17 at 17:25 -0700, Nathan Chancellor wrote:
> > clang warns:
> >
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
> > is used uninitialized whenever 'if' condition is
> > false [-Wsometimes-uninitiali
fix typo for vcn2.5/jpeg2.5 idle check
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/jp
fix typo for vcn1 idle check
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 71f61af..09b0572 100644
--- a/drivers/gpu/drm/a
fix typo for vcn2/jpeg2 idle check
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v
Series are:
Reviewed-by: Leo Liu
-Original Message-
From: amd-gfx On Behalf Of James Zhu
Sent: March 18, 2020 5:15 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James
Subject: [PATCH 1/3] drm/amdgpu: fix typo for vcn1 idle check
fix typo for vcn1 idle check
Signed-off-by: James Zhu
[AMD Official Use Only - Internal Distribution Only]
ping
-Original Message-
From: Liu, Shaoyun
Sent: Tuesday, March 17, 2020 12:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for SRIOV guest
RLCG is enabled by host drive
[Why]
Mask bit IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE was missing for osssys v5.0.
[How]
IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE bit mask added for IH_CLK_CTRL register
on osssys v5_0_0 mask header file.
Change-Id: I71e5ea3a8e5b5077b21906c730bcf30faa678f10
Signed-off-by: Alex Sierra
---
drivers/
[Why]
IH implementation for arcturus has been added.
This reference has to be replace it for Arcutus ih ip.
[How]
Replace arcturus ih ip reference.
Change-Id: I5a12b329146fa7883586bb10d22077046a977701
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++--
1 file changed, 3
Arcturus has its own ih implementation. There's no need to support
this on vega10 ih anymore.
Change-Id: I29c843e0b12a458d2915129503c0ad852bcebc48
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/
[Why]
Arcturus uses osssys v4.2. This shares the same register map as
osssys v5.0.
[How]
Copy vega10_ih into new arcturus_ih source and header files.
Replace osssys include file with v5.0.0 on arcturus_ih.c source.
Change-Id: I5215f32f477adb6a30acef6e8add9f8e5bb041ef
Signed-off-by: Alex Sierra
-
Change-Id: I4701d12bff12052774562e666f95b5978097b5e4
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c2bbcdd9c875..2da7922c166d
[Why]
Same reason as commit "reroute VMC and UMD to IH ring 1" for vega10.
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, sinc
Renoir and Vega10 references removed. Both have their implementation
under vega10_ih
Change-Id: Id12a0228ea75dd7122c5ec264e5b38a00a79b45d
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/arcturus_ih.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/d
Replace function prefix name from vega10 to arcturus
Change-Id: Ic21713f2dda30a0bc28c7b525e20d5f1fcde96dd
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/arcturus_ih.c | 162 +++
drivers/gpu/drm/amd/amdgpu/arcturus_ih.h | 8 +-
2 files changed, 85 insertions(+), 8
I believe this should be squashed into Patch #8 or applied after patch
#8. Otherwise it creates a broken intermediate state where Arcturus
doesn't have any valid IH support. That said, it's probably less
critical because it only affects the case of direct (backdoor) firmware
loading.
Regards,
How much overlap is there between arcturus_ih and nave10_ih? Given that
they both use the same register map, could they share the same driver
code with only minor differences?
If they're almost the same, maybe you could rename navi10_ih.[ch] to
osssys_v5_0.[ch] and use it for both navi10 and a
[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per
register.
[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.
Change-Id: Iae28c22dd6e650f56286bfa0d9e002a8562fa855
Signed-off-by: Alex Sierra
---
driv
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Arcturus.
Change-Id: I8a6d9b89ea115fb51ff694493c88b8972d6248a5
Signed-off-by: Al
[AMD Public Use]
if we have been using vega10_ih all along for arcturus, presumably the register
map is close enough. I'd suggest either adding whatever new stuff you need to
vega10_ih.c or navi10_ih.c. No need to add a completely new one for a small
change like this.
Alex
__
On Mon, Mar 16, 2020 at 08:32:12PM +0100, Christoph Hellwig wrote:
> When acting on device private mappings a driver needs to know if the
> device (or other entity in case of kvmppc) actually owns this private
> mapping. This series adds an owner field and converts the migrate_vma
> code over to c
Hi Dave, Daniel,
Fixes for 5.6.
The following changes since commit 16b78f052d0129cd2998305480da6c4e3ac220a8:
Merge tag 'topic/mst-bw-check-fixes-for-airlied-2020-03-12-2' of
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes (2020-03-13 10:38:25
+1000)
are available in the Git reposi
On some EFI systems, the video BIOS is provided by the EFI firmware. The
boot stub code stores the physical address of the ROM image in pdev->rom.
Currently we attempt to access this pointer using phys_to_virt(), which
doesn't work with CONFIG_HIGHMEM.
On these systems, attempting to load the rad
On Tue, Mar 17, 2020 at 7:47 AM Colin King wrote:
>
> From: Colin Ian King
>
> There are spelling mistakes in pr_err messages and a comment. Fix these.
>
> Signed-off-by: Colin Ian King
The relevant code was recently dropped so no longer applies.
Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amd
On Tue, Mar 17, 2020 at 12:55 PM shaoyunl wrote:
>
> RLCG is enabled by host driver, no need to enable it in guest for none-PSP
> load path
>
> Change-Id: I2f313743bf3d492f06aaef07224da6eda3878a28
> Signed-off-by: shaoyunl
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
On Wed, Mar 18, 2020 at 5:08 PM Nick Desaulniers
wrote:
>
> On Wed, Mar 18, 2020 at 2:05 PM Nathan Chancellor
> wrote:
> >
> > clang warns:
> >
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:754:6: warning: variable 'shadow'
> > is used uninitialized whenever 'if' condition is
> > false [-Wsometimes-u
On Wed, Mar 18, 2020 at 11:10 PM Alex Deucher wrote:
>
> On Tue, Mar 17, 2020 at 7:47 AM Colin King wrote:
> >
> > From: Colin Ian King
> >
> > There are spelling mistakes in pr_err messages and a comment. Fix these.
> >
> > Signed-off-by: Colin Ian King
>
> The relevant code was recently dropp
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Liu, Shaoyun
Sent: Thursday, March 19, 2020 05:30
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Subject: RE: [PATCH] drm/amdgpu/sriov : Don't resume RLCG for S
[AMD Public Use]
Reviewed-by: Hawking Zhang
Regards,
Hawking
From: Clements, John
Sent: Thursday, March 19, 2020 00:43
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
Subject: [PATCH] drm/amdgpu: protect RAS sysfs during GPU reset
[AMD Public Use]
Submitting patch for review to protect RA
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