Acked-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Jack
> Zhang
> Sent: Thursday, January 2, 2020 3:44 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jack (Jian)
> Subject: [PATCH 1/2] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF
>
> Before, initialization
I am having this error with kernel version 4.19 amdgpu driver for a
polaris12 based GPU. What could be the problem? Any suggestions? Thanks.
*Full dmesg:*
[5.426009] [drm] amdgpu kernel modesetting enabled.
[5.430109] [drm] initializing kernel modesetting (POLARIS12
0x1002:0x6987 0x1787:0
Hello Christian,
I solved this problem weeks ago. The problem was, the system I use could
only give 256 MB address range but GPU was demanding more. Even if I give 4
GB, PCIe slot is only having 256 MB, nothing more. I put a empty area that
is between PCIe2 ( GPU was connected to this) and PCIe3
[AMD Official Use Only - Internal Distribution Only]
First you could check if the binary 'polaris12_smc.bin' is in your system:
/lib/firmware/../amdgpu/
If it's there, then does this happen after a warm reset?
Thanks.
From: amd-gfx On Behalf Of Yusuf
Altiparmak
Sent: Thursday, January 2, 2020
Hi Qu,
that problem is completely unrelated to amdgpu. See you thunderbold
bridge fails to assign the necessary I/O resources to the PCI device
long before amdgpu even loads:
From your dmesg:
Jan 01 07:22:22 thinkpad kernel: pci_bus :06: Allocating resources
Jan 01 07:22:22 thinkpad ker
Am 20.12.19 um 07:24 schrieb Alex Sierra:
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c9337836e7d4a430df3f16dcc8288
On 1/1/20 1:52 PM, Christian König wrote:
Am 19.12.19 um 13:01 schrieb Nirmoy:
Reviewed-by: Nirmoy Das
On 12/19/19 12:42 PM, Le Ma wrote:
This workaround does not affect other asics because amdgpu only need
expose
one gfx sched to user for now.
Change-Id: Ica92b8565a89899aebe0eba7b2b5a2515
Hello,
First you could check if the binary ‘polaris12_smc.bin’ is in your system:
> /lib/firmware/../amdgpu/
>
'polaris12_smc.bin' exists in my /lib/firmware/amdgpu folder. There are
also 18 other binaries which starts with 'polaris12_'.
If it’s there, then does this happen after a warm reset?
>
[AMD Official Use Only - Internal Distribution Only]
Added patch to resolve following issue where error counter detection was not
iterating over all UMC instances/channels.
Removed support for accessing UMC error counters via MMIO.
Thank you,
John Clements
0001-drm-amdgpu-resolve-bug-in-UMC-6-
[AMD Official Use Only - Internal Distribution Only]
UMC_REG_OFFSET(adev, ch_inst, umc_inst) and the function get_umc_reg_offset
actually do the same thing? I guess you just want to keep either of them, right?
Regards,
Hawking
From: Clements, John
Sent: Thursday, January 2, 2020 18:31
To: amd-
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kent Russell
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 2/4] drm/amdkfd: Remove unused variable
dqm->pipeline_m
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Kent Russell
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Friday, December 20, 2019 3:30 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 1/4] drm/amdkfd: Fix permissions of hang_hws
Reading fr
On 2019-12-02 4:47 p.m., Thomas Anderson wrote:
> For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
> "interesting" modes would be disabled, leaving only low-res or low
> framerate modes.
>
> This change lower
Am 02.01.20 um 10:47 schrieb Nirmoy:
On 1/1/20 1:52 PM, Christian König wrote:
Am 19.12.19 um 13:01 schrieb Nirmoy:
Reviewed-by: Nirmoy Das
On 12/19/19 12:42 PM, Le Ma wrote:
This workaround does not affect other asics because amdgpu only
need expose
one gfx sched to user for now.
Change-
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c9337836e7d4a430df3f16dcc82888e8018c
Signed-off-by: Alex Sierra
---
dri
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Alex Sierra
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 87
See one inline comment. Other than that:
Acked-by: Yong Zhao
On 2020-01-02 4:11 p.m., Alex Sierra wrote:
This can be used directly from amdgpu and amdkfd to invalidate
TLB through pasid.
It supports gmc v7, v8, v9 and v10.
Change-Id: I6563a8eba2e42d1a67fa2547156c20da41d1e490
Signed-off-by: Al
One comment inline.
On 2020-01-02 4:11 p.m., Alex Sierra wrote:
[Why]
Avoid reclaim filesystem while eviction lock is held called from
MMU notifier.
[How]
Setting PF_MEMALLOC_NOFS flags while eviction mutex is locked.
Using memalloc_nofs_save / memalloc_nofs_restore API.
Change-Id: I5531c93378
[AMD Public Use]
+#define UMC_REG_OFFSET(adev, ch_inst, umc_inst) ((adev)->umc.channel_offs *
(ch_inst) + UMC_6_INST_DIST*(umc_inst))
Coding style problem, miss blank space around last "*".
+for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++)
+{
Another codi
[AMD Public Use]
I think we can implement it by only updating amdgpu_umc_for_each_channel macro,
here is an example:
#define amdgpu_umc_for_each_channel(func)\
struct ras_err_data *err_data = \
(struct ras_err_data *)ras_error_status;\
uint
[AMD Public Use]
Hello GuChun/Hawking,
Thank you for your feedback, I have updated the patch with the following
amendments:
* Remove +#define UMC_REG_OFFSET (I forgot to remove this in original
patch, I prefer the function over the macro)
* Updated the coding style of the braces in the
[AMD Public Use]
Hello Tao,
That is an interesting suggestion, I agree that there is a little bit of
duplicate code with the same for loops being used in multiple functions.
My only concern with implementing the loops in a macro is code readability.
I’ll have to think about the trade off betw
[AMD Public Use]
Yes, John, that concern is cleared after I look into the code.
One more issue is, it's better that function get_umc_reg_offset is one static
inline function? With this problem fixed, the patch is: Reviewed-by: Guchun
Chen
uint32_t get_umc_reg_offset(struct amdgpu_device *adev
[AMD Public Use]
Hello GuChun,
Good point, it makes sense to make function static inline here, I think I shall
also rename the function from get_umc_reg_offset to get_umc_6_reg_offset.
Thank you,
John Clements
From: Chen, Guchun
Sent: Friday, January 3, 2020 11:09 AM
To: Clements, John ; Z
[AMD Official Use Only - Internal Distribution Only]
Hi Christian,
I wonder if you had a chance to look into this warning.
Please let me know if there's something we could help with.
Regards,
Alejandro
-Original Message-
From: Christian König
Sent: Thursday, December 12, 2019 2:52 AM
[Why]
According to DP spec, it should shift left 4 digits for NO_STOP_BIT
in REMOTE_I2C_READ message. Not 5 digits.
In current code, NO_STOP_BIT is always set to zero which means I2C
master is always generating a I2C stop at the end of each I2C write
transaction while handling REMOTE_I2C_READ side
Hello,
Still can't find a solution about this. Anyone can help me about this ?
Regards.
Yusuf Altıparmak , 2 Oca 2020 Per, 13:29 tarihinde
şunu yazdı:
> Hello,
>
> First you could check if the binary ‘polaris12_smc.bin’ is in your system:
>> /lib/firmware/../amdgpu/
>>
> 'polaris12_smc.bin' ex
[AMD Official Use Only - Internal Distribution Only]
Disabled PSP XGMI TA unload sequence as it currently causes GPU recovery to
fail.
Thank you,
John Clements
0001-drm-amdgpu-disable-PSP-XGMI-TA-unload-sequence.patch
Description: 0001-drm-amdgpu-disable-PSP-XGMI-TA-unload-sequence.patch
_
[AMD Official Use Only - Internal Distribution Only]
Added dedicated function to wait for PSP BL availability.
Increased driver wait time for PSP BL availability.
Thank you,
John Clements
0001-drm-amdgpu-added-function-to-wait-for-PSP-BL-availab.patch
Description: 0001-drm-amdgpu-added-functio
[AMD Official Use Only - Internal Distribution Only]
Enable path for GPU recovery in event of UMC uncorrectable error.
Thank you,
John Clements
0001-drm-amdgpu-removed-GFX-RAS-support-check-in-UMC-ECC-.patch
Description: 0001-drm-amdgpu-removed-GFX-RAS-support-check-in-UMC-ECC-.patch
__
[AMD Official Use Only - Internal Distribution Only]
- /* there might be handshake issue with hardware which needs delay
*/
- mdelay(20);
To be safety, I don't think we should remove this delay. And this actually do
nothing with the code refine in this patch.
Regards,
G
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