BACO reset mode strategy is determined by latter func when
calling amdgpu_ras_reset_gpu. So not to confuse audience, drop
it.
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
Am 12.12.19 um 17:06 schrieb Leo Liu:
Because VCN1.0 power management and DPG mode are managed together with
JPEG1.0 under both HW and FW, so separated them from general VCN code.
Also the multiple instances case got removed, since VCN1.0 HW just have
a single instance.
Signed-off-by: Leo Liu
-
On Wed, Dec 11, 2019 at 10:57:13PM +, Jason Gunthorpe wrote:
> On Thu, Dec 05, 2019 at 11:03:24AM -0500, Jerome Glisse wrote:
>
> > > struct mmu_notifier_mm (ie the mm->mmu_notifier_mm)
> > >-> mmn_mm
> > > struct mm_struct
> > >-> mm
> > > struct mmu_notifier (ie the user subscriptio
Because VCN1.0 power management and DPG mode are managed together with
JPEG1.0 under both HW and FW, so separated them from general VCN code.
Also the multiple instances case got removed, since VCN1.0 HW just have
a single instance.
v2: override work func with vcn1.0's own
Signed-off-by: Leo Liu
Any update about the Sensor Fusion HUB status? Thanks.
--
Luya Tshimbalanga
Fedora Design Team
Fedora Design Suite maintainer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Am 13.12.19 um 15:42 schrieb Leo Liu:
Because VCN1.0 power management and DPG mode are managed together with
JPEG1.0 under both HW and FW, so separated them from general VCN code.
Also the multiple instances case got removed, since VCN1.0 HW just have
a single instance.
v2: override work func wi
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: Chen, Guchun
Sent: Friday, December 13, 2019 3:53 AM
To: Zhang, Hawking ; Ma, Le ; Zhou1, Tao
; Deucher, Alexander ;
amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun
Subject: [
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher
From: Zhu, Changfeng
Sent: Thursday, December 12, 2019 10:24 PM
To: amd-gfx@lists.freedesktop.org ; Liang, Prike
; Liu, Aaron ; Huang, Ray
; Huang, Shimmer ; Deucher, Alexander
Cc: Zh
[Why]
Watermark value was expected to copy to SMU
within navi10_display_config_changed(). But
navi10_display_config_changed() is never called.
As a result, the watermark value is never
copied to SMU.
[How]
At end of navi10_set_watermarks_table,
copy watermark to SMU.
Signed-off-by: Zhan Liu
Sign
[Why]
Watermark value was expected to copy to SMU
within navi10_display_config_changed(). But
navi10_display_config_changed() is never called.
As a result, the watermark value is never
copied to SMU.
[How]
At end of navi10_set_watermarks_table,
copy watermark to SMU.
Signed-off-by: Zhan Liu
---
This prevents the NULL pointer access when there are fewer than 8 sdma
engines.
Change-Id: Iabae9bff7546b344720905d5d4a5cfc066a79d25
Signed-off-by: Yong Zhao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 64 ---
1 file changed, 42 insertions(+), 22 deletions(-)
diff --git
[Why]
SMU watermark table (WMTABLE) validity check is
missing on Renoir. This validity check is very
useful for checking whether WMTABLE is updated successfully.
[How]
Add SMU watermark validity check.
Signed-off-by: Zhan Liu
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12 ++--
1 f
This is to avoid queueing jobs to same CPU during XGMI hive reset
because there is a strict timeline for when the reset commands
must reach all the GPUs in the hive.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 inse
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 61
Use task barrier in XGMI hive to synchronize ASIC resets
across devices in XGMI hive.
v2: Retrun right away with a warning if no xgmi hive, update doc.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 +-
1 file changed, 31 insertio
In preparation for doing XGMI reset synchronization using task barrier.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 76 +-
2 files changed, 12 insertions(+), 6
It is used to synchronize N threads at a rendevouz point before execution
of critical code that has to be started by all the threads at approximatly
the same time.
v2: Remove mention of reset use case, improve doc.
Signed-off-by: Andrey Grodzovsky
---
include/drm/task_barrier.h | 107 ++
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Yong Zhao
Sent: Wednesday, December 11, 2019 6:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhao, Yong
Subject: [PATCH] drm/amdgpu: Add CU info print log
On Fri, Dec 13, 2019 at 11:11 AM Zhan Liu wrote:
>
> [Why]
> Watermark value was expected to copy to SMU
> within navi10_display_config_changed(). But
> navi10_display_config_changed() is never called.
> As a result, the watermark value is never
> copied to SMU.
>
> [How]
> At end of navi10_set_wa
Some typographical error nitpicks inline.
On 12/13/19 10:54 AM, Andrey Grodzovsky wrote:
> It is used to synchronize N threads at a rendevouz point before execution
rendezvous
> of critical code that has to be started by all the threads at approximatly
approximately
> the same time.
>
> v2: Remove
We already did this for older generations.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 64c53
We already did this for older generations.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 39 +++---
1 file changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
inde
Am 13.12.19 um 19:48 schrieb Alex Deucher:
We already did this for older generations.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König for the series.
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 39 +++---
1 file changed, 10 insertions(+), 29 deletions(-)
d
From: Mikita Lipski
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not
support virtual DPCD registers, but do support DSC.
The DSC caps can be read from the physical aux,
like in SST DSC. These hubs have many different
DEVICE_IDs. Add a new quirk to detect this case.
v2: Fix error when checking r
From: David Francis
This field on drm_dp_mst_branch was never filled
It is initialized to zero when the port is kzallocced.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.
v2: remember to decrement on port removal
v3: don't e
From: David Francis
Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.
This means that DRM drivers can make MST DPCD read/writes.
v2: Fix spacing
v3: Dump dpcd access on MST read/writes
v4: Fix call
From: David Francis
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate
From: David Francis
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FE
From: David Francis
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.
Use the cached dsc_aux field.
Reviewed-by: Wenjing Liu
Signed-off-by: David Francis
Signed-off-by: Mikita Lipski
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++-
1 file cha
From: Mikita Lipski
Adding a helper function to be called by
drivers outside of DRM to enable DSC on
the MST ports.
Function is called to recalculate VCPI allocation
if DSC is enabled and raise the DSC flag to enable.
In case of disabling DSC the flag is set to false
and recalculation of VCPI sl
From: Mikita Lipski
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if tha
From: Mikita Lipski
[why]
Need to calculate VCPI slots differently for DSC
to take in account current link rate, link count
and FEC.
[how]
Add helper to get pbn_div from dc_link
Cc: Harry Wentland
Cc: Lyude Paul
Signed-off-by: Mikita Lipski
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst
From: Mikita Lipski
[why]
Adding PBN attribute to drm_dp_vcpi_allocation structure to
keep track of how much bandwidth each Port requires.
Adding drm_dp_mst_atomic_check_bw_limit to verify that
state's bandwidth needs doesn't exceed available bandwidth.
The funtion is called in drm_dp_mst_atomic_
From: Mikita Lipski
This set of patches is a continuation of DSC enablement
patches for AMDGPU. This set enables DSC on MST. It also
contains implementation of both encoder and connector
atomic check routines.
These patches have been introduced in multiple
iterations to the mailing list before.
From: David Francis
Add drm_dp_mst_dsc_aux_for_port. To enable DSC, the DSC_ENABLED
register might have to be written on the leaf port's DPCD,
its parent's DPCD, or the MST manager's DPCD. This function
finds the correct aux for the job.
As part of this, add drm_dp_mst_is_virtual_dpcd. Virtual D
From: Mikita Lipski
[why]
For DSC case we cannot use topology manager's PBN divider
variable. The default divider does not take FEC into account.
Therefore the driver has to calculate its own divider based
on the link rate and lane count its handling, as it is hw specific.
[how]
Pass pbn_div as
From: Mikita Lipski
[why]
Whenever a connector on an MST network is changed or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stre
From: Mikita Lipski
[why]
drm_dp_mst_atomic_check_topology_state() should be renamed
to reflect more specific type of check. Since it is verifying
payload allocation limit it should be renamed into
drm_dp_mst_atomic_check_vcpi_alloc_limit()
Cc: Lyude Paul
Signed-off-by: Mikita Lipski
---
driv
From: David Francis
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Reviewed-by: Nicholas Kazlauskas
Signed-off-by
From: David Francis
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of b
From: David Francis
During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.
Use drm_dp_mst_dsc_aux_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.
Reviewed-by: Wenjing Liu
Signed-off-by: David Francis
Signed-of
From: Mikita Lipski
[why]
Since for DSC MST connector's PBN is claculated differently
due to compression, we have to recalculate both PBN and
VCPI slots for that connector.
[how]
The function iterates through all the active streams to
find, which have DSC enabled, then recalculates PBN for
it an
Series is
Reviewed-by: Harry Wentland
Harry
On 2019-12-11 10:45 a.m., roman...@amd.com wrote:
> From: Roman Li
>
> [Why]
> The earlier change: "check phy dpalt lane count config"
> uses link encoder registers not defined properly.
> That caused regression with mst-enabled display not
> lightin
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