Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Saturday, November 9, 2019 12:18 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH] drm/amdgpu/powerplay/smu7: fix AVFS handling with custom
> powerplay table
If smu_get_pptable_power_limit() is designed to be used internally, the second
argument "lock_needed" can be dropped.
Except that, the patch is reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of Matt
> Coffin
> Sent: Saturday, November 9, 2019 7:54 AM
> To: amd-gfx
Series is reviewed-by: Evan Quan
> -Original Message-
> From: zhengbin
> Sent: Monday, November 11, 2019 11:46 AM
> To: rex@amd.com; Quan, Evan ; Deucher,
> Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; airl...@linux.ie; dan...@ffwll.ch; amd-
> g...@lists.freedesktop.or
Series is reviewed-by: Evan Quan
> -Original Message-
> From: Matt Coffin
> Sent: Saturday, November 9, 2019 5:28 AM
> To: amd-gfx@lists.freedesktop.org; Quan, Evan
> Cc: Matt Coffin ; Deucher, Alexander
>
> Subject: [PATCH v2 0/3] navi10: Implement overdrive pp_od_clk_voltage
>
> [Wh
xgmi, ras, hdcp and dtm ta are actually separated ucode and
need to handled case by case to upload to psp.
We support the case that ta binary have one or multiple of
them built-in. As a result, the driver should check each ta
binariy's availablity before decide to upload them to psp.
In the termi
xgmi, ras, hdcp and dtm ta are actually separated ucode and
need to handled case by case to upload to psp.
We support the case that ta binary have one or multiple of
them built-in. As a result, the driver should check each ta
binariy's availablity before decide to upload them to psp.
In the termi
Reviewed-by: Le Ma
-Original Message-
From: Hawking Zhang
Sent: Monday, November 11, 2019 12:44 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Clements, John ; Ma, Le
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: avoid upload corrupted ta ucode to psp
xgmi, ras, hdcp
Hi Alex,
We have confirmed that the performance on Vega20 in the compute mode is
expected and doesn't need the similar change.
This is because that by default on Vega20 all the deep sleep features are
disabled, and ulv feature doesn't involve reducing mclk in Vega20
while it does in Vega10.
We t
Feng, Kenneth would like to recall the message, "[PATCH v2] drm/amd/powerplay:
dynamically disable ds and ulv for compute".
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Hi Andrey,
I don’t think your patch will help for this. As it will may call
kthread_should_park in drm_sched_cleanup_jobs first, and then call
kcl_kthread_park. And then it still has a race between the 2 threads.
Best wishes
Emily Deng
>-Original Message-
>From: Grodzovsky, Andrey
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