Thanks, Chris.
I double check all engines on gfx10 implement the emit_reg_write_reg_wait
callback.
You're right. I miss .emit_reg_write_reg_wait =
gfx_v10_0_ring_emit_reg_write_reg_wait, for gfx_v10_0_ring_funcs_kiq. So I add
it.
For sdma5, there is one amdgpu_ring_funs engine: amdgpu_ring_fun
From: changzhu
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where
status registers requiring HW to update have a 1 cycle delay, due
to the register update h
I kind of feeling the changes of VCE and UVD(of vega10_hwmgr.c) are not needed
as there is already lock protection in pp_dpm_powergate_uvd/vce.
Can you help to confirm that?
Regards,
Evan
> -Original Message-
> From: amd-gfx On Behalf Of Jesse
> Zhang
> Sent: Wednesday, November 6, 2019
Am 06.11.19 um 09:21 schrieb Zhu, Changfeng:
> From: changzhu
>
> The GRBM register interface is now capable of bursting 1 cycle per
> register wr->wr, wr->rd much faster than previous muticycle per
> transaction done interface. This has caused a problem where
> status registers requiring HW to u
Not an expert on the PCI IRQ stuff, but from what I know that looks
correct to me.
Only question I can see is why don't we use pci_alloc_irq_vectors()?
Alex probably needs to take a look.
Regards,
Christian.
Am 06.11.19 um 07:28 schrieb Deng, Emily:
Hi all,
Please help to review this.
Am 06.11.19 um 07:56 schrieb Jesse Zhang:
Unloading driver has call trace when unloading happens
2s after loading driver.
Since ring test are delayed after initializing driver,
it is possible that driver has been unloaded before or
while doing ring test.
Add mutex to prevent ring test and drive
Again that looks like the wrong approach to me.
How are the UVD/VCE power gate functions called here?
We most likely just forget to cancel/flush some background worker instead.
Regards,
Christian.
Am 06.11.19 um 10:13 schrieb Quan, Evan:
I kind of feeling the changes of VCE and UVD(of vega10_
Am 06.11.19 um 10:14 schrieb Pan Bian:
> The object fence is not set to NULL after its reference is dropped. As a
> result, its reference may be dropped again if error occurs after that,
> which may lead to a use after free bug. To avoid the issue, fence is
> explicitly set to NULL after dropping i
Am 06.11.19 um 10:53 schrieb Pan Bian:
> After dropping the reference of object fence in the loop, it should be
> set to NULL to protecting dropping its reference again outside the loop.
NAK, the actual bug is that we shouldn't drop the fence outside the loop
in the first place.
Just move the dm
Hi Christian,
We use " pci_alloc_irq_vectors " in amdgpu_irq_init. This patch use "
pci_free_irq_vectors " in amdgpu_irq_fini.
Hi Alex,
Could you help to review this?
Best wishes
Emily Deng
>-Original Message-
>From: Christian König
>Sent: Wednesday, November 6, 2019 5:32 PM
Hi Chris,
I move gfx_v10_0_check_fw_write_wait(adev);
to gfx_v10_0_init_microcode
BR,
Changfeng.
-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 6, 2019 5:26 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org;
Tuikov, Luben ; Huang, Ray ; Huang,
Shimmer
Subje
From: changzhu
The GRBM register interface is now capable of bursting 1 cycle per
register wr->wr, wr->rd much faster than previous muticycle per
transaction done interface. This has caused a problem where
status registers requiring HW to update have a 1 cycle delay, due
to the register update h
Am 06.11.19 um 11:52 schrieb Zhu, Changfeng:
> From: changzhu
>
> The GRBM register interface is now capable of bursting 1 cycle per
> register wr->wr, wr->rd much faster than previous muticycle per
> transaction done interface. This has caused a problem where
> status registers requiring HW to u
Am 06.11.19 um 12:35 schrieb Pan Bian:
> The reference to object fence is dropped at the end of the loop.
> However, it is dropped again outside the loop. The reference can be
> dropped immediately after calling dma_fence_wait() in the loop and
> thus the dropping operation outside the loop can be
Thanks, Chris.
BR,
Changfeng.
-Original Message-
From: Koenig, Christian
Sent: Wednesday, November 6, 2019 8:48 PM
To: Zhu, Changfeng ; amd-gfx@lists.freedesktop.org;
Tuikov, Luben ; Huang, Ray ; Huang,
Shimmer
Subject: Re: [PATCH 1/2] drm/amdgpu: add dummy read by engines for some G
-Original Message-
From: amd-gfx On Behalf Of Zhu,
Changfeng
Sent: Wednesday, November 6, 2019 8:50 PM
To: Koenig, Christian ;
amd-gfx@lists.freedesktop.org; Tuikov, Luben ; Huang, Ray
; Huang, Shimmer
Subject: RE: [PATCH 1/2] drm/amdgpu: add dummy read by engines for some GCVM
stat
vega20 only requires all devices be set to same pstate level for low
pstate and not high.
Change-Id: I399c84a47f6e24abca937ce950685c0c7f0e3279
Signed-off-by: Jonathan Kim
---
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drive
The current bare metal registers also get reset with gfxoff and GPU reset.
Alex
From: amd-gfx on behalf of Jiang, Jerry
(SW)
Sent: Tuesday, November 5, 2019 7:04 PM
To: Huang, JinHuiEric ; Alex Deucher
Cc: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] d
Ashkan,
Can you comment on the observation from Alex regarding
RLC_GPU_CLOCK_COUNT_LSB/MSB register with GFXoff and GPU reset?
If the statement from Alex is the real situation, we can simply our change.
Jerry
From: Deucher, Alexander
Sent: Wednesday, November 6, 2019 9:10 AM
To: Jiang, Jerry
Reviewed-by: Alex Deucher
From: Deng, Emily
Sent: Wednesday, November 6, 2019 5:09 AM
To: Koenig, Christian ; amd-gfx@lists.freedesktop.org
; Deucher, Alexander
Subject: RE: [PATCH] drm/amdgpu: Need to disable msix when unloading driver
Hi Christian,
We use
The reference to object fence is dropped at the end of the loop.
However, it is dropped again outside the loop. The reference can be
dropped immediately after calling dma_fence_wait() in the loop and
thus the dropping operation outside the loop can be removed.
Signed-off-by: Pan Bian
---
v2: fix
After dropping the reference of object fence in the loop, it should be
set to NULL to protecting dropping its reference again outside the loop.
Signed-off-by: Pan Bian
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu
The object fence is not set to NULL after its reference is dropped. As a
result, its reference may be dropped again if error occurs after that,
which may lead to a use after free bug. To avoid the issue, fence is
explicitly set to NULL after dropping its reference.
Signed-off-by: Pan Bian
---
dr
On Tue, Nov 05, 2019 at 01:23:46PM -0800, John Hubbard wrote:
> On 10/28/19 1:10 PM, Jason Gunthorpe wrote:
> > From: Jason Gunthorpe
> >
> > Now that we have KERNEL_HEADER_TEST all headers are generally compile
> > tested, so relying on makefile tricks to avoid compiling code that depends
> > on
On Mon, Aug 26, 2019 at 3:27 PM Andrzej Pietrasiewicz
wrote:
>
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
> Acked-by: Sam Ravnborg
> Reviewed-by: Emil Velikov
Acked-by: Sean Paul
> ---
> drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 6 +++
Ping?
On Tue, Oct 29, 2019 at 4:10 PM Alex Deucher wrote:
>
> To properly handle the option parsing ordering.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++
> drivers/gpu/drm/amd/amdgpu/soc15.c| 5 -
> 2 files changed, 6 insertions(+), 5 deleti
Ping?
On Wed, Oct 30, 2019 at 10:22 AM Alex Deucher wrote:
>
> Need to set the dte flag on this asic.
>
> Port the fix from amdgpu:
> 5cb818b861be114148e8dbeb4259698148019dd1
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/si_dpm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Ping?
On Wed, Oct 30, 2019 at 2:41 PM Alex Deucher wrote:
>
> Clarify some areas, clean up formatting, add section for
> unrecoverable error handling.
>
> Signed-off-by: Alex Deucher
> ---
> Documentation/gpu/amdgpu.rst| 35 ++
> drivers/gpu/drm/amd/amdgpu/amdgp
On Tue, Nov 5, 2019 at 4:34 AM Quan, Evan wrote:
>
> Enable pcie_replay_count interface support on Navi.
>
> Change-Id: Idc770663416ecf45aab8caa19de9cc99b619d2c3
> Signed-off-by: Evan Quan
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/nv.c | 14 ++
> .../amd/
Reviewed-by: Yong Zhao
On 2019-11-06 11:34 a.m., Alex Deucher wrote:
> Ping?
>
> On Tue, Oct 29, 2019 at 4:10 PM Alex Deucher wrote:
>> To properly handle the option parsing ordering.
>>
>> Signed-off-by: Alex Deucher
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++
>> drivers/gpu
Reviewed-by: Yong Zhao
On 2019-10-30 10:22 a.m., Alex Deucher wrote:
> Need to set the dte flag on this asic.
>
> Port the fix from amdgpu:
> 5cb818b861be114148e8dbeb4259698148019dd1
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/si_dpm.c | 1 +
> 1 file changed, 1 insertion(+)
See two wording comments inline. With that
Reviewed-by: Yong Zhao
On 2019-10-30 2:41 p.m., Alex Deucher wrote:
> Clarify some areas, clean up formatting, add section for
> unrecoverable error handling.
>
> Signed-off-by: Alex Deucher
> ---
> Documentation/gpu/amdgpu.rst| 35 +++
On Mon, Nov 4, 2019 at 8:54 AM yu kuai wrote:
>
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function
> ‘gfx_v8_0_gpu_early_init’:
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1713:6: warning: variable
> ‘mc_shared_chmap’ set but not used [-Wunused-but-
On Wed, Nov 6, 2019 at 4:39 AM Koenig, Christian
wrote:
>
> Am 06.11.19 um 10:14 schrieb Pan Bian:
> > The object fence is not set to NULL after its reference is dropped. As a
> > result, its reference may be dropped again if error occurs after that,
> > which may lead to a use after free bug. To
On Tue, Nov 5, 2019 at 6:10 PM Raul E Rangel wrote:
>
> drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces
> around initializer [-Werror=missing-braces]
> SmuMetrics_t metrics = {0};
> ^
>
> Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for getting dpm
> cloc
Explain fields like aper_base, agp_start etc. The definition
of those fields are confusing as they are from different view
(CPU or GPU). Add comments for easier understand.
Change-Id: I02c2a27cd0dbc205498eb86aafa722f2e0c25fe6
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |
On Wed, Nov 6, 2019 at 7:48 AM Koenig, Christian
wrote:
>
> Am 06.11.19 um 12:35 schrieb Pan Bian:
> > The reference to object fence is dropped at the end of the loop.
> > However, it is dropped again outside the loop. The reference can be
> > dropped immediately after calling dma_fence_wait() in
Explain fields like aper_base, agp_start etc. The definition
of those fields are confusing as they are from different view
(CPU or GPU). Add comments for easier understand.
Change-Id: I02c2a27cd0dbc205498eb86aafa722f2e0c25fe6
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |
I think you meant "This test tests" instead of "This tests tests" for your 2nd
comment but agreed on the consistent verb tenses.
Kent
-Original Message-
From: amd-gfx On Behalf Of Zhao, Yong
Sent: Wednesday, November 6, 2019 12:15 PM
To: amd-gfx@lists.freedesktop.org
Subject: Re: [PATC
On Wed, Nov 6, 2019 at 12:21 PM Zeng, Oak wrote:
>
> Explain fields like aper_base, agp_start etc. The definition
> of those fields are confusing as they are from different view
> (CPU or GPU). Add comments for easier understand.
>
> Change-Id: I02c2a27cd0dbc205498eb86aafa722f2e0c25fe6
> Signed-of
When the sched thread is parked we assume ring_mirror_list is
not accessed from here.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/scheduler/sched_main.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/d
This reverts commit 3cdf9bd0089723c468d5f6240e54d1afa52e9a04.
We will do a proper fix in next patch.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
b/dr
Problem:
During GPU reset we call the GPU scheduler to suspend it's
thread, those two functions in amdgpu also suspend and resume
the sceduler for their needs but this can collide with GPU
reset in progress and accidently restart a suspended thread
before time.
Fix:
Serialize with GPU reset.
Sign
Removes thread park/unpark hack from drm_sched_entity_fini and
by this fixes reactivation of scheduler thread while the thread
is supposed to be stopped.
Signed-off-by: Andrey Grodzovsky
Suggested-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 12
drivers/gpu/dr
[Why]
Before this patch, the smu_v11_0 power limit setting function
incorrectly always thought that TDPODLimit was 0 on navi10 cards. This
meant that between 5.3 and 5.4, when the power limit started being
obeyed, one could no longer set higher power limits for navi10.
[How]
Just as for vega20, we
Thanks Alex.
> AGP is also used for page tables in system memory.
I am not aware of this usage. I thought page table are all in frame buffer
today. Was this a use case in old asics?
Oak
-Original Message-
From: Alex Deucher
Sent: Wednesday, November 6, 2019 12:37 PM
To: Zeng, Oak
Cc
One comment.
With that fixed, this patch is: Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Thursday, November 7, 2019 12:35 AM
To: amd-gfx list
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: Improve RAS documentation
On 10/28/19 1:10 PM, Jason Gunthorpe wrote:
...
> include/linux/mmu_notifier.h | 98 +++
> mm/Kconfig | 1 +
> mm/mmu_notifier.c| 533 +--
> 3 files changed, 607 insertions(+), 25 deletions(-)
>
> diff --git a/include/linux/mmu_
Need to protect some DSC functions.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a1bdd51c50f
On Wed, Nov 06, 2019 at 04:23:21PM -0800, John Hubbard wrote:
> On 10/28/19 1:10 PM, Jason Gunthorpe wrote:
[...]
> > /**
> > * enum mmu_notifier_event - reason for the mmu notifier callback
> > @@ -32,6 +34,9 @@ struct mmu_notifier_range;
> > * access flags). User should soft dirty the page
Hi Dave, Daniel,
Fixes for 5.4.
The following changes since commit a99d8080aaf358d5d23581244e5da23b35e340b9:
Linux 5.4-rc6 (2019-11-03 14:07:26 -0800)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux tags/drm-fixes-5.4-2019-11-06
for you to fetch changes u
Reviewed-by: Evan Quan
> -Original Message-
> From: Kim, Jonathan
> Sent: Wednesday, November 6, 2019 10:04 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix ; Quan, Evan
> ; Strawbridge, Michael
> ; Kim, Jonathan ;
> Kim, Jonathan
> Subject: [PATCH] drm/amdgpu: fix vega20 ps
On 2019-10-30 20:17, Zhao, Yong wrote:
> release_mem won't be used at all on GFX9 and GFX10, so delete it.
Hawaii was GFXv7. So we're not using the release_mem packet on GFXv8
either. Why arbitrarily limit this change to GFXv9 and 10?
Regards,
Felix
>
> Change-Id: I13787a8a29b83e7516c582a740
On 2019-10-30 20:17, Zhao, Yong wrote:
> This is cleaner.
>
> Change-Id: I8cdecad387d8c547a088c6050f77385ee1135be1
> Signed-off-by: Yong Zhao
Reviewed-by: Felix Kuehling
> ---
> .../gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c | 19 +++
> 1 file changed, 7 insertions(+), 12 deleti
On 2019-10-30 20:17, Zhao, Yong wrote:
> The kernel queue functions for v9 and v10 are the same except
> pm_map_process_v* which have small difference, so they should be reused.
> This eliminates the need of reapplying several patches which were
> applied on v9 but not on v10, such as bigger GWS an
On 2019-11-05 18:18, Zhao, Yong wrote:
> The new code uses straightforward bit shifts and thus has better
> readability.
You're missing the MMAP-related code for mmio remapping. In
kfd_ioctl_alloc_memory_of_gpu:
/* MMIO is mapped through kfd device
* Generate a kfd mmap offse
move cancel_delayed_work_sync() to the begining
of amdgpu_device_fini() to cancel unfinished
works which are no longer needed.
Change-Id: I8831935b797c78b971aa7233697c36140374f1ac
Signed-off-by: Jesse Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/am
OD is not supported on Arcturus. Thus the
pp_od_clk_voltage sysfs interface is also not supported.
Change-Id: Ib70632a55a0980cf04c3432d43dbcf869cd1b4bf
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --gi
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