> -Original Message-
> From: Chen, Guchun
> Sent: 2019年9月17日 14:52
> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org;
> Zhang, Hawking
> Subject: RE: [PATCH] drm/amdgpu: replace DRM_ERROR with DRM_WARN in
> ras_reserve_bad_pages
>
>
>
> -Original Message-
> From: Zhou1, Tao
>
Yeah, that's fine.
Reviewed-by: Guchun Chen
-Original Message-
From: Zhou1, Tao
Sent: Tuesday, September 17, 2019 3:01 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org; Zhang,
Hawking
Subject: RE: [PATCH] drm/amdgpu: replace DRM_ERROR with DRM_WARN in
ras_reserve_bad_pages
>
From: Jiange Zhao
Add Navi12 PCI id support.
Signed-off-by: Jiange Zhao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 420888e941df..b52c7255e5e4 100644
---
On Mon, Sep 16, 2019 at 2:03 AM Xinpeng Liu wrote:
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/Makefile:70: *** missing
> `endif'. Stop.
> make[4]: *** [drivers/gpu/drm/amd/amdgpu] Error 2
>
> Signed-off-by: Xinpeng Liu
Tested-by: Nick Desaulniers
+ Mark
I think this was a result of the
Welcome^_^!
Mark Brown 于2019年9月17日周二 上午6:36写道：
> On Mon, Sep 16, 2019 at 11:12:03PM +0100, Mark Brown wrote:
> > On Mon, Sep 16, 2019 at 01:51:15PM -0700, Nick Desaulniers wrote:
> >
> > > + Mark
> > > I think this was a result of the resolved merge conflict. See the
> > > -next only commit tit
Am 17.09.19 um 08:16 schrieb Zhou1, Tao:
the bo pointer is reused for bad pages, initialize it in each loop
Signed-off-by: Tao Zhou
Reviewed-by: Christian König for the series.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/dr
Am 16.09.19 um 21:50 schrieb Alex Deucher:
We are reserving vram pages so they should be aligned to the
GPU page size.
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Am 16.09.19 um 22:06 schrieb Li, Sun peng (Leo):
On 2019-09-13 8:08 a.m., Christian König wrote:
[SNIP]
- if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT,
- PAGE_SIZE, &bo))
+ if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SI
Am 17.09.19 um 07:47 schrieb Jani Nikula:
On Mon, 16 Sep 2019, Marek Olšák wrote:
The purpose is to get rid of all PCI ID tables for all drivers in
userspace. (or at least stop updating them)
Mesa common code and modesetting will use this.
I'd think this would warrant a high level description
Am 17.09.19 um 08:22 schrieb Zhou1, Tao:
umc retired page belongs to vram and it should be aligned to gpu page
size
Signed-off-by: Tao Zhou
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
On Tue, Sep 17, 2019 at 10:12 AM Christian König
wrote:
>
> Am 17.09.19 um 07:47 schrieb Jani Nikula:
> > On Mon, 16 Sep 2019, Marek Olšák wrote:
> >> The purpose is to get rid of all PCI ID tables for all drivers in
> >> userspace. (or at least stop updating them)
> >>
> >> Mesa common code and
Am 17.09.19 um 10:17 schrieb Daniel Vetter:
> On Tue, Sep 17, 2019 at 10:12 AM Christian König
> wrote:
>> Am 17.09.19 um 07:47 schrieb Jani Nikula:
>>> On Mon, 16 Sep 2019, Marek Olšák wrote:
The purpose is to get rid of all PCI ID tables for all drivers in
userspace. (or at least stop
On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
> Am 17.09.19 um 10:17 schrieb Daniel Vetter:
>> On Tue, Sep 17, 2019 at 10:12 AM Christian König
>> wrote:
>>> Am 17.09.19 um 07:47 schrieb Jani Nikula:
On Mon, 16 Sep 2019, Marek Olšák wrote:
> The purpose is to get rid of all PCI ID t
On 2019-09-17 11:23 a.m., Michel Dänzer wrote:
> On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
>> Am 17.09.19 um 10:17 schrieb Daniel Vetter:
>>> On Tue, Sep 17, 2019 at 10:12 AM Christian König
>>> wrote:
Am 17.09.19 um 07:47 schrieb Jani Nikula:
> On Mon, 16 Sep 2019, Marek Olšák
Signed-off-by: Xiaojie Yuan
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index ab8c92a60fc
Reviewed-by: Evan Quan
-Original Message-
From: Yuan, Xiaojie
Sent: Tuesday, September 17, 2019 7:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH] drm/amdgpu/powerplay: add new mapping for APCC_DFLL feature
Si
Am 17.09.19 um 11:27 schrieb Michel Dänzer:
On 2019-09-17 11:23 a.m., Michel Dänzer wrote:
On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
Am 17.09.19 um 10:17 schrieb Daniel Vetter:
On Tue, Sep 17, 2019 at 10:12 AM Christian König
wrote:
Am 17.09.19 um 07:47 schrieb Jani Nikula:
On Mon,
On Tue, Sep 17, 2019 at 11:27 AM Michel Dänzer wrote:
>
> On 2019-09-17 11:23 a.m., Michel Dänzer wrote:
> > On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
> >> Am 17.09.19 um 10:17 schrieb Daniel Vetter:
> >>> On Tue, Sep 17, 2019 at 10:12 AM Christian König
> >>> wrote:
> Am 17.09.19 u
On Tue, Sep 10, 2019 at 01:54:48PM +0200, Michal Hocko wrote:
> On Fri 06-09-19 08:45:39, Tejun Heo wrote:
> > Hello, Daniel.
> >
> > On Fri, Sep 06, 2019 at 05:34:16PM +0200, Daniel Vetter wrote:
> > > > Hmm... what'd be the fundamental difference from slab or socket memory
> > > > which are hand
Applied. Thanks!
Alex
On Mon, Sep 2, 2019 at 4:16 PM Kai-Heng Feng
wrote:
>
> Laptops with AMD APU doesn't restore display backlight brightness after
> system resume.
>
> This issue started when DC was introduced.
>
> Let's use BL_CORE_SUSPENDRESUME so the backlight core calls
> update_status c
On 2019-09-17 1:20 p.m., Christian König wrote:
> Am 17.09.19 um 11:27 schrieb Michel Dänzer:
>> On 2019-09-17 11:23 a.m., Michel Dänzer wrote:
>>> On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
Am 17.09.19 um 10:17 schrieb Daniel Vetter:
> On Tue, Sep 17, 2019 at 10:12 AM Christian Kö
Reviewed-by: Kevin Wang
From: Yuan, Xiaojie
Sent: Tuesday, September 17, 2019 7:04 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Wang,
Kevin(Yang) ; Yuan, Xiaojie
Subject: [PATCH] drm/amdgpu/powerplay: add new mapping for APCC_DFLL fea
On Tue, Sep 17, 2019 at 3:12 AM wrote:
>
> From: Jiange Zhao
>
> Add Navi12 PCI id support.
>
> Signed-off-by: Jiange Zhao
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
We can remove this later as things get closer to launch.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index c6
We need to make sure the fifo is flushed before we ask the psp to
process the commands.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v12_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
Otherwise we may get stale data.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bc46a429b4dc..7991edf58123 100644
--- a/drivers/
Hello,
Applying this locally, the issue we were seeing with very high submit
times in high-end workloads seems largely gone. My methodology is to
measure the total time spent in DRM_IOCTL_AMDGPU_CS with `strace -T` for
the whole first scene of the Shadow of the Tomb Raider benchmark, and
divi
On 9/12/19 10:32 AM, Pierre-Loup A. Griffais wrote:
On 9/12/19 10:22 AM, Harry Wentland wrote:
On 2019-09-12 1:01 p.m., Kazlauskas, Nicholas wrote:
On 2019-09-12 12:44 p.m., Pierre-Loup A. Griffais wrote:
It's otherwise properly supported, just needs exposing to userspace.
Signed-off-by: Pi
For ASICs like renoir/arct, driver doesn't need to load mec2 jt.
when mec1 jt is loaded, mec2 jt will be loaded automatically
since the write is actaully broadcasted to both.
We need to more time to test other gfx9 asic. but for now we should
be able to draw conclusion that mec2 jt is not needed f
enable psp block for firmware loading and other security
feature setup.
Signed-off-by: Hawking Zhang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 284a6435bfdc..6faa1f625
drmVersion::name = amdgpu, radeon, intel, etc.
drmVersion::desc = vega10, vega12, vega20, ...
The common Mesa code will use name and desc to select the driver.
The AMD-specific Mesa code will use desc to identify the chip.
Mesa won't receive any PCI IDs for future chips.
Marek
On Tue, Sep 17,
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Wednesday, September 18, 2019 7:09 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Clements, John
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: do not init mec2 jt for renoir
For
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Zhang,
Hawking
Sent: Wednesday, September 18, 2019 7:09 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Clements, John
Cc: Zhang, Hawking
Subject: [PATCH] drm/amdgpu: add psp ip block for arct
enable p
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, September 18, 2019 4:21 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/amdgpu/psp: invalidate the hdp read cache before
reading the psp response
O
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Wednesday, September 18, 2019 4:21 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 1/2] drm/amdgpu/psp: flush HDP write fifo after submitting cmds
to the psp
We need t
Reviewed-by: Xiaojie Yuan
BR,
Xiaojie
> On Sep 18, 2019, at 3:52 AM, Alex Deucher wrote:
>
> We can remove this later as things get closer to launch.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
null ptr should be checked first to avoid null ptr access
Change-Id: I85c0a096eef77cad3a34265c995b1845451e04d0
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b
No need to define the same variables in each loop of the function.
Change-Id: Id8bbcc5a2ac87e9d31a72244345fde2d6bb99d42
Signed-off-by: Guchun Chen
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/dr
"control = &con->eeprom_control" is suggested, apart from this, the series is:
Reviewed-by: Tao Zhou
> -Original Message-
> From: Chen, Guchun
> Sent: 2019年9月18日 11:38
> To: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> ; Zhou1, Tao ;
> Grodzovsky, Andrey
> Cc: Chen, Guchun
> Subjec
On Tue, 17 Sep 2019 13:32:05 +0200
Daniel Vetter wrote:
> On Tue, Sep 17, 2019 at 11:27 AM Michel Dänzer wrote:
> >
> > On 2019-09-17 11:23 a.m., Michel Dänzer wrote:
> > > On 2019-09-17 10:23 a.m., Koenig, Christian wrote:
> > >> Am 17.09.19 um 10:17 schrieb Daniel Vetter:
> > >>> On Tue,
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