Correct the settings for auto mode and skip the unnecessary
settings for dcefclk and fclk.
Change-Id: I7e6ca75ce86b4d5cd44920a9fbc71b6f36ea3c49
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 60 +--
1 file changed, 54 insertions(+), 6 deletions(-)
d
Fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
Change-Id: Id9a373f8d8866b97450be0aef0ba19d0835d40d8
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 ++
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 1 +
2 files changed,
Reviewed-by: Evan Quan
> -Original Message-
> From: amd-gfx On Behalf Of
> Wang, Kevin(Yang)
> Sent: Wednesday, August 21, 2019 1:48 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xu, Feifei ; Wang, Kevin(Yang)
>
> Subject: [PATCH] drm/amd/powerpaly: fix navi series custom peak level
> va
Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu
Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_s
arcturus for sriov would use the unified mc base address
Change-Id: I3f10f88877aa38145a259b88c11a6aa2329f3fe2
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amd
arcturus for sriov would use the unified mc base address
Change-Id: I3f10f88877aa38145a259b88c11a6aa2329f3fe2
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amd
Since agp is not used for sriov, just disable it
Change-Id: I3aa9753499e2e74d982bb611214f94bd57bdcd9e
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 8
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgp
Series
Reviewed-by: Emily Deng
>-Original Message-
>From: amd-gfx On Behalf Of
>Frank.Min
>Sent: Wednesday, August 21, 2019 6:01 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Min, Frank
>Subject: [PATCH 1/2] drm/amdgpu: unity mc base address for arcturus
>
>arcturus for sriov would use th
Hi Evan,
this is know issue for me.
i think we should add update feature mask cached operation into
smu_feature_update_enable_state function.
Best Regards,
Kevin
On 8/21/19 5:24 PM, Evan Quan wrote:
> Need to update in cache feature enablement status after pp_feature
> settings. Another fix for
On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> >
> > Hi,
> >
> > > > Changing the order doesn't look hard. Patch attached (untested, have no
> > > > test hardware). But maybe I missed some detail ...
> > >
> > > I came up with
On 8/20/19 5:09 PM, Lyude Paul wrote:
> This should definitely be implemented as an atomic helper in
> drm_dp_mst_topology.c as well.
This is probably reasonable, most drivers would probably want this.
The issues with this in general are still:
(1) Knowing if you have a DSC in the MST network to
On 8/20/19 4:43 PM, Lyude Paul wrote:
> Some nitpicks below
>
> On Tue, 2019-08-20 at 15:11 -0400, David Francis wrote:
>> We were using drm helpers to convert a timing into its
>> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>>
>> These helpers
>> -Did not take DSC timings into a
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of sdma
engines with following logic:
(enab
On Wed, Aug 21, 2019 at 9:23 AM Yuan, Xiaojie wrote:
>
> navi1x has 2 sdma engines but commit
> "e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
> changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
> which causes amdgpu_irq_gpu_reset_resume_help
v2: set num_types based on num_instances
navi1x has 2 sdma engines but commit
"e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
changes the max number of sdma irq types (AMDGPU_SDMA_IRQ_LAST) from 2 to 8
which causes amdgpu_irq_gpu_reset_resume_helper() to recover irq of
Thanks Alex. I've sent out patch v2.
BR,
Xiaojie
> On Aug 21, 2019, at 9:30 PM, Alex Deucher wrote:
>
>> On Wed, Aug 21, 2019 at 9:23 AM Yuan, Xiaojie wrote:
>>
>> navi1x has 2 sdma engines but commit
>> "e7b58d03b678 drm/amdgpu: reorganize sdma v4 code to support more instances"
>> changes t
Am 21.08.19 um 12:00 schrieb Frank.Min:
Since agp is not used for sriov, just disable it
Change-Id: I3aa9753499e2e74d982bb611214f94bd57bd
Missing Signed-of-by line in the commit message.
With that fixed Reviewed-by: Christian König
for the series.
cd9e
---
drivers/gpu/drm/amd/amdgpu/am
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
allocated array as well as the reference counts of sync objects are leaked.
Signed-off-by: Nicolai Hähnle
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |
To upgrade performance in small bar mode, set sdma buffer function
ring and pte function ring to use different instance.
Change-Id: Ida6377914eb68a188f745e63409f344f0ce1a8c4
Signed-off-by: Gang Ba
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
Am 21.08.19 um 16:29 schrieb Haehnle, Nicolai:
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
allocated array as well as the reference counts of sync objects are leaked.
Signed-off-by: Nicolai Hähn
Am 21.08.19 um 16:32 schrieb Gang Ba:
To upgrade performance in small bar mode, set sdma buffer function
ring and pte function ring to use different instance.
NAK, we intentionally reserved the first paging queue here.
I wanted to revert that as well, but in this case you would need to
revert
On 2019-08-20 8:36 a.m., Jason Gunthorpe wrote:
> On Tue, Aug 20, 2019 at 11:45:54AM +1000, Stephen Rothwell wrote:
>> Hi all,
>>
>> On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap
>> wrote:
>>> On 8/19/19 2:18 AM, Stephen Rothwell wrote:
Hi all,
Changes since 20190816:
>
On Wed, Aug 21, 2019 at 03:34:12PM +, Kuehling, Felix wrote:
>
> On 2019-08-20 8:36 a.m., Jason Gunthorpe wrote:
> > On Tue, Aug 20, 2019 at 11:45:54AM +1000, Stephen Rothwell wrote:
> >> Hi all,
> >>
> >> On Mon, 19 Aug 2019 18:34:41 -0700 Randy Dunlap
> >> wrote:
> >>> On 8/19/19 2:18 AM,
On 2019-08-20 7:57 p.m., Nathan Chancellor wrote:
> When building arm32 allyesconfig:
>
> ld.lld: error: undefined symbol: __aeabi_uldivmod
referenced by dc_link.c
gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive
drivers/built-in.a
referenced by dc_link.c
>
[Why]
The only place where state->max_bpc is updated on the connector is
at the start of atomic check during drm_atomic_connector_check. It
isn't updated when adding the connectors to the atomic state after
the fact. It also doesn't necessarily reflect the right value when
called in amdgpu during m
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Yuan,
Xiaojie
Sent: Wednesday, August 21, 2019 9:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: alexdeuc...@gmail.com ; Xiao, Jack
; Yuan, Xiaojie ; Zhang, Hawking
Subject: [PATCH] drm/amdgpu/sdma5: fix numbe
On 8/20/19 3:12 PM, David Francis wrote:
> The first step in MST DSC is checking MST endpoints
> to see how DSC can be enabled
>
> Case 1: DP-to-DP peer device
> if the branch immediately upstream has
> - PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2)
> - DPCD rev. >= DP 1.4
> - Exactly one input
Reviewed-by: Leo Li
Thanks!
On 2019-08-21 12:57 p.m., Nicholas Kazlauskas wrote:
> [Why]
> The only place where state->max_bpc is updated on the connector is
> at the start of atomic check during drm_atomic_connector_check. It
> isn't updated when adding the connectors to the atomic state after
>
On Wed, 2019-08-21 at 12:27 +, Kazlauskas, Nicholas wrote:
> On 8/20/19 4:43 PM, Lyude Paul wrote:
> > Some nitpicks below
> >
> > On Tue, 2019-08-20 at 15:11 -0400, David Francis wrote:
> > > We were using drm helpers to convert a timing into its
> > > bandwidth, its bandwidth into pbn, and i
On Tue, Aug 06, 2019 at 08:15:37PM -0300, Jason Gunthorpe wrote:
> This series is already entangled with patches in the hmm & RDMA tree and
> will require some git topic branches for the RDMA ODP stuff. I intend for
> it to go through the hmm tree.
The RDMA related patches have been applied to t
Liu, Wenjing would like to recall the message, "[PATCH v2 11/14]
drm/amd/display: Validate DSC caps on MST endpoints".
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.
Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works
Signed-off-by: David Francis
Reviewed-by: Roman Li
Reviewed-by: Harry Wentland
Reviewed-by
We were using drm helpers to convert a timing into its
bandwidth, its bandwidth into pbn, and its pbn into timeslots
These helpers
-Did not take DSC timings into account
-Used the link rate and lane count of the link's aux device,
which are not the same as the link's current cap
-Did not take FEC
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Signed-off-by: David Francis
Reviewed-by: Nicholas Kazlauskas
---
With DSC, bpp can be a multiple of 1/16, so
drm_dp_calc_pbn_mode is insufficient.
Add drm_dp_calc_pbn_mode_dsc, a function which is
the same as drm_dp_calc_pbn_mode, but the bpp is
in units of 1/16.
Cc: Lyude Paul
Cc: Nicholas Kazlauskas
Signed-off-by: David Francis
---
drivers/gpu/drm/drm_dp
This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.
optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled
The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are n
This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.
This commit was accidentally promoted twice
Signed-off-by: David Francis
Reviewed-by: Roman Li
Reviewed-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 --
.../gpu/drm/amd
This patchset enables Display Stream Compression (DSC) on DP
connectors on Navi ASICs, both SST and DSC.
8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.
Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi pr
In create_stream_for_sink, check for SST DP connectors
Parse DSC caps to DC format, then, if DSC is supported,
compute the config
DSC hardware will be programmed by dc_commit_state
Tested-by: Mikita Lipski
Signed-off-by: David Francis
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/disp
This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.
This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timin
This field on drm_dp_mst_branch was never filled
Initialize it to zero when the list of ports is created.
When a port is added to the list, increment num_ports,
and when a port is removed from the list, decrement num_ports.
v2: remember to decrement on port removal
Signed-off-by: David Francis
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FEC and DSC support
Sto
During MST mode enumeration, if a new dc_sink is created,
populate it with dsc caps as appropriate.
Use drm_dp_mst_dsc_caps_for_port to get the raw caps,
then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.
Cc: Wenjing Liu
Cc: Nikola Cornij
Signed-off-by: David Francis
---
.../display/amd
Instead of having drm_dp_dpcd_read/write and
drm_dp_mst_dpcd_read/write as entry points into the
aux code, have drm_dp_dpcd_read/write handle both.
This means that DRM drivers can make MST DPCD read/writes.
Cc: Leo Li
Cc: Lyude Paul
Signed-off-by: David Francis
---
drivers/gpu/drm/drm_dp_aux_
Add drm_dp_mst_dsc_caps_for_port and drm_dp_mst_dsc_enable,
two helper functions for MST DSC
The former, given a port, returns the raw DPCD DSC caps off
that port.
The latter, given a port, enables or disables DSC on that port.
In both cases, the port given as input should be a leaf of
the MST t
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case.
Use the drm_dp_mst_dsc_enable helper.
Cc: Wenjing Liu
Cc: Nikola Cornij
Signed-off-by: David Francis
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c| 16 +++-
1 file changed, 15 insertions(+), 1 deletion
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of bandwidths possible for
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not chang
This patch set introduces EEPROM table to store RAS errors which rise
during run time so on next driver load those errors can be retrieved
and action taken on them (e.g. Reserve bad memory pages to disallow
their usage by the GPU).
First patch is HW independent EEPROM table manager while the next
Add RAS EEPROM table manager to eanble RAS errors to be stored
upon appearance and retrived on driver load.
v2: Fix some prints.
v3:
Fix checksum calculation.
Make table record and header structs packed to do correct byte value sum.
Fix record crossing EEPROM page boundry.
v4:
Fix byte sum val c
v2:
PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict
over I2C bus and engine disable thermal control access to
force SMU stop using the I2C bus until the issue is reslolved.
Expose and call vega20_is_smc_ram_running to skip locking when SMU
FW is not yet loaded.
v3:
Remove the p
v3: Merge CKSVII2C_IC regs into exsisting headers.
Signed-off-by: Andrey Grodzovsky
---
.../include/asic_reg/smuio/smuio_11_0_0_offset.h | 92
.../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h | 231 +
2 files changed, 323 insertions(+)
diff --git a/drivers/gpu/
Implement HW I2C enigne controller to be used by the RAS EEPROM
table manager. This is based on code from ATITOOLs.
v2:
Rename the file and all function prefixes to smu_v11_0_i2c
By Luben's observation always fill the TX fifo to full so
we don't have garbadge interpreted by the slave as valid dat
I know this looks like it could be a DRM helper, but
- That would require a DRM-generic way of knowing if a
connector supports DSC, and current precedent is that
DSC functionality is stored on a driver-specific basis
- This function, by necessity, locks global state. Other
hardware may b
Reviewed-by: Lyude Paul
Thanks!
On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> With DSC, bpp can be a multiple of 1/16, so
> drm_dp_calc_pbn_mode is insufficient.
>
> Add drm_dp_calc_pbn_mode_dsc, a function which is
> the same as drm_dp_calc_pbn_mode, but the bpp is
> in units of 1/1
On Wed, 2019-08-21 at 20:02 +, Francis, David wrote:
> I know this looks like it could be a DRM helper, but
> - That would require a DRM-generic way of knowing if a
>connector supports DSC, and current precedent is that
>DSC functionality is stored on a driver-specific basis
Don't mis
On Wed, 2019-08-21 at 16:01 -0400, David Francis wrote:
> Instead of having drm_dp_dpcd_read/write and
> drm_dp_mst_dpcd_read/write as entry points into the
> aux code, have drm_dp_dpcd_read/write handle both.
>
> This means that DRM drivers can make MST DPCD read/writes.
>
> Cc: Leo Li
> Cc: Ly
What branch does this patch series actually apply to? I've been trying to
apply this locally, but it doesn't appear to apply against drm-tip/drm-tip,
amdgpu-next/drm-next, or origin (e.g. kernel.org) /master. Is there any chance
we could have this go against drm-tip instead (and even better, split
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index c13c51af0b68..9d9004afc81b 100644
-
Flush via the ring works differently on CIK and requires a
special sequence.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik_sdma.c | 36
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c
b/drivers/g
force power control even if ATPX claims to not support it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
b/drivers/gpu/drm/amd/amdgpu/amdgp
Add quirks for handling PX/HG systems. In this case, add
a quirk for a weston dGPU that only seems to properly power
down using ATPX power control rather than HG (_PR3).
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 56 +---
1 file change
Flush via the ring works differently on CIK and requires a
special sequence.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 73 +++-
1 file changed, 45 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/
Ignore those. wrong directory.
Alex
From: Alex Deucher
Sent: Wednesday, August 21, 2019 6:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH 2/2] drm/radeon: use WAIT_REG_MEM special op for CP HDP flush
Flush via the ring works diff
This patch set adds initial power management support for
renoir.
Aaron Liu (15):
drm/amd/powerplay: add smu12_driver_if.h (v3)
drm/amdgpu/powerplay: add initial renoir_ppt.c for renoir (v3)
drm/amdgpu/powerplay: add smu_v12_0.c & smu_v12_0.h for renoir
drm/amdgpu/powerplay: add smu ip bloc
From: Aaron Liu
Add renoir_ppt and map ppsmc to amdgpu_smu.h
v2: squash in ppsmc updates (Alex)
v3: squash in driver_if updates (Alex)
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 44 +++
drivers/gpu/drm
From: Huang Rui
Renoir DPM is not functional so far, we skip it for the comment.
Will revert this patch once SMU 12 is functional.
Signed-off-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +
1 file changed, 9 in
From: Leo Liu
Thus VCN can be powered up for normal operations
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: Evan Quan
Reviewed-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8 ++--
drivers/gpu/dr
From: Huang Rui
All apu series need powerup sdma and vcn via smu messages.
Signed-off-by: Huang Rui
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/po
From: Aaron Liu
1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir
2.adjust smu ip block ahead of gfx&sdma ip block
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c| 4 +--
drivers/gpu/drm/am
This is the SMU v12 driver message interface.
v2: squash in updates
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/inc/smu_v12_0_ppsmc.h | 106 ++
1 file changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
diff --git a/dri
From: Aaron Liu
add smu_v12_0.c & smu_v12_0.h for renoir
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 37
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 170 ++
2 files changed, 207 inse
From: Aaron Liu
This patch updates gfxoff feature.
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 5 +++
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 -
drivers/
From: Aaron Liu
add swSMU [smu_v12_0] for renoir
v2: whitespace fixes (Alex)
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c| 2 ++
drivers/gpu/drm/amd/powerplay/Makefile| 2 +-
drivers/gpu/drm/amd/powe
From: Aaron Liu
This patch adds smu12_driver_if.h
v2: squash in updates (Alex)
v3: more updates (Alex)
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
.../drm/amd/powerplay/inc/smu12_driver_if.h | 217 ++
1 file chang
From: Prike Liang
Enable mmhub midle grain and light sleep clock gating.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/s
From: Aaron Liu
This patch adds add DPMCLOCKS table implementation
Rename smu_populate_smc_pptable to smu_populate_smc_tables
Signed-off-by: Aaron Liu
Reviewed-by: Kenneth Feng
Reviewed-by: Evan Quan
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdg
From: Prike Liang
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 2bd7ada80
From: Prike Liang
Enable IH clock gating during IH block initialized.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15
From: Aaron Liu
This interface support SMU_MSG_GetDriverIfVersion
and SMU_MSG_GetSmuVersion checking.
v2: squash in driver_if changes (Alex)
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c |
From: Prike Liang
Add support for SDMA clockgating on RN.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/
From: Prike Liang
Enable HDP light sleep clock gating.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/g
From: Prike Liang
Enable BIF light sleep clock gating.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/g
From: Aaron Liu
add and map smu tables for renoir
Signed-off-by: Aaron Liu
Reviewed-by: Kenneth Feng
Reviewed-by: Evan Quan
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 2 ++
drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 27
From: Prike Liang
Enable DF clock gating during DF IP early init.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
From: Aaron Liu
For renoir, it should use mmSMUIO_GFX_MISC_CNTL to check
gfxoff status. For the first time to enter gfxoff status,
it maybe takes about one second more. So just set the max
timeout to 5s.
GFXOFF_STATUS(bits 2:1)'s description is below:
0=GFXOFF(default).
1=Transition out of GFX S
From: Prike Liang
Enable VCN middle grain clock gating.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/
From: Prike Liang
Enable rom light sleep clock gating.
Reviewed-by: Alex Deucher
Signed-off-by: Prike Liang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/g
From: Prike Liang
To avoid the dpm frequence range get failed when DPM enabled and it
will be enabled later once handle well the feature bit map struct.
Signed-off-by: Prike Liang
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 f
From: Aaron Liu
Initialize smu tables for renoir:
WATERMARKS/DPMCLOCKS/SMU_METRICS
Signed-off-by: Aaron Liu
Reviewed-by: Kenneth Feng
Reviewed-by: Evan Quan
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 16 +++
drivers/gpu/drm/
From: Aaron Liu
Check whether the message mapping is valid
Signed-off-by: Aaron Liu
Reviewed-by: Kenneth Feng
Reviewed-by: Evan Quan
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 5 +
drivers/gpu/drm/amd/powerplay/renoir_ppt.c
From: Aaron Liu
add set_gfx_cgpg implement
v2: check if using sw_smu (Alex)
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 3
From: Huang Rui
We still encouter the CP hang while gfxoff is enabled under X start.
So disable it for the moment till this issue is addressed.
Signed-off-by: Huang Rui
Reviewed-by: Aaron Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1
From: Aaron Liu
This reverts commit dfb2c6ee8bec5914d47a4b75f73eff731bb937ae.
Signed-off-by: Aaron Liu
Acked-by: changzhu
Acked-by: Chen Gong
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driver
From: Aaron Liu
This patch updates gc/sdma goldensetting for renoir
Signed-off-by: Aaron Liu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
2 files changed, 5 insertions(+), 6 deletio
From: Thong Thai
This will enable indirect SRAM loading for VCN DPG mode initialization.
Signed-off-by: Thong Thai
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/am
From: Prike Liang
enable the dpm feature for the renoir.
Signed-off-by: Prike Liang
Reviewed-by: Aaron Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drive
From: Thong Thai
This reverts commit 444a0fea5107e9ad7e3cbbafed78678489e31713.
We are ready to enable it now.
Signed-off-by: Thong Thai
Reviewed-by: Leo Liu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +++
From: Prike Liang
Enable sdma middle grain and light sleep clock gating.
Signed-off-by: Prike Liang
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/s
From: Prike Liang
Enable SDMA PG flag during device ip early init.
Reviewed-by: Alex Deucher
Signed-off-by: Prike Liang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b
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