before this patch, we have 4 apis to manage smu feature bits.
the patch add a new one in them, but it is not add any feature in smu.
before your patch:
smu_feature_is_enabled and smu_feature_set_enabled is pair of functions,
after your patch:
smu_feature_is_enabled and smu_enable_smc_feature is pa
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
V2: a better naming
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/a
I cannot get your point. What do you mean "pairs of functions"?
Yes, this patch does not bring real changes.
But this helps for future maintain and fit common logic.
1. As in my previous patch("drm/amd/powerplay: correct Navi10 VCN powergate
control" ), "smu_feature_set_enabled(smu, SMU_FEATURE_V
for better clarification
Change-Id: I245d760d5f9d64eb10b137d5ce375ef52a4d873a
Signed-off-by: Le Ma
---
tests/amdgpu/basic_tests.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 938106e..fa0f568 1
Patch is Reviewed-by: Flora Cui
Could you apply the similar change to draw test?
-Original Message-
From: amd-gfx On Behalf Of Le Ma
Sent: Monday, July 22, 2019 4:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le ; Cui, Flora
Subject: [PATCH libdrm 1/1] tests/amdgpu: divide dispatch te
in fact, the smu feature bitmap is cached of smc firmware hardware bitmap,
most of time, when driver want to check whether enable is available.
the driver should talk with smc to check featue enabled.
i think it is very low efficiency.
so the driver will provide a bitmap structure to store hardw
Thanks Flora. No need change for draw test since it only runs gfx ring test.
Regards,
Ma Le
-Original Message-
From: Cui, Flora
Sent: Monday, July 22, 2019 4:07 PM
To: Ma, Le ; amd-gfx@lists.freedesktop.org
Cc: Ma, Le
Subject: RE: [PATCH libdrm 1/1] tests/amdgpu: divide dispatch test i
for better clarification
v2: accordingly change dispatch_test caller in gpu_reset test
Change-Id: I245d760d5f9d64eb10b137d5ce375ef52a4d873a
Signed-off-by: Le Ma
Reviewed-by: Flora Cui
---
tests/amdgpu/basic_tests.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
dif
The implementation of SMU_MSG_PowerDown[UP]Vcn (in smu fw) already includes the
identical hardware enablement/disablement of SMU_FEATURE_VCN_PG_BIT.
Thus after that, only update the bitmask is enough. This is done on purpose.
Regards,
Evan
From: Wang, Kevin(Yang)
Sent: Monday, July 22, 2019 4:11
We need to check the context number instead if the previous sequence to detect
an error and if an error is detected we need to drop the reference to the
current fence or otherwise would leak it.
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_syncobj.c | 10 +-
1 file changed, 5 i
On 22/07/2019 15:59, Christian König wrote:
We need to check the context number instead if the previous sequence to detect
an error and if an error is detected we need to drop the reference to the
current fence or otherwise would leak it.
Signed-off-by: Christian König
Fixes: 27b575a9aa2f ("d
it seems this feature is specific feature on some asic in smc firmware.
why not create a specific function to handle this case,
the apis of smu_feature_is_enabled and smu_feature_set_enabled is public api
for all smu asic.
how can you be sure that message must have the same logic on other asics
Am 22.07.19 um 15:16 schrieb Lionel Landwerlin:
On 22/07/2019 15:59, Christian König wrote:
We need to check the context number instead if the previous sequence
to detect
an error and if an error is detected we need to drop the reference to
the
current fence or otherwise would leak it.
Signed
On 22/07/2019 16:21, Christian König wrote:
Am 22.07.19 um 15:16 schrieb Lionel Landwerlin:
On 22/07/2019 15:59, Christian König wrote:
We need to check the context number instead if the previous sequence
to detect
an error and if an error is detected we need to drop the reference
to the
curr
This one properly in purpose , The mqd init for CP and COMPUTE will
have the same routine .
Regard
sshaoyun.liu
On 2019-07-21 6:59 p.m., Gustavo A. R. Silva wrote:
> Add missing break statement in order to prevent the code from falling
> through to case KFD_MQD_TYPE_COMPUTE.
>
> This bug was
Units in the GDS block default to allowing all VMIDs access to all
entries. Disable shader access to the GDS, GWS, and OA blocks from all
compute and gfx VMIDs by default. For compute, HWS firmware will set
up the access bits for the appropriate VMID when a compute queue
requires access to these bl
We need to add a /*fall through */ comment then.
Alex
From: Liu, Shaoyun
Sent: Monday, July 22, 2019 11:14 AM
To: Gustavo A. R. Silva ; Cox, Philip
; Oded Gabbay ; Deucher, Alexander
; Koenig, Christian ;
Zhou, David(ChunMing) ; David Airlie ;
Daniel Vetter
C
On 7/22/19 10:58 AM, Deucher, Alexander wrote:
> We need to add a /*fall through */ comment then.
>
It might be better to remove the call to pr_debug() in KFD_MQD_TYPE_CP:
case KFD_MQD_TYPE_CP:
case KFD_MQD_TYPE_COMPUTE:
pr_debug("%s@%i\n", __func__, __LINE__);
+Eric Biederman too, who might be able to Ack this...
On Mon, Jul 15, 2019 at 06:00:04PM +0200, Andrey Konovalov wrote:
> On Mon, Jun 24, 2019 at 7:50 PM Catalin Marinas
> wrote:
> >
> > On Mon, Jun 24, 2019 at 04:32:52PM +0200, Andrey Konovalov wrote:
> > > This patch is a part of a series that
From: Emil Velikov
As mentioned by Christian, for drivers which support only primary nodes
this changes the returned error from -EACCES into -EOPNOTSUPP/-ENOSYS.
For others, this check in particular will be a noop. So let's remove it
as suggested by Christian.
Cc: Alex Deucher
Cc: Christian Kö
That sounds good to me .
Regards
shaoyun.liu
On 2019-07-22 12:13 p.m., Gustavo A. R. Silva wrote:
>
> On 7/22/19 10:58 AM, Deucher, Alexander wrote:
>> We need to add a /*fall through */ comment then.
>>
> It might be better to remove the call to pr_debug() in KFD_MQD_TYPE_CP:
>
> case KFD
In preparation to enabling -Wimplicit-fallthrough, this patch silences
the following warning:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c: In function
‘mqd_manager_init_v10’:
./include/linux/dynamic_debug.h:122:52: warning: this statement may fall
through [-Wimplicit-fallthrough=]
Reviewed-by: shaoyunl
On 2019-07-22 1:47 p.m., Gustavo A. R. Silva wrote:
> In preparation to enabling -Wimplicit-fallthrough, this patch silences
> the following warning:
>
> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.c: In function
> ‘mqd_manager_init_v10’:
> ./include/linux/dyn
Am 22.07.19 um 17:34 schrieb Greathouse, Joseph:
Units in the GDS block default to allowing all VMIDs access to all
entries. Disable shader access to the GDS, GWS, and OA blocks from all
compute and gfx VMIDs by default. For compute, HWS firmware will set
up the access bits for the appropriate VM
On Sun, Jul 21, 2019 at 6:12 PM Gustavo A. R. Silva
wrote:
>
> Add missing break statement in order to prevent the code from falling
> through to case CHIP_NAVI10.
>
> This bug was found thanks to the ongoing efforts to enable
> -Wimplicit-fallthrough.
>
> Fixes: 14328aa58ce5 ("drm/amdkfd: Add nav
On Sun, Jul 21, 2019 at 6:39 PM Gustavo A. R. Silva
wrote:
>
> Add missing break statement in order to prevent the code from falling
> through to case AMDGPU_IRQ_STATE_ENABLE.
>
> This bug was found thanks to the ongoing efforts to enable
> -Wimplicit-fallthrough.
>
> Fixes: a644d85a5cd4 ("drm/amd
Am 22.07.19 um 19:40 schrieb Emil Velikov:
> From: Emil Velikov
>
> As mentioned by Christian, for drivers which support only primary nodes
> this changes the returned error from -EACCES into -EOPNOTSUPP/-ENOSYS.
>
> For others, this check in particular will be a noop. So let's remove it
> as sugg
Applied. Thanks!
Alex
On Mon, Jul 22, 2019 at 2:14 PM Liu, Shaoyun wrote:
>
> Reviewed-by: shaoyunl
>
> On 2019-07-22 1:47 p.m., Gustavo A. R. Silva wrote:
> > In preparation to enabling -Wimplicit-fallthrough, this patch silences
> > the following warning:
> >
> > drivers/gpu/drm/amd/amdgpu/
On 7/22/19 2:12 PM, Alex Deucher wrote:
> On Sun, Jul 21, 2019 at 6:39 PM Gustavo A. R. Silva
> wrote:
>>
>> Add missing break statement in order to prevent the code from falling
>> through to case AMDGPU_IRQ_STATE_ENABLE.
>>
>> This bug was found thanks to the ongoing efforts to enable
>> -Wimp
On 7/22/19 2:10 PM, Alex Deucher wrote:
> On Sun, Jul 21, 2019 at 6:12 PM Gustavo A. R. Silva
> wrote:
>>
>> Add missing break statement in order to prevent the code from falling
>> through to case CHIP_NAVI10.
>>
>> This bug was found thanks to the ongoing efforts to enable
>> -Wimplicit-fallt
On Mon, Jul 22, 2019 at 3:19 PM Gustavo A. R. Silva
wrote:
>
>
>
> On 7/22/19 2:10 PM, Alex Deucher wrote:
> > On Sun, Jul 21, 2019 at 6:12 PM Gustavo A. R. Silva
> > wrote:
> >>
> >> Add missing break statement in order to prevent the code from falling
> >> through to case CHIP_NAVI10.
> >>
> >>
On 7/22/19 2:45 PM, Alex Deucher wrote:
>>
>> By the way, Alex, I'm planning to add these fixes to my tree. I want
>> to send a pull-request to Linus for v5.3-rc2 this afternoon. We want
>> to have the -Wimplicit-fallthrough option globally enabled in v5.3,
>> and these are some of the last fal
arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
on SSE2 to support emitting double precision floating point instructions
rather than calls to non-existent (usually available from gcc_s or
compiler_rt) floatin
smu_feature_set_enabled() is refreshed to update the stored copy only because
there do has the use case.
Another example is vega20_set_ppfeature_status() which needs also updating the
stored feature masks only. That is missing now and is a bug.
I have noticed that for a while and do not have time
ASIC hang randomly.
Signed-off-by: Flora Cui
---
tests/amdgpu/amdgpu_test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 6f1e372..a4ce8ce 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
Reviewed-by: Feifei Xu
-Original Message-
From: amd-gfx On Behalf Of Cui, Flora
Sent: Tuesday, July 23, 2019 10:03 AM
To: amd-gfx@lists.freedesktop.org
Cc: Cui, Flora
Subject: [PATCH libdrm] tests/amdgpu: disable reset test for now
ASIC hang randomly.
Signed-off-by: Flora Cui
---
In case we add bad pages during gpu reset. Bad pages might not been
reserved in time.
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
ind
On Thu, Jul 11, 2019 at 01:26:39PM +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Shawn Guo
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On Thu, Jul 11, 2019 at 01:26:40PM +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Shawn Guo
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