Am 20.07.19 um 01:46 schrieb Greathouse, Joseph:
> Units in the GDS block default to allowing all VMIDs access
> to all entries. Disable shader access to the GDS, GWS, and OA
> blocks from all compute and gfx VMIDs by default. For compute,
> HWS firmware will set up the access bits for the appropri
Add missing break statement in order to prevent the code from falling
through to case CHIP_NAVI10.
This bug was found thanks to the ongoing efforts to enable
-Wimplicit-fallthrough.
Fixes: 14328aa58ce5 ("drm/amdkfd: Add navi10 support to amdkfd. (v3)")
Cc: sta...@vger.kernel.org
Signed-off-by: Gu
Add missing break statement in order to prevent the code from falling
through to case AMDGPU_IRQ_STATE_ENABLE.
This bug was found thanks to the ongoing efforts to enable
-Wimplicit-fallthrough.
Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)")
Cc: sta...@vger.kernel.org
Signed-
Add missing break statement in order to prevent the code from falling
through to case KFD_MQD_TYPE_COMPUTE.
This bug was found thanks to the ongoing efforts to enable
-Wimplicit-fallthrough.
Fixes: 14328aa58ce5 ("drm/amdkfd: Add navi10 support to amdkfd. (v3)")
Cc: sta...@vger.kernel.org
Signed-o
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_int
Commonly used for VCN powergate status retrieval for SW SMU.
Change-Id: Ibc2f498848f728eb7727cd3fa889e91a2b09d07b
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/
Enable VCN powergate status report on Raven.
Change-Id: I60c793f8185ce6799b40a0cabd97d9c9fe5483fd
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
b/drive
VCN should be used for Vega20 later ASICs.
Evan Quan (5):
drm/amd/powerplay: add new sensor type for VCN powergate status
drm/amd/powerplay: support VCN powergate status retrieval on Raven
drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
drm/amd/powerplay: correct Navi1
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.
Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 --
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.
Change-Id: Icc53d6fa176c48f0fc5348e79b8a5010357867eb
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +-
1 file changed, 36 insertions(+), 20 deletions(-)
diff --
I just suggest that we use AMDGPU_PP_SENSOR_VCN_POWER_STATE instead of
AMDGPU_PP_SENSOR_VCN_POWER,
since we gets the state of power on/off, not the real VCN power value.
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan
Quan
Sent: Monday, July 22, 2019 11:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 2/5] drm/amd/powerplay: support V
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan
Quan
Sent: Monday, July 22, 2019 11:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 3/5] drm/amd/powerplay: support V
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan
Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 4/5] drm/amd/powerplay: correct N
Reviewed-by: Kenneth Feng
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan
Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH 5/5] drm/amd/powerplay: correct U
you should check return value in smu anytime.
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
Reviewed-by: Kevin Wang
Best Regards,
kevin
From: amd-gfx on behalf of Feng,
Kenneth
Sent: Monday, July 22, 2019 12:28:40 PM
To: Quan, Ev
It does more than updating the bitmask. In fact it enables also the
feature. That's confusing. As for this, a new API is added for the
feature enablement job. And smu_feature_set_enabled is updated to
setting the bitmask only(as smu_feature_set_supported).
Change-Id: I758e4461be34c0fcbdf19448e3418
That does not really matters. The API will still return success even on
smu_feature_set_enabled failure. It does not care about smu_feature_set_enabled
failure.
But it helps me find another issue(about the naming smu_feature_set_enabled). I
just sent out a patch to address that.
Regards,
Evan
F
It's not necessary in the current code,
but if you update the implementation of the API one day,
your code won't look so strong.
I don't recommend it.
Best Regards,
Kevin
From: Quan, Evan
Sent: Monday, July 22, 2019 2:42:26 PM
To: Wang, Kevin(Yang) ; Feng, Kenne
Good point. It was following old naming style.
But I think we can make some changes to make it more understandable.
Let me address this in the V2 version.
Regards,
Evan
> -Original Message-
> From: Feng, Kenneth
> Sent: Monday, July 22, 2019 12:27 PM
> To: Quan, Evan ; amd-gfx@lists.freed
Am 20.07.19 um 00:02 schrieb Kuehling, Felix:
This memory allocation flag will be used to indicate BOs containing
sensitive data that should not be leaked to other processes.
Just a nit pick, but I would reorder the series and make patch #3 the
first and #2 the last one.
Just to have a clean
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