Hi
Am 18.04.19 um 00:16 schrieb Kuehling, Felix:
> Adding dri-devel
>
> On 2019-04-17 6:15 p.m., Yang, Philip wrote:
>> After patch "drm: Use the same mmap-range offset and size for GEM and
>> TTM", application failed to create bo of system memory because drm
>> mmap_range size decrease to 64GB f
Quoting Thomas Zimmermann (2019-04-18 08:29:39)
> Hi
>
> Am 18.04.19 um 00:16 schrieb Kuehling, Felix:
> > Adding dri-devel
> >
> > On 2019-04-17 6:15 p.m., Yang, Philip wrote:
> >> After patch "drm: Use the same mmap-range offset and size for GEM and
> >> TTM", application failed to create bo of
On Wed, Apr 17, 2019 at 12:33 AM Douglas Gilbert wrote:
>
> On 2019-04-16 4:19 p.m., Arnd Bergmann wrote:
> > Hi Al,
> >
> > It took me way longer than I had hoped to revisit this series, see
> > https://lore.kernel.org/lkml/20180912150142.157913-1-a...@arndb.de/
> > for the previously posted vers
On Wed, Apr 17, 2019 at 09:13:22PM +0200, Christian König wrote:
> Am 17.04.19 um 21:07 schrieb Daniel Vetter:
> > On Tue, Apr 16, 2019 at 08:38:33PM +0200, Christian König wrote:
> > > Each importer can now provide an invalidate_mappings callback.
> > >
> > > This allows the exporter to provide t
Am 18.04.19 um 10:08 schrieb Daniel Vetter:
> On Wed, Apr 17, 2019 at 09:13:22PM +0200, Christian König wrote:
>> Am 17.04.19 um 21:07 schrieb Daniel Vetter:
>>> On Tue, Apr 16, 2019 at 08:38:33PM +0200, Christian König wrote:
Each importer can now provide an invalidate_mappings callback.
Am 18.04.19 um 09:32 schrieb Chris Wilson:
Quoting Thomas Zimmermann (2019-04-18 08:29:39)
Hi
Am 18.04.19 um 00:16 schrieb Kuehling, Felix:
Adding dri-devel
On 2019-04-17 6:15 p.m., Yang, Philip wrote:
After patch "drm: Use the same mmap-range offset and size for GEM and
TTM", application fa
On Thu, Apr 18, 2019 at 08:28:51AM +, Koenig, Christian wrote:
> Am 18.04.19 um 10:08 schrieb Daniel Vetter:
> > On Wed, Apr 17, 2019 at 09:13:22PM +0200, Christian König wrote:
> >> Am 17.04.19 um 21:07 schrieb Daniel Vetter:
> >>> On Tue, Apr 16, 2019 at 08:38:33PM +0200, Christian König wrot
Two new hwmon interfaces(temp2_input and temp3_input) are added.
They are supported on SOC15 dGPUs only.
Change-Id: I935c512bd38e080fb8b6e3164c5e5294baff4e91
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 45 +++
.../gpu/drm/amd/include/kgd_pp_interf
Correct Vega10, Vega12 and Vega20 hotspot temperature critical max
values.
Change-Id: I77bb77761e8530066ec4f3225f8555cf8f672348
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +-
drivers/gpu/drm/amd/p
These new interfaces(temp1_emergency, temp2_emergency,
temp3_emergency) are supported on SOC15 dGPUs only.
Change-Id: I2552df63f9c8c50294b3940bb2a402217673c2bc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 40
Expose temp[1-3]_label hwmon interfaces. While temp2_label
and temp3_label are visible for SOC15 dGPUs only.
Change-Id: I7f1e10c52ec21d272027554cdf6da97103e0be58
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 40 +++
.../gpu/drm/amd/include/kgd_pp_in
These new interfaces(temp2_crit, temp2_crit_hyst, temp3_crit,
temp3_crit_hyst) are supported on SOC15 dGPUs only.
Change-Id: Ia87e3f6ad816b51d6680eb74c8f755d6c2b0a6ae
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 8 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
That should provide some necessary sensor information.
Change-Id: I898371cef06795c5369a14c4dd3fe8717959d81a
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 21 +++
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.h| 3 +++
.../drm/amd/powerplay/smumgr/ve
Provide the real sensor information for current power.
Change-Id: Ifad48d08a5aa4232549316fbe61bfd5f10bb1c62
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 21 +--
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/pow
Provide the real sensor information for current gpu activity.
Change-Id: I8449672a6fdabb4287e12e36a4f95e08e2d65e47
Signed-off-by: Evan Quan
---
.../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 21 ++-
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/a
On Tue, Apr 16, 2019 at 08:38:29PM +0200, Christian König wrote:
> Hi everybody,
>
> core idea in this patch set is that DMA-buf importers can now provide an
> optional invalidate callback. Using this callback and the reservation object
> exporters can now avoid pinning DMA-buf memory for a long
Am 18.04.19 um 11:13 schrieb Daniel Vetter:
On Tue, Apr 16, 2019 at 08:38:29PM +0200, Christian König wrote:
Hi everybody,
core idea in this patch set is that DMA-buf importers can now provide an
optional invalidate callback. Using this callback and the reservation object
exporters can now av
Add a peer2peer flag noting that the importer can deal with device
resources which are not backed by pages.
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf.c | 1 +
include/linux/dma-buf.h | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/d
A lot of root complexes can still do P2P even when PCI devices
don't share a common upstream bridge.
Start adding a whitelist and allow P2P if both participants are
attached to known good root complex.
Signed-off-by: Christian König
---
drivers/pci/p2pdma.c | 38
Check if we can do peer2peer on the PCIe bus.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
We should be able to do this now after checking all the prerequisites.
v2: fix entrie count in the sgt
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c| 46 --
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 9 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mg
Importing should work out of the box.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 30634396719b..af103b7e21e8 100644
--
Hi guys,
as promised this is the patch set which enables P2P buffer sharing with DMA-buf.
Basic idea is that importers can set a flag noting that they can deal with and
sgt which doesn't contains pages.
This in turn is the signal to the exporter that we don't need to move a buffer
to system me
Use this function to set an sg entry to point to device resources mapped
using dma_map_resource(). The page pointer is set to NULL and only the DMA
address, length and offset values are valid.
Signed-off-by: Christian König
---
include/linux/scatterlist.h | 23 +++
1 file cha
On 2019-04-18 5:51 a.m., Mario Kleiner wrote:
>
> My desired application of VRR for neuroscience/vision research
> is to control the timing of when frames show up onscreen, e.g.,
> to show animations at different "unconventional" framerates,
> so i'm mostly interested in how well one can control t
On 4/18/19 10:24 AM, Michel Dänzer wrote:
> On 2019-04-18 5:51 a.m., Mario Kleiner wrote:
>>
>> My desired application of VRR for neuroscience/vision research
>> is to control the timing of when frames show up onscreen, e.g.,
>> to show animations at different "unconventional" framerates,
>> so i'm
From: Christian König
Don't block others while waiting for the fences to finish, concurrent
submission is perfectly valid in this case and holding the lock can
prevent killed applications from terminating.
Signed-off-by: Christian König
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd
Problem:
Sched thread's cleanup function races against TO handler
and removes the guilty job from mirror list and we
have no way of differentiating if the job was removed from within the
TO handler or from the sched thread's clean-up function.
Fix:
Add a flag to scheduler to hint the TO handler th
From: Christian König
We now destroy finished jobs from the worker thread to make sure that
we never destroy a job currently in timeout processing.
By this we avoid holding lock around ring mirror list in drm_sched_stop
which should solve a deadlock reported by a user.
v2: Remove unused variable
Patch '5edb0c9b Fix deadlock with display during hanged ring recovery'
was accidentaly removed during one of DALs code merges.
v4: Update description.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +--
1
Also reject TDRs if another one already running.
v2:
Stop all schedulers across device and entire XGMI hive before
force signaling HW fences.
Avoid passing job_signaled to helper fnctions to keep all the decision
making about skipping HW reset in one place.
v3:
Fix SW sched. hang after non HW res
For later driver's reference to see if the fence is signaled.
v2: Move parent fence put to resubmit jobs.
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/scheduler/sched_main.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/dri
From: Leo Li
smu.ppt_funcs is only initialized for specific SMU versions.
On a Hawaii ASIC, attempting to access the udev attribute
ATTRS{power_dpm_state} will cause a null pointer deref in
amdgpu_get_dpm_state() because of this.
Fix by checking that ppt_funcs is initialized first.
CC: Chengmi
From: Leo Li
They will be used by DC when runing ASIC-specific HUBP initialization.
Signed-off-by: Leo Li
---
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
b/drive
From: Eric Bernstein
[Why]
Starting with DCN1, the input_pixel_processor (ipp) struct has been
replaced by dpp struct (part of DAL3.1 SW architecture change).
Need to update logic to handle cases where ipp is never allocated.
[How]
Only skip cursor position programming if both ipp and dpp resour
From: Nicholas Kazlauskas
[Why]
We can't do cursor programming after the planes have been disabled
since there won't be any pipes - leading to lock warnings and the wrong
cursor state being left in the registers.
When we re-enable the planes after the previous cursor state will also
remain if we
From: Eric Yang
[Why]
The new interface now replaces the old interface for all known
configurations.
Change-Id: I10c5d4805763b8d903f7a843e14f04e715b48c82
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c | 27 +---
From: Anthony Koo
[Why]
Some DMCU messages were being sent in cases where
there was no DMCU FW at all, which resulted in some wait
timeouts
[How]
Delay sending some of the DMCU messages after FW
init is called and DMCU is running.
Change-Id: Id21853decf507dddb5cf13d1895b07b9585f53a3
Signed-off-
From: Aric Cyr
Change-Id: Ib1ba11f3a4ac43ee17fd8b575b90aa0a30ef32c7
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm
From: Nicholas Kazlauskas
[Why]
We only currently drop the vblank reference when the stream is
being removed from the context. We should be dropping it whenever we
disable interrupts and reaquiring it after we re-enable them.
We also never get the extra reference correctly when re-enabling
inter
From: Charlene Liu
Different HW will need to init HUBP differently. For now, add a vtable
entry, and hook a NO-OP for DCN1.
In addition, future HW will need to access the HUBPREQ_DEBUG register
for hubp_init. Add it to the reg list.
Change-Id: I8e804e6ee02e569ac7e7b2263c7a154e8b3dfe8d
Signed-of
From: Leo Li
Summary of change:
* Implement ability to have an active CRTC, without any active planes
* Removed deprecated pplib interface
* Fixed potential register wait warning on boot
* Fixed potential eDP blackscreen on S4 resume
Anthony Koo (3):
drm/amd/display: Allow system to enter stu
From: Jun Lei
[why]
When DMCU interrupts x86, it leads to undefined phy programming
[how]
expand dmcu interface to support new PHY lock and unlock commands
if DMCU FW doesn't support these commands, they fail silently so its okay
Change-Id: I13fbb779263774e5c7c4f72e2f74a827cd0006e2
Signed-off-b
From: Anthony Koo
[Why]
Power down of PHY on eDP requires us to call eDP power
control to power on again
[How]
1. In the case link rates don't match, disable PHY
requires calling of eDP power control ON after
2. Link disable case limit to eDP path since
this is not really applicable to DP since
From: Thomas Lim
[Why]
Due to the generic introduction of seamless boot, the display is no
longer blanked upon boot. However, this causes corruption on some
systems that does not lock the memory in the non-secure boot case,
resulting in brief corruption on boot due to garbage being written into
From: Anthony Koo
[Why]
Workaround was missing in one HW disable path,
meaning when all pipes are power gated, stutter was
not working
[How]
Add workaround for init_hw path for stutter
workaround
Change-Id: Ib1f00f3605d189bc20ccb3033f2ffd22009fceb8
Signed-off-by: Anthony Koo
Reviewed-by: Aric
From: John Barberiz
Refactor dp vendor parsing int to a new function, and call it before
get_active_converter_info().
Also, add a flag to skip parsing of Display ID 2.0. Some devices fail on
readind DID2, but we shouldn't fail EDID read because of it. Add this
flag to facilitate the logic.
Chan
From: Yongqiang Sun
* Replace certain register writes with register sets that overwrites the
the entire register, instead of only a field within the register.
* Add program_watermarks() entry to hubbub vtable. Hook it up to
existing functions that program watermarks.
* Add additional watermar
From: Nicholas Kazlauskas
[Why]
When disabling all the pipes for a CRTC the page-flip interrupt also
gets disabled on Raven. We can't re-enable the page-flip interrupt
unless we give DC at least one active DC plane.
We currently enable interrupts after the call to dc_commit_state since
there's c
From: Nicholas Kazlauskas
[Why]
The vblank and pageflip interrupts should only be enabled for a CRTC
that's enabled and has active planes.
The current logic takes care of this, but isn't setup to handle the case
where the active plane count goes to zero but the stream remains
enabled.
We curren
From: Nicholas Kazlauskas
[Why]
Originally we did the amdgpu_dm_handle_vrr_transition call before
interrupts were enabled. After the interrupt toggling logic was
moved around for support enabling CRTCs with no primary planes
active this was no longer being called in the case where there
wasn't a
From: Nicholas Kazlauskas
[Why]
Many userspace applications (and IGT) seem to expect that most drivers
can keep a CRTC active and enabled if there are no primary or overlay
planes.
DC is setup to handle this but only in the case where there are
absolutely no planes on the CRTC - no primary, curs
From: Wenjing Liu
We'll need the ability to copy a dc_stream_state for some features.
Implement it here.
Change-Id: I74a6b147cb4389f60c376071db22ac8164b2b47b
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 21
On 4/17/19 11:51 PM, Mario Kleiner wrote:
> Helps with debugging issues with low framerate compensation.
>
> Signed-off-by: Mario Kleiner
> ---
This looks like it'd generate a ton of debug output (the flip stuff is
already a bit too spammy).
But more importantly the DC and module code doesn't
On 4/17/19 11:51 PM, Mario Kleiner wrote:
> The comparison of inserted_frame_duration_in_us against a
> duration calculated from max_refresh_in_uhz is both wrong
> in its math and not needed, as the min_duration_in_us value
> is already cached in in_out_vrr for reuse. No need to
> recalculate it wr
It's normal for VRAM to lost during GPU reset and so change
the log level to INFO to avoid confusing users.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device
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