shadow was added into shadow_list by amdgpu_bo_create_shadow.
meanwhile, shadow->tbo.mem was not fully configured.
tbo.mem would be fully configured by amdgpu_vm_sdma_map_table until calling
amdgpu_vm_clear_bo.
If sriov TDR occurred between amdgpu_bo_create_shadow and
amdgpu_vm_sdma_map_table,
am
Am 11.04.19 um 21:57 schrieb Alex Deucher:
Got accidently dropped when 2+1 level support was added.
Fixes: 6a42fd6fbf534096 ("drm/amdgpu: implement 2+1 PD support for Raven v3")
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/amd/am
Am 11.04.19 um 22:31 schrieb Zeng, Oak:
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will
Am 12.04.19 um 09:13 schrieb wentalou:
shadow was added into shadow_list by amdgpu_bo_create_shadow.
meanwhile, shadow->tbo.mem was not fully configured.
tbo.mem would be fully configured by amdgpu_vm_sdma_map_table until calling
amdgpu_vm_clear_bo.
If sriov TDR occurred between amdgpu_bo_create
Am 11.04.19 um 18:03 schrieb Andrey Grodzovsky:
Also reject TDRs if another one already running.
v2:
Stop all schedulers across device and entire XGMI hive before
force signaling HW fences.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 125
Am 11.04.19 um 18:03 schrieb Andrey Grodzovsky:
Patch '5edb0c9b Fix deadlock with display during hanged ring recovery'
was accidentaly removed during one of DALs code merges.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +--
1 fi
'default n' is the default value for any bool or tristate Kconfig
setting so there is no need to write it explicitly.
Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
is not set' for visible symbols") the Kconfig behavior is the same
regardless of 'default n' being present or not
On Fri, 12 Apr 2019, Bartlomiej Zolnierkiewicz wrote:
> 'default n' is the default value for any bool or tristate Kconfig
> setting so there is no need to write it explicitly.
>
> Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
> is not set' for visible symbols") the Kconfig beh
Asynchronous update is the ability change the hw state at any time, not
only during vblank.
Amend mode is the ability to perform 1000 commits to be applied as soon
as possible without waiting for 1000 vblanks.
async updates can be seen as amend, but the opposite is not true.
&drm_plane_helper_fu
Hi,
This patch series is an attempt to clarify some concepts and how things
are hooked inside drm.
There are two main concepts that are similar but different and are
causing some confusion:
- Asynchronous update: is the ability change the hw state at any time, not
only during vblank.
Add atomic_async_{check,update} hooks in drm_plane_helper_funcs.
These hooks are called when userspace requests asyncronous page flip in
the atomic api through the flag DRM_MODE_PAGE_FLIP_ASYNC.
Update those hooks in the drivers that implement async functions, except
for amdgpu who handles the fla
On 4/12/19 9:58 AM, Helen Koike wrote:
> Add atomic_async_{check,update} hooks in drm_plane_helper_funcs.
> These hooks are called when userspace requests asyncronous page flip in
> the atomic api through the flag DRM_MODE_PAGE_FLIP_ASYNC.
>
> Update those hooks in the drivers that implement asy
Hi Helen,
On Fri, 12 Apr 2019 09:58:25 -0300
Helen Koike wrote:
> Asynchronous update is the ability change the hw state at any time, not
> only during vblank.
>
> Amend mode is the ability to perform 1000 commits to be applied as soon
> as possible without waiting for 1000 vblanks.
>
> async
Hi Boris,
On 4/12/19 10:49 AM, Boris Brezillon wrote:
> Hi Helen,
>
> On Fri, 12 Apr 2019 09:58:25 -0300
> Helen Koike wrote:
>
>> Asynchronous update is the ability change the hw state at any time, not
>> only during vblank.
>>
>> Amend mode is the ability to perform 1000 commits to be applied
On 4/12/19 3:40 AM, Christian König wrote:
> Am 11.04.19 um 18:03 schrieb Andrey Grodzovsky:
>> Patch '5edb0c9b Fix deadlock with display during hanged ring recovery'
>> was accidentaly removed during one of DALs code merges.
>>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>> drivers/gpu/drm/amd/d
On Fri, 12 Apr 2019 11:06:13 -0300
Helen Koike wrote:
> Hi Boris,
>
> On 4/12/19 10:49 AM, Boris Brezillon wrote:
> > Hi Helen,
> >
> > On Fri, 12 Apr 2019 09:58:25 -0300
> > Helen Koike wrote:
> >
> >> Asynchronous update is the ability change the hw state at any time, not
> >> only during
Reviewed-by: Alex Deucher
From: Pan, Xinhui
Sent: Friday, April 12, 2019 1:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH libdrm V2] amdgpu: Fix a structure initialization issue
struct drmPciBusInfo has been aligned to 6 bytes. So m
Hi Christian,
After hdp registers are moved to a new place in mmio space, we can't access
those registers through the pre-defined register offset. I recorded the new
register offset in struct amdgpu_nbio_funcs (because those registers are nbio
registers) and initialized them in the early init.
On 4/12/19 3:39 AM, Christian König wrote:
> Am 11.04.19 um 18:03 schrieb Andrey Grodzovsky:
>> Also reject TDRs if another one already running.
>>
>> v2:
>> Stop all schedulers across device and entire XGMI hive before
>> force signaling HW fences.
>>
>> Signed-off-by: Andrey Grodzovsky
>> ---
>
From: Leo Li
Hi all,
This is a follup to this change made by Ville to add MST aux nodes:
https://github.com/vsyrjala/linux/commit/cac63f799ee2f5fbbe4f0a375383f13e03d640a5
Patch 2/2 describes what I added on top.
Sending as an RFC since there are some items I'm not certain on:
1) Only expose au
From: Leo Li
In preparation for adding aux devices for DP MST:
1. A non-cyclic idr is used for the device minor version. That way,
hotplug cycling MST devices won't needlessly increment the minor
version index.
2. A suffix option is added to the aux device file name. It can be used
to i
From: Ville Syrjälä
Expose AUX devices for MST ports, similar to how they are exposed for
SST.
The registered device will have it's MST port path appended in order to
identify it. i.e. /dev/drm_dp_aux4_mst:0-2-1
So for a MST topology like so:
+-+
| ASIC
On Fri, Apr 12, 2019 at 5:56 AM Bartlomiej Zolnierkiewicz
wrote:
>
> 'default n' is the default value for any bool or tristate Kconfig
> setting so there is no need to write it explicitly.
>
> Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
> is not set' for visible symbols") th
On Fri, Apr 12, 2019 at 12:05:29PM -0400, sunpeng...@amd.com wrote:
> From: Leo Li
>
> Hi all,
>
> This is a follup to this change made by Ville to add MST aux nodes:
> https://github.com/vsyrjala/linux/commit/cac63f799ee2f5fbbe4f0a375383f13e03d640a5
> Patch 2/2 describes what I added on top.
C
Method of getting firmware version is the same across ASICs, so remove
them from ASIC-specific files and create one in amdgpu_amdkfd.c. This new
created get_fw_version simply reads fw_version from adev->gfx than parsing
the ucode header.
Signed-off-by: Amber Lin
---
drivers/gpu/drm/amd/amdgpu/am
Remap HDP_MEM_COHERENCY_FLUSH_CNTL and HDP_REG_COHERENCY_FLUSH_CNTL
to an empty page in mmio space. We will later map this page to process
space so application can flush hdp. This can't be done properly at
those registers' original location because it will expose more than
desired registers to proc
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