Hi Alex,
could you help to submit this patch upstream?
在 3/6/2019 4:08 PM, Christian König 写道:
> Am 06.03.19 um 07:37 schrieb Cui, Flora:
>> deadlock test for sdma will cause gpu recoverty.
>> disable the test for now until GPU reset recovery could survive at least
>> 1000 times test.
>>
>> v2: a
This is a quick workaround. A more complete
error handling around psp_hw_start is actually
needed.
Change-Id: I398efd652584e022debf237950207199a4ea78fc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/dr
Am 15.03.19 um 07:01 schrieb Evan Quan:
"error" was not correctly spelled.
Change-Id: Idc3acb6172469c1d63227cb5f0df75f912c10871
Signed-off-by: Evan Quan
Reviewed-by: Christian König for this one.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2
Am 15.03.19 um 09:33 schrieb Evan Quan:
This is a quick workaround. A more complete
error handling around psp_hw_start is actually
needed.
Change-Id: I398efd652584e022debf237950207199a4ea78fc
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +
1 file changed,
add memcpy dispatch test for gfx9
Change-Id: Ic9b280db2ced21b15e228c1c4c217836ab3f44a8
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/basic_tests.c | 163 -
1 file changed, 161 insertions(+), 2 deletions(-)
add memset draw test for gfx9
Change-Id: I3a1f2460ec0917e29ce1a891200eeaa1a0565fda
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 554 +
2 files changed, 559 insertions(+)
diff --git
add memset dispatch test for gfx9
v2: disable dispatch test for other ASICs
Change-Id: I55a410a4ea0a6d19d1aca1f172e1dfcbbd1112fa
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 273
add memcpy draw test for gfx9
Change-Id: Ib80e55b1ab7aa556c4b5adfdd39aedf7d58ba628
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/basic_tests.c | 264 +++--
1 file changed, 253 insertions(+), 11 deletions(-)
diff --git a/tests/amdgpu/basic
Hw_init -> psp_hw_init -> psp_hw_start (failed) -> ras_pre_fini -> hw_fini ->
psp_hw_fini
On psp_hw_start failure, it destroys the cmd/fence/fw buffers. But the ras/xgmi
deinit was delayed to psp_hw_fini.
In ras_pre_fini, it calls the ras APIs to disable previously enabled ras
features. And th
From: Christian König
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's no
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
v4: add unorder point check, print a warn calltrace
Signed-off-by: Christian König
---
drivers/
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add comment for xxx_WAIT_AVAI
we need to import/export timeline point.
v2: unify to one transfer ioctl
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 74 ++
include/uapi/drm/drm.h | 10 +++
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8a0732088640..4d8db87048d3 100644
--- a/drivers/gpu/drm/amd/amdgp
user mode can query timeline payload.
v2: check return value of copy_to_user
v3: handle querying entry by entry
v4: rebase on new chain container, simplify interface
v5: query last signaled timeline point, not last point.
v6: add unorder point check
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
v2: individually allocate chain array, since chain node is free independently.
v3: all existing points must be already signaled before cpu perform signal
operation,
so add check condition for that.
Signed-off-by: Chunming Zhou
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
v3: fix checking for timeline syncobj
Signed-off-by: Chunming Zhou
Cc: Daniel Rakos
Cc: Jason Ekstrand
Cc: Bas Nieuwenhuizen
Cc: Dave Airlie
Cc: Christian König
Cc: Chris Wilson
From: Christian König
Implement finding the right timeline point in drm_syncobj_find_fence.
v2: return -EINVAL when the point is not submitted yet.
v3: fix reference counting bug, add flags handling as well
v4: add timeout for find fence
Signed-off-by: Christian König
---
drivers/gpu/drm/drm_
[Why]
DC provides a few visual confirmation debug options that can be
dynamically changed at runtime to help debug surface programming issues
but we don't have any way to access it from userspace.
[How]
Add the amdgpu_dm_visual_confirm debugfs entry.
It accepts a string containing the DC visual co
Am 15.03.19 um 13:42 schrieb Nicholas Kazlauskas:
[Why]
DC provides a few visual confirmation debug options that can be
dynamically changed at runtime to help debug surface programming issues
but we don't have any way to access it from userspace.
[How]
Add the amdgpu_dm_visual_confirm debugfs en
On 3/15/19 8:47 AM, Christian König wrote:
> Am 15.03.19 um 13:42 schrieb Nicholas Kazlauskas:
>> [Why]
>> DC provides a few visual confirmation debug options that can be
>> dynamically changed at runtime to help debug surface programming issues
>> but we don't have any way to access it from usersp
From: Yongqiang Sun
we were only checking the return value in one place, thus changing
generic_reg_wait from int to void and reading the register instead of
getting it from generic_reg_wait, when we need the return value.
Change-Id: Ib14a77e497960f39d9860ca8832355bdea1d9909
Signed-off-by: Yongqi
Summary of changes
*ODM related fixes and programming changes
*DP audio regression fix
*Multi-thread related fixes
Aidan Wood (1):
drm/amd/display: Fix multi-thread writing to 1 state
Aric Cyr (3):
drm/amd/display: Add a hysteresis to BTR frame multiplier
drm/amd/display: 3.2.22
drm/amd/d
From: Yongqiang Sun
Move out of header to dc_helper.c, in preparation for future
implementations.
Change-Id: I004584f11db4a136e704c4c80f830a20ff05809d
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc_helper.c | 18 ++
From: Charlene Liu
[Description]
when programming VID_TIMING, we were using the original VESA timing for
DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444.
Change-Id: I8a60e252383c11f81789f190fd3477cb3083554b
Signed-off-by: Charlene Liu
Reviewed-by: Nikola Cornij
Ac
From: Nicholas Kazlauskas
[Why]
To help prevent plane state not being set to the correct default
value if any new properties are added in the future.
[How]
Use the drm helper - which seems to be the common solution among other
DRM drivers.
Change-Id: I951a36da92ead790a3b6888d59995e349fc98b3b
Si
From: Hugo Hu
[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.
[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.
Change-Id: I41d4f5b24896ca34f50fdb3d1d121678faa09034
Signed-off-by: Hugo Hu
Reviewed-by: Reza Amini
From: Wesley Chalmers
Audio was unmuted for HDMI only, need to do so for DP as well.
Signed-off-by: Wesley Chalmers
Reviewed-by: Chris Park
Reviewed-by: Eric Bernstein
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 ++---
1 file changed, 2 in
From: Eric Bernstein
Change-Id: I1a903bcc614aadbe63725713fddf1cb0574b3a33
Signed-off-by: Eric Bernstein
Reviewed-by: Nevenko Stupar
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 -
2 files changed,
From: Nicholas Kazlauskas
[Why]
The plane_reset callback is subclassed but hasn't been updated since
the drm helper got updated to include resetting alpha related state
(state->alpha and state->pixel_blend_mode). The overlay planes
exposed by amdgpu_dm were therefore being rendered as invisible b
From: Aidan Wood
[Why]
Multiple threads were writing back to one global VBA in DC resulting
in multiple threads overwriting eachother's data
[How]
Add an instance of DML (which contains VBA) to each context and
change all calls that used dc->dml to use context->dml. Created a
seperate copy const
From: David Francis
[Why]
We need arbitrary read/write over DP AUX DPCD
for debugging
[How]
Three debugfs entries
Set the target address by writing to
"aux_dpcd_address"
(The first four bytes written are used)
Set the transaction size in bytes by writing to
"aux_dpcd_size"
(The first four byte
From: Reza Amini
Refactor setting bit fields. Correcting the offset of MD0.
Initializing the InfoPacket header fields. Defining the field offsets
and masks.
Change-Id: Ifc05e2cb861102113bc6e70e5780321e5996dd3b
Signed-off-by: Reza Amini
Reviewed-by: Anthony Koo
Acked-by: Bhawanpreet Lakha
---
From: Aric Cyr
Change-Id: I77d304828085ec379f0ebddcf5d9d143287312fe
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/driv
From: Dmytro Laktyushkin
Releasing planes should not release the 2nd odm pipe right away,
this change leaves us with 2 pipes with null planes and same stream
when planes are released during odm.
Change-Id: I9183a086d2240510b04fd6c76a9ce425128bb72c
Signed-off-by: Dmytro Laktyushkin
Reviewed-by:
From: "Leo (Hanghong) Ma"
[Why]
We need to add DP SDP message test debugfs to make sdp message test
more convenient and efficient.
[How]
Add a DM accessible SDP interface for custom data.
Change-Id: I8ad12f9ffb8dd2b7d01d12f572bbc7eb0c6c2537
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Harry W
From: Dmytro Laktyushkin
We fail to reset the second odm combine pipe. This change fixes
odm pointer management.
Change-Id: Ie4084f696636636a5965c9d75bb6291eb0626fa9
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/core/
From: Dmytro Laktyushkin
A number of places opp programming was missing for odm second pipe.
This change fixes the oversight.
Change-Id: I344c0480c76cf56a0b78a3547a5e5770d52fb547
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/dis
From: "Leo (Hanghong) Ma"
[Why]
We need to add DP SDP message test debugfs to make sdp message test
more convenient and efficient.
[How]
Add sdp_message debugfs entry in amdgpu.
Change-Id: I3bb349566bb255c1515470694b1aff602a12cc77
Signed-off-by: Leo (Hanghong) Ma
Reviewed-by: Sun peng Li
Acke
From: Wenjing Liu
Add these interfacese for future use
setup_global_lock()
lock_global()
pipe_control_lock_global()
Change-Id: I0b21add5fb5fcb0cb866534a159dccfc34283149
Signed-off-by: Wenjing Liu
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/inc/hw/ti
From: Jun Lei
[why]
There exist displays with EDIDs > 512 bytes, existing code
will cause us to ignore all extension blocks.
Change-Id: I0458baf7f8cc41f04405e25f6efe8456c0b05a57
Signed-off-by: Jun Lei
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc_
From: Eric Bernstein
[Why]
Need to set VID_N_MUL for 4:2:0 cases
[How]
Move setting to enc1_stream_encoder_dp_unblank and
ensure it is also set for non-4:2:0 cases.
Change-Id: If17faba806244d6800ec9ec64990684675f82d0f
Signed-off-by: Eric Bernstein
---
.../drm/amd/display/dc/dce110/dce110_hw_s
From: Samson Tam
[Why]
In certain cases we do link training when we don't have a backend.
[How]
In dc_link_set_preferred_link_settings(), store preferred link settings
first and then verify that the link is DP and the link stream's backend is
enabled. If either is false, then we will not do any
From: David Francis
[Why]
Somewhere in the atomic check reshuffle ABM got lost.
ABM is a crtc property (copied from a connector property).
It can change without a modeset, just like underscan.
[How]
In the skip_modeset branch of atomic check crtc updates,
copy over the abm property.
Change-Id:
From: Harmanprit Tatla
[Why]
Currently we are missing a few checks to see if HDR10 is allowed.
In particular we never check for the extended colorimetry bit (whether its
present or set to 1). Further we don't read in the dpcd block in DC that
would provide these bits.
[How]
- Added in DC code to
From: Dmytro Laktyushkin
There are issues removing surfaces/streams when odm is active.
This is a step to fix that
Change-Id: Ib2aaa55ca4b504e1d8d75247e84422f1ac9b
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
---
.../gpu/drm/amd/display/dc/core/dc
From: Aric Cyr
Change-Id: Iab825a9085c97f9584db201e1b52c48909b57d81
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Bhawanpreet Lakha
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/driv
From: Aric Cyr
[Why]
Flickering is observed on some displays when the number of inserted BTR
frames changes frequently.
[How]
Add in a margin of drift to prevent the inserted number of frames from
jumping around too frequently.
Change-Id: I592ce229f93faa74b5baa2e43a89c9e5a6174103
Signed-off-by:
Greetings All,
I was trying to ask a question on IRC but after registering it just complains
and I have no idea why,
if you want my nick to check it out it is was haweh. Anyhow I'm a student with
interest in helping out with
your mesa stack.
I've already got a few very minor patches in gcc and
On Fri, Mar 15, 2019 at 4:25 AM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> radeon_glamor_finish only works if we're using glamor, otherwise it'll
> crash.
>
> Fixes: ce7db51020d3 "Cancel pending scanout update in
> drmmode_crtc_scanout_update"
> Bug: https://bugs.debian.org/924540
> Signed
Hi Nick,
I can see your username on the radeon IRC channel, so that much is working.
When I try to chat it just hands up at "offering DCC CHAT to haweh" though.
What kind of error message are you getting ?
Thanks,
John
From: amd-gfx on behalf of nick
Sen
On Fri, Mar 15, 2019 at 2:36 PM nick wrote:
>
> Greetings All,
>
> I was trying to ask a question on IRC but after registering it just complains
> and I have no idea why,
> if you want my nick to check it out it is was haweh. Anyhow I'm a student
> with interest in helping out with
> your mesa s
Hi Lauri,
Thanks for your persistence. Seeing that this is reproducible on several boards
with up-to-date BIOS is really helpful and gives me some confidence that it's
more than a weird vendor or board-specific corner case and that we should be
able to reproduce it. Yong is going to start looki
Hi Chunming,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on next-20190306]
[cannot apply to v5.0]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.co
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