Some registers read/write needs program through SDRAM pool under
DPG mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/driv
Add functions to support VCN DPG pause mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 161 +++-
1 file changed, 159 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/
New register offset/mask need to be added to support VCN DPG mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
.../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 8 +++
.../drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 25 ++
2 files changed, 33 insertio
On Mon, Sep 24, 2018 at 02:38:18PM +0200, Christian König wrote:
> Let's start to support multiple rings.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8
> drivers/g
Add DPG pause state to support VCN DPG mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index d
Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers
can't be directly accessed under DPG(Dynamic Power Gate) mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16
1 file changed, 8 insertions(+), 8 deletions
Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
inde
Add DPG support flag for VCN DPG mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 86b167e..2083c30
Add DPG mode start/stop/mc_resume/clock_gating to
support vcn 1.0 DPG mode.
Signed-off-by: James Zhu
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 319 +-
1 file changed, 313 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/
On Mon, Sep 24, 2018 at 02:38:18PM +0200, Christian König wrote:
> Let's start to support multiple rings.
>
> Signed-off-by: Christian König
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 8
> drivers/g
Am 25.09.2018 um 21:55 schrieb James Zhu:
Add DPG support flag for VCN DPG mode.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
in
Am 26.09.2018 um 08:05 schrieb Huang Rui:
On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote:
One for the ring buffer and one for the IV handling.
Signed-off-by: Christian König
Reviewed-by: Huang Rui
How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't need
two
From: Akshu Agrawal
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
Multiple runs of power measurement shows no imapct.
Change-Id: I6171ced550ee244e6b9a961fb50247d12f4168a0
Signed-off-by: Akshu Agrawal
Signe
static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 1ceec56de015..412359b446f1 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -517,6 +517,8 @@ struct drm_amdgpu_gem_va {
#def
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian K?nig
> Sent: Monday, September 24, 2018 8:38 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 8/9] drm/amdgpu: simplify IH programming
>
> Calculate all the addresses and p
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian K?nig
> Sent: Monday, September 24, 2018 8:38 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH 9/9] drm/amdgpu: enable IH ring 1 and ring 2
>
> The entries are ignored for n
> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Tuesday, September 25, 2018 7:01 PM
> To: Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
>
> Am 25.09.2018 um 12:28 schrieb Huang Rui:
Am 26.09.2018 um 10:52 schrieb Huang, Ray:
-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Tuesday, September 25, 2018 7:01 PM
To: Huang, Ray
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
Am 25.09.2018
Hey Chunming,
On 20.09.2018 13:03, Chunming Zhou wrote:
@@ -1113,48 +1117,91 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct
amdgpu_cs_parser *p,
}
static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
- struct amdgp
> -Original Message-
> From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
> Sent: Wednesday, September 26, 2018 4:09 PM
> To: Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
>
> Am 26.09.2018 um 08:05 schrieb Hua
Am 26.09.2018 um 11:16 schrieb Huang, Ray:
-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Wednesday, September 26, 2018 4:09 PM
To: Huang, Ray
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs
Am 26
> -Original Message-
> From: Koenig, Christian
> Sent: Wednesday, September 26, 2018 4:58 PM
> To: Huang, Ray
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c
>
> Am 26.09.2018 um 10:52 schrieb Huang, Ray:
> >> -Original Message-
> >>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of James Zhu
> Sent: Wednesday, September 26, 2018 7:03 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, James
> Subject: [PATCH v2 1/8] drm/amdgpu:Use register UVD_SCRATCH9 for VCN
> ring/ib t
The debugfs_create_file() returns error pointers if DEBUGFS isn't
enabled. But here, we know that it is enabled so it returns NULL on
error which could lead to a NULL dereference a few lines later.
Signed-off-by: Dan Carpenter
---
If someone wanted to delete the error handling as well that would
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 8ef4a53..2ceab76 100644
--- a/
Am 26.09.2018 um 14:41 schrieb Rex Zhu:
Signed-off-by: Rex Zhu
Actually that code can just be removed because uvd_*_enc_get_destroy_msg
is only called with direct=true.
Christian.
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
2 files c
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 +
drivers/gpu/drm/amd/powerplay/smumgr
the vcn power will be controlled by VCN.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 16 +---
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr
SDMA IP can be power up/down via smu message
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 8
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 27 insert
HW CG feature will be enabled after hw ip initialized
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumg
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 5 -
drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c | 5 -
4 files changed, 12 deletions(
initialize gfx/sdma before dpm features enabled.
and disable dpm features before gfx/sdma fini.
Acked-by: Alex Deucher
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/cik.c | 17 +
drivers/gpu/drm/amd/amdgpu/si.c| 13 +++--
drivers/gpu/drm/amd/amdgpu/soc15.c
Export this interface for the AMDGPU_FW_LOAD_SMU type.
gfx/sdma can request smu to load firmware.
Split the smu7/8_start_smu function into two functions
1. start_smu, used for load smu firmware in smu7/8 and
check smu firmware version.
2. request_smu_load_fw, used for load other ip's firmware
On 2018-09-26 04:02 AM, Christian König wrote:
Am 25.09.2018 um 21:55 schrieb James Zhu:
Add DPG support flag for VCN DPG mode.
Signed-off-by: James Zhu
---
drivers/gpu/drm/amd/include/amd_shared.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/amd_share
On 2018-09-26 06:38 AM, Huang, Ray wrote:
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of James Zhu
Sent: Wednesday, September 26, 2018 7:03 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James
Subject: [PATCH v2 1/8] drm/amdgpu:Use register
From: Shaoyun Liu
Firmware have the workaround to replace the atomic Ops with read-modify-write
on CP side.
User should not expect atomic Ops on system memory works normally if system
didn't not
support it.
Change-Id: I89395b099fe0931b9b3627651b512dde3149fadd
Signed-off-by: Shaoyun Liu
Signed
Ok. I will remove the code.
Best Regards
Rex
From: Christian König
Sent: Wednesday, September 26, 2018 8:45 PM
To: Zhu, Rex; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Fix copy error in uvd_v6/7_0.c
Am 26.09.2018 um 14:41 schrieb Rex Zhu:
printk_ratelimit() is much better suited to limit the number of reported
VM faults.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 37 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 -
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 18
Not used any more.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 13 -
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 13 -
drivers/gpu/drm/amd/am
This allows us to filter out VM faults in the GMC code.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 29 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_
Calculate all the addresses and pointers in amdgpu_ih.c
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 34 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 23 -
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 9 -
dri
The entries are ignored for now, but it at least stops crashing the
hardware when somebody tries to push something to the other IH rings.
v2: limit ring size, add TODO comment
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 4 +-
drivers/gpu/drm/amd/amdgpu/vega10_
To distinct on which IH ring an IV was found.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 11 +++
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
This finally enables processing of ring 1 & 2.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 68 +++---
1 file changed, 63 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/ve
Previously we only added the ring buffer memory, now add the handling as
well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 32
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 4 +++-
2 files changed, 35 insertions(+), 1 deletion(-)
di
That should add back pressure on the client.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index dd155a207fdd..c8525c29fc16 100644
--
Let's start to support multiple rings.
v2: decode IV is needed as well
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 13
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 29 +
drivers/gpu/drm/amd
We ignored the return code here.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index f35d7a554ad5..2420ae90047e 100644
--- a/drivers/gp
The GMC/VM subsystem is causing the faults, so move the handling here as
well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 59 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 69 --
2 files changed, 59 inserti
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu wrote:
>
> Signed-off-by: Rex Zhu
Please describe why the code is useless and can be removed.
Thanks,
Alex
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c| 1 -
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 -
> drivers/gpu/drm/a
On Wed, Sep 26, 2018 at 8:51 AM Rex Zhu wrote:
>
> SDMA IP can be power up/down via smu message
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 8
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu wrote:
>
> smu only expose interface to other ip blocks.
> in order to reduce dependence between smu and other ip blocks
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++
> driv
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu wrote:
>
> the vcn power will be controlled by VCN.
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 16 +---
> 1 file changed, 1 insertion(+), 15 deletions(-)
>
> diff --git
On Wed, Sep 26, 2018 at 8:52 AM Rex Zhu wrote:
>
> HW CG feature will be enabled after hw ip initialized
>
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/drivers/
On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu wrote:
>
> Export this interface for the AMDGPU_FW_LOAD_SMU type.
> gfx/sdma can request smu to load firmware.
>
> Split the smu7/8_start_smu function into two functions
> 1. start_smu, used for load smu firmware in smu7/8 and
>check smu firmware version
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo':
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning:
variable 'header' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing
---
drivers/gpu/drm/
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, September 26, 2018 10:15 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
>
> On Wed, Sep 26, 2018 at 8:53 AM Rex Zhu wrote:
> >
> > Export this interface for the AM
On Wed, Sep 26, 2018 at 11:21 AM Zhu, Rex wrote:
>
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Wednesday, September 26, 2018 10:15 PM
> > To: Zhu, Rex
> > Cc: amd-gfx list
> > Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
> >
> > On Wed, Sep 26, 201
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, September 26, 2018 11:39 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 6/7] drm/amd/pp: Export load_firmware interface
>
> On Wed, Sep 26, 2018 at 11:21 AM Zhu, Rex wrote:
> >
> >
> >
> > > -Original Messag
expects argument of type ‘unsigned int’ has type ‘long int’
Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach
expected value")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
Fix some indentation issues.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 36 -
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index c6
Am 26.09.2018 um 18:25 schrieb Alex Deucher:
expects argument of type ‘unsigned int’ has type ‘long int’
Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach
expected value")
Signed-off-by: Alex Deucher
Reviewed-by: Christian König for the series.
---
drivers/
Acked-by: Alex Deucher
From: amd-gfx on behalf of Kent Russell
Sent: Wednesday, September 26, 2018 9:41:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent; Liu, Shaoyun
Subject: [PATCH] drm/amdkfd: Remove the requirement for atomic Ops on vg20
From: Sha
On 2018-09-26 12:25 PM, Alex Deucher wrote:
expects argument of type ‘unsigned int’ has type ‘long int’
Fixes: 52e211c1f04 ("drm/amdgpu:Add error message when register failed to reach
expected value")
Signed-off-by: Alex Deucher
Reviewed-by: James Zhu for the series.
---
drivers/gpu/drm
From: Leo Li
Summary of change:
* Edid emulation fix
* S3 resume fix on Vega10
* Add build types for internal tracking
* Fix screen corruption on polaris
* Interlace video timing fix
Bhawanpreet Lakha (1):
drm/amd/display: Fix Edid emulation for linux
Charlene Liu (2):
drm/amd/display: fix
From: Jun Lei
[why]
Sometimes there are indications that the incorrect driver is being
loaded in automated tests. This change adds the ability for builds to
be tagged with a string, and picked up by the test infrastructure.
[how]
dc.c will allocate const for build id, which is init-ed with defau
From: Charlene Liu
[Why]
HDMI_scramber is not enabled for pixel rate >340Mhz.
[How]
Calculate the phy clock to include the Hw frame packing factor.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
1 file chang
From: Nikola Cornij
[why]
Same functions exist for all other signal types.
[how]
Add a function that checks against virtual signal type.
Signed-off-by: Nikola Cornij
Reviewed-by: Leo Li
---
drivers/gpu/drm/amd/display/include/signal_types.h | 5 +
1 file changed, 5 insertions(+)
diff --
From: Su Sung Chung
[Why]
Previously bandwidth validation was failing because swizzle mode was not
initialized during plane_state allocation. The swizzle mode was
calculated using pixed format which is how swizzle mode is initially
calculated in addrlib.
[How]
* Set default swizzle mode for vali
From: Eryk Brol
Also add dram clock to clocks struct, for systems that uses them.
Signed-off-by: Eryk Brol
Reviewed-by: Jun Lei
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +
drivers/gpu/drm/amd/display/dc/dc.h | 4 +++-
drivers/gpu/drm/amd/display/
From: Eric Yang
[why]
Currently not supported, will black screen when set.
[How]
Fail validate timing helper for those modes.
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 3 +++
drivers/gpu/drm/amd/display/
From: Eric Yang
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
---
drivers/gpu/drm/amd/dis
From: Jun Lei
[why]
ddc engines were recently changed to be independently tracked
from pipe count. the change was reflected in resource constructor
but not in destructor. this manifests as a memory leak when
pipe harvesting is enabled, since not all constructed ddc engines
are freed
[how]
make
From: Yongqiang Sun
[Why]
DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL
is set by bios command table during dcn init_hw.
[How]
As a work around, check STATE_CNTL status before init_hw,
if it is 0 before init_hw and set to 1 after init_hw,
change it to 0.
Signed-off-by: Yongqiang Sun
From: Bhawanpreet Lakha
[Why]
EDID emulation didn't work properly for linux, as we stop programming
if nothing is connected physically.
[How]
We get a flag from DRM when we want to do edid emulation. We check if
this flag is true and nothing is connected physically, if so we only
program the fro
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Steven Chiu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index f328483..1995271 10
From: Charlene Liu
[Description] interlace mode shows wrong vertical timing.
Interface timing in Edid is half vertical timing as progressive timing.
driver doubled the vertical timing in edid_paser,
no need to double in optc again.
Signed-off-by: Charlene Liu
Reviewed-by: Chris Park
Acked-by:
From: Leo Li
[Why]
There is no reason why the common data needs to be kept separate.
[How]
Flatten the struct by moving common data into the DM IRQ struct.
Signed-off-by: Leo Li
Reviewed-by: David Francis
Acked-by: Leo Li
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 37 -
From: Murton Liu
[Why]
Due to a small pre-fetch window, the active vline timing is a couple
of lines off when compared to what it should be.
[How]
Changed the calculation for the start vline to account for this window.
Signed-off-by: Murton Liu
Reviewed-by: Aric Cyr
Acked-by: Leo Li
---
dri
From: Roman Li
[Why]
There have been a few reports of Vega10 display remaining blank
after S3 resume. The regression is caused by workaround for mode
change on Vega10 - skip set_bandwidth if stream count is 0.
As a result we skipped dispclk reset on suspend, thus on resume
we may skip the clock u
From: Nicholas Kazlauskas
[Why]
The DISPCLK value was previously requested to be 15% higher for all
ASICS that went through the dce110 bandwidth code path. As part of a
refactoring of dce_clocks and dce110 set_bandwidth this was removed
for power saving considerations.
This changed caused corru
On Wed, Sep 26, 2018, at 08:53, Christian König wrote:
> This allows us to filter out VM faults in the GMC code.
>
> Signed-off-by: Christian König
The KFD needs to receive notification of unhandled VM faults; when demand
paging is disabled or the address is not pageable. It propagates this to
On Wed, Sep 26, 2018 at 9:54 AM Christian König
wrote:
>
> This finally enables processing of ring 1 & 2.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 68
> +++---
> 1 file changed, 63 insertions(+), 5 deletions(-)
>
> diff --gi
Manual fan RPM and pwm setting on vega20 are
available now.
V2: correct the register for fan speed setting and
avoid divide-by-zero
Change-Id: Iad45a169d6984acc091c4efaf46973619fe43a29
Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
Reviewed-by: Rex Zhu
---
.../include/asic_reg/thm/thm
I had a chat with Jerome yesterday. He pointed out that the new blockable
parameter can be used to infer whether the MMU notifier is being called in a
reclaim operation. So if blockable==true, it should even be safe to take the BO
reservation lock without problems. I think with that we should b
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