[bug report] drm/amd/display: Program vline interrupt on FAST update

[ This patch is from May. I don't know why it's only complaining now. - dan ] Hello SivapiriyanKumarasamy, This is a semi-automatic email about new static checker warnings. The patch 27e2e2077479: "drm/amd/display: Program vline interrupt on FAST update" from May 18, 2018, leads to the follo

Re: [PATCH] drm/amdgpu: Move fence SW fallback warning.

Am 24.09.2018 um 21:32 schrieb Andrey Grodzovsky: Only print the warning if there was actually some fence processed from the SW fallback timer. Well that is a wider change than I expected. Maybe we could let amdgpu_fence_process() return if it processed something instead? Most callers can t

Re: [PATCH] drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gating

Am 25.09.2018 um 07:29 schrieb Rex Zhu: Signed-off-by: Rex Zhu Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 9

Re: [PATCH 3/6] drm: add support of syncobj timeline point wait v2

On Thu, Sep 20, 2018 at 6:04 AM Chunming Zhou wrote: > points array is one-to-one match with syncobjs array. > v2: > add seperate ioctl for timeline point wait, otherwise break uapi. > I think ioctl structs can be extended as long as fields aren't re-ordered. I'm not sure on the details of this

Re: [PATCH 3/6] drm: add support of syncobj timeline point wait v2

Am 25.09.2018 um 11:22 schrieb Jason Ekstrand: On Thu, Sep 20, 2018 at 6:04 AM Chunming Zhou > wrote: points array is one-to-one match with syncobjs array. v2: add seperate ioctl for timeline point wait, otherwise break uapi. I think ioctl structs can be

Re: [PATCH 1/9] drm/amdgpu: drop extra newline in amdgpu_iv trace

On Mon, Sep 24, 2018 at 02:38:12PM +0200, Christian König wrote: > That is superflous here. > > Signed-off-by: Christian König Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd

[PATCH] drm/amdgpu: Fix Rv init failed

Partially revert: commit 91079a250cbe ("drm/amdgpu: Change the gfx/sdma init/fini sequence")' drm/amdgpu: Change the gfx/sdma init/fini sequence Currently sdma ip is power up when smu hw init, so can't change the hw sequence on Rv. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/soc15.c |

Re: [PATCH] drm/amdgpu: Fix Rv init failed

On Tue, Sep 25, 2018 at 05:54:00PM +0800, Rex Zhu wrote: > Partially revert: > commit 91079a250cbe ("drm/amdgpu: Change the gfx/sdma init/fini sequence")' > drm/amdgpu: Change the gfx/sdma init/fini sequence > > Currently sdma ip is power up when smu hw init, so can't change > the hw sequence on R

Re: [PATCH 2/9] drm/amdgpu: make function pointers mandatory

On Mon, Sep 24, 2018 at 02:38:13PM +0200, Christian König wrote: > We always want those to be setup correctly. > > Signed-off-by: Christian König Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/cik_ih.c | 3 +-- > drivers/gpu/drm/amd/amdgpu/cik_sdma.c| 20 -

Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c

On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote: > Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. > > Signed-off-by: Christian König Reviewed-by: Huang Rui Will we have multiple interrupt rings in new asic? Thanks, Ray > --- > drivers/gpu/drm/amd/amdgpu/a

Re: [PATCH 3/9] drm/amdgpu: cleanup amdgpu_ih.c

Am 25.09.2018 um 12:28 schrieb Huang Rui: On Mon, Sep 24, 2018 at 02:38:14PM +0200, Christian König wrote: Cleanup amdgpu_ih.c to be able to handle multiple interrupt rings. Signed-off-by: Christian König Reviewed-by: Huang Rui Will we have multiple interrupt rings in new asic? Vega alrea

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On 2018-09-24 10:26 p.m., Ville Syrjälä wrote: > On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: >> On 09/24/2018 02:38 PM, Ville Syrjälä wrote: >>> >>> Actually I don't understand why this per-crtc thing is being added at >>> all. You already have the prop on the connector. W

[PATCH 2/3] drm/amdgpu: Move out power up/down sdma out of smu

smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 + drivers/gpu/drm/amd/powerplay/smumgr

[PATCH 1/3] drm/amd/pp: Expose the smu support for SDMA PG cntl

SDMA IP can be power up/down via smu message Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 ++ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 8 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 + 3 files changed, 27 insert

[PATCH 3/3] drm/amd/pp: Remove uncessary extra vcn pg cntl in smu

the vcn power will be controlled by VCN. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c | 16 +--- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr

Re: [PATCH 1/3] drm/amd/pp: Expose the smu support for SDMA PG cntl

Patch 1, 2: Reviewed-by: Huang Rui Patch 3 make raven2 hang during load vcn ucode. Thanks, Ray On Tue, Sep 25, 2018 at 09:32:55PM +0800, Rex Zhu wrote: > SDMA IP can be power up/down via smu message > > Signed-off-by: Rex Zhu > --- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 18 +++

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On 09/24/2018 04:26 PM, Ville Syrjälä wrote: On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: On 09/24/2018 02:38 PM, Ville Syrjälä wrote: On Mon, Sep 24, 2018 at 02:15:36PM -0400, Nicholas Kazlauskas wrote: Variable refresh rate algorithms have typically been enabled only

Re: [PATCH] drm/amdgpu: Move fence SW fallback warning.

If only we had C++ default arguments :) np. Andrey On 09/25/2018 04:04 AM, Christian König wrote: Am 24.09.2018 um 21:32 schrieb Andrey Grodzovsky: Only print the warning if there was actually some fence processed from the SW fallback timer. Well that is a wider change than I expected. Ma

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On Tue, Sep 25, 2018 at 03:28:28PM +0200, Michel Dänzer wrote: > On 2018-09-24 10:26 p.m., Ville Syrjälä wrote: > > On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: > >> On 09/24/2018 02:38 PM, Ville Syrjälä wrote: > >>> > >>> Actually I don't understand why this per-crtc thing

[PATCH v2] dmr/amdgpu: Move fence SW fallback warning v2

Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_fallback to let amdgpu_fence_fallback know fences were actually processed and then print the warning. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgp

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On 2018-09-25 4:04 p.m., Ville Syrjälä wrote: > On Tue, Sep 25, 2018 at 03:28:28PM +0200, Michel Dänzer wrote: >> On 2018-09-24 10:26 p.m., Ville Syrjälä wrote: >>> On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas wrote: On 09/24/2018 02:38 PM, Ville Syrjälä wrote: > > Ac

Re: [PATCH v2 2/3] drm: Add variable refresh property to DRM CRTC

On Tue, Sep 25, 2018 at 04:35:59PM +0200, Michel Dänzer wrote: > On 2018-09-25 4:04 p.m., Ville Syrjälä wrote: > > On Tue, Sep 25, 2018 at 03:28:28PM +0200, Michel Dänzer wrote: > >> On 2018-09-24 10:26 p.m., Ville Syrjälä wrote: > >>> On Mon, Sep 24, 2018 at 03:06:02PM -0400, Kazlauskas, Nicholas

Re: [PATCH v2] dmr/amdgpu: Move fence SW fallback warning v2

Am 25.09.2018 um 16:27 schrieb Andrey Grodzovsky: Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_fallback to let amdgpu_fence_fallback know fences were actually processed and then print the warning. Signed-off-b

[PATCH v3] dmr/amdgpu: Move fence SW fallback warning v3

Only print the warning if there was actually some fence processed from the SW fallback timer. v2: Add return value to amdgpu_fence_fallback to let amdgpu_fence_fallback know fences were actually processed and then print the warning. v3: Always return true if seq != last_seq Signed-off-by: Andrey

Re: [PATCH v3] dmr/amdgpu: Move fence SW fallback warning v3

Am 25.09.2018 um 20:11 schrieb Andrey Grodzovsky: > Only print the warning if there was actually some fence processed > from the SW fallback timer. > > v2: Add return value to amdgpu_fence_fallback to let > amdgpu_fence_fallback know fences were actually > processed and then print the warning. > >

Re: [PATCH v3] dmr/amdgpu: Move fence SW fallback warning v3

On Tue, Sep 25, 2018 at 2:11 PM Andrey Grodzovsky wrote: > > Only print the warning if there was actually some fence processed > from the SW fallback timer. > > v2: Add return value to amdgpu_fence_fallback to let > amdgpu_fence_fallback know fences were actually > processed and then print the war

[PATCH 6/8] drm/amdgpu:Add DPG pause state

Add DPG pause state to support VCN DPG mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index d2219ab..0b88a46 100644 ---

[PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0

Add DPG mode start/stop/mc_resume/clock_gating to support vcn 1.0 DPG mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 319 +- 1 file changed, 313 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/driver

[PATCH 1/8] drm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib test

Use register UVD_SCRATCH9 for VCN ring/ib test. Since those registers can't be directly accessed under DPG(Dynamic Power Gate) mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/g

[PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO

Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 138c481..9f462c0 100644 -

[PATCH 7/8] drm/amdgpu:Add DPG pause mode support

Add fucntions to support VCN DPG pause mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 161 +++- 1 file changed, 159 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_v

[PATCH 4/8] drm/amdgpu:Add DPG mode read/write macro

Some registers read/write needs program through SDRAM pool under DPG mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/soc15_common.h | 20 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc1

[PATCH 3/8] drm/amdgpu:Add DPG support flag

Add DPG support flag for VCN DPG mode. Signed-off-by: James Zhu --- drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 86b167e..2f6bdf1 100644 --- a/drivers/gpu/

[PATCH 2/8] drm/amdgpu:Add new register offset/mask to support VCN DPG mode

New register offset/mask need to be added to support VCN DPG mode. Signed-off-by: James Zhu --- .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 8 +++ .../drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 25 ++ 2 files changed, 33 insertions(+) diff --git a/drivers

Re: [PATCH 3/8] drm/amdgpu:Add DPG support flag

On Tue, Sep 25, 2018 at 4:04 PM James Zhu wrote: > > Add DPG support flag for VCN DPG mode. > > Signed-off-by: James Zhu > --- > drivers/gpu/drm/amd/include/amd_shared.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/include/amd_shared.h > b/drivers/gpu/drm/amd/i

Re: [PATCH 5/8] drm/amdgpu:Add DPG mode support for vcn 1.0

On Tue, Sep 25, 2018 at 4:04 PM James Zhu wrote: > > Add DPG mode start/stop/mc_resume/clock_gating to > support vcn 1.0 DPG mode. > > Signed-off-by: James Zhu > --- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 319 > +- > 1 file changed, 313 insertions(+), 6 deleti

Re: [PATCH 7/8] drm/amdgpu:Add DPG pause mode support

On Tue, Sep 25, 2018 at 4:04 PM James Zhu wrote: > > Add fucntions to support VCN DPG pause mode. fucntions -> functions With that fixed: Reviewed-by: Alex Deucher > > Signed-off-by: James Zhu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 161 > +++- > 1 file

Re: [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO

On Tue, Sep 25, 2018 at 4:04 PM James Zhu wrote: > > Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso > > Signed-off-by: James Zhu I made some comments on a few of the patches, the rest are: Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- > 1 file change

Re: [PATCH 8/8] drm/amdgpu:Enable DPG mode on PCO

On 2018-09-25 04:15 PM, Alex Deucher wrote: On Tue, Sep 25, 2018 at 4:04 PM James Zhu wrote: Add flag AMD_PG_SUPPORT_DPG to enable DPG mode on Picasso Signed-off-by: James Zhu I made some comments on a few of the patches, the rest are: Reviewed-by: Alex Deucher All fixed will be included

Re: [PATCH 6/9] drm/amdgpu: separate IH and IRQ funcs

On Mon, Sep 24, 2018 at 02:38:17PM +0200, Christian König wrote: > One for the ring buffer and one for the IV handling. > > Signed-off-by: Christian König Reviewed-by: Huang Rui How about merge amdgpu_ih.c into amdgpu_irq.c? As I think, we don't need two common interrupt handle files. IH is ac

Re: [PATCH 4/9] drm/amdgpu: move more interrupt processing into amdgpu_irq.c

On Mon, Sep 24, 2018 at 02:38:15PM +0200, Christian König wrote: > Add a callback to amdgpu_ih_process to remove most of the IV logic. > > Signed-off-by: Christian König Acked-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 24 +--- > drivers/gpu/drm/amd/am

Re: [PATCH 5/9] drm/amdgpu: move more defines into amdgpu_irq.h

On Mon, Sep 24, 2018 at 02:38:16PM +0200, Christian König wrote: > Everything that isn't related to the IH ring. > > Signed-off-by: Christian König Reviewed-by: Huang Rui > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h| 22 +--- > drivers/gpu/drm/amd/amdgpu/amdgpu_i