We won't initialize fence scheduler in drm_sched_fence_create() anymore, so it
will refer null fence scheduler if open trace event to get the timeline name.
Actually, it is the scheduler name from the entity, so add a macro to replace
legacy getting timeline name by job.
[ 212.844281] BUG: unable
Yeah that is a known issue, but this solution is not correct either.
See the scheduler where the job is execute on is simply not determined
yet when we want to trace it.
So using the scheduler name from the entity is wrong as well.
We should probably move the reschedule from drm_sched_entity_
On 08/08/2018 02:51 PM, Christian König wrote:
Am 08.08.2018 um 06:08 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
Can the new function be also used to initialize a BO structure during import?
Yeah, that's what I'm going to talk a bit more in this patch.
(actual
Am 08.08.2018 um 09:12 schrieb Zhang, Jerry (Junwei):
On 08/08/2018 02:51 PM, Christian König wrote:
Am 08.08.2018 um 06:08 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
Can the new function be also used to initialize a BO structure during
import?
Yeah, that's
On 08/08/2018 02:48 PM, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu.h| 23
On 2018年08月08日 14:48, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu.h | 23
Am 08.08.2018 um 10:43 schrieb zhoucm1:
On 2018年08月08日 14:48, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei
On 08/08/2018 04:51 PM, Christian König wrote:
Am 08.08.2018 um 10:43 schrieb zhoucm1:
On 2018年08月08日 14:48, Christian König wrote:
Am 08.08.2018 um 06:23 schrieb zhoucm1:
On 2018年08月08日 12:08, Junwei Zhang wrote:
Userspace needs to know if the user memory is from BO or malloc.
v2: updat
Add a test for API to query bo by CPU mapping
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
tests/amdgpu/bo_tests.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 9d4da4a..dc2de9b 1006
When create bo from user memory, add it to handle table
for future query.
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
amdgpu/amdgpu_bo.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 422c7c9..b24e69
Userspace needs to know if the user memory is from BO or malloc.
v2: update mutex range and rebase
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
amdgpu/amdgpu.h| 23 +++
amdgpu/amdgpu_bo.c | 39 +++
2 files changed, 62
The idea and proposal is originally from Christian, and I continue to work to
deliver it.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end of the LRU, and impact perfor
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
---
include/drm/ttm/ttm_bo_driver.h | 28
1 file changed, 28 i
From: Christian König
When move a BO to the end of LRU, it need remember the BO positions.
Make sure all moved bo in between "first" and "last". And they will be bulk
moving together.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 -
This function allow us to bulk move a group of BOs to the tail of their LRU.
The positions of group of BOs are stored on the (first, last) bulk_move_pos
structure.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
---
drivers/gpu/drm/ttm/ttm_bo.c | 52 +
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end of the LRU, and impact performance seriousl
The new bulk moving functionality is ready, the overhead of moving PD/PT bos to
LRU is fixed. So move them on LRU again.
Signed-off-by: Huang Rui
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Am 08.08.2018 um 11:59 schrieb Huang Rui:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end
On Wed, Aug 08, 2018 at 03:10:07PM +0800, Koenig, Christian wrote:
> Yeah that is a known issue, but this solution is not correct either.
>
> See the scheduler where the job is execute on is simply not determined
> yet when we want to trace it.
>
> So using the scheduler name from the entity is
On Wed, Aug 8, 2018 at 4:58 PM Huang Rui wrote:
> On Wed, Aug 08, 2018 at 03:10:07PM +0800, Koenig, Christian wrote:
> > Yeah that is a known issue, but this solution is not correct either.
> >
> > See the scheduler where the job is execute on is simply not determined
> > yet when we want to trac
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Emily Deng
Sent: Tuesday, August 7, 2018 10:13 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily; Liu, Monk
Subject: [PATCH] drm/amdgpu/sriov: give 8s for recover vram under RUNTIME
Modify the commit mes
Dear Deng,
On 08/08/18 04:13, Emily Deng wrote:
> Modify the commit message
I guess the line above is a leftover from some template, and can be
removed?
> Extend the timeout for recovering vram bos from shadows on sr-iov
> to cover the worst case scenario for timeslices and VFs
>
> Under runti
From: "Jerry (Fangzhi) Zuo"
[Why]
DOUBLE_BUFFER_EN bit is getting cleared before enable blanking.
That leads to CRTC_BLANK_DATA_EN is getting updated immediately.
[How]
Get DOUBLE_BUFFER_EN bit set, the same as DCE110.
Change-Id: Ib88dc8b81b4e5dadca1fa086d2b509e491846396
Signed-off-by: Jerry (F
From: "Leo (Sunpeng) Li"
Summary of change:
* Enable clock sharing b/w HDMI and single link DVI
* Fix possible null pointer deref when fetching CRC
Charlene Liu (2):
drm/amd/display: fix single link DVI has no display
drm/amd/display: add retimer log for HWQ tuning use.
Dmytro Laktyushkin (
From: "Leo (Sunpeng) Li"
[Why]
Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for
overflows. read_channel_reply also returns -1 on error, which is what
dc_link_aux_transfer is expected to return on error.
[How]
Remove the if-statement. Return result of read_channel_reply di
From: Gloria Li
[Why]
There are outstanding bugs for PIP in Dal3:
-Crash when toggling PIP visibility
-Global Alpha is not working, Adjusting global alpha
doesn’t have an effect
-Cursor is not working with pip plane and pipe splits
-One flash occurs when cursor enters PIP plane from
top/bottom
From: Charlene Liu
Change-Id: Ie73c190eb7caf8d07df66b0f94297e2dacd24afe
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_l
From: Dmytro Laktyushkin
mono formats are treated exactly the same as equivallent bpp
444 formats. Dml validation however lacks 444 8 bit format
while dml perf param calculation lacks mono format support
This change makes them equivallent as far as the enum is concerned
to avoid having to update
From: Dmytro Laktyushkin
This allows us to avoid any vbios bugs when initializing clocks
Change-Id: Id29c32528b3d98c625f8921c2ef50da7d3de454c
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Charlene Liu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 4 +++-
drivers/gpu
From: Charlene Liu
Change-Id: If940d2adae8c51e66f705193d6bd2ac20c85cc5e
Signed-off-by: Charlene Liu
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 59 ++
drivers/gpu/drm/amd/display/include/logger_types.h | 3 +-
From: Tony Cheng
Change-Id: I7401aaec323190bf12dae37bdee3ecf4971c6ab0
Signed-off-by: Tony Cheng
Reviewed-by: Steven Chiu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/
From: Mikita Lipski
[why]
HDMI and DVI share the same PHY clock and single link
DVI and HDMI both use 4 lanes, so they should be allowed
to be sharing the same clock source if all other parameters
are satisfied.
[how]
Change a check for general DVI to Dual DVI.
Change-Id: Ie1d4c283e9d0683186874
From: SivapiriyanKumarasamy
Add gamut remap to dc_stream_update struct, and program if set when updating
streams.
Change-Id: Iad520a93af1fd5345b85a2216c53882548145962
Signed-off-by: SivapiriyanKumarasamy
Reviewed-by: Anthony Koo
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/core/dc.c
From: Nicholas Kazlauskas
[Why]
A null pointer deference can occur if crtc is null in
amdgpu_dm_crtc_handle_crc_irq. This can happen if get_crtc_by_otg_inst
returns NULL during dm_crtc_high_irq, leading to a hang in some IGT
test cases.
[How]
Check that CRTC is non-null before accessing its fi
From: Mikita Lipski
[why]
We are disabling clock source while other pipes are still using
it, because we don't verify the number of pipes that share it.
[how]
- Adding a function in resources to return the number of pipes
sharing the clock source.
- Checking that no one is sharing the clock sour
From: Tony Cheng
Change-Id: I5dd27f5520845636cc5d3957f7ee14b12485a73c
Signed-off-by: Tony Cheng
Reviewed-by: Steven Chiu
Acked-by: Leo Li
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/
From: Mikita Lipski
[why]
Older ASICs require both phys_id and connector_id
to execute bios command table. If we are not passing the
right connector_id - it can lead to a black screen.
[how]
Set connector_obj_id when executing vbios command table
Change-Id: I23c73a9e60dbf7c386e7189a60fcea11e803
Hi Paul,
Answers as below:
-Original Message-
From: Paul Menzel
Sent: Wednesday, August 8, 2018 10:29 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk
Subject: Re: [PATCH] drm/amdgpu/sriov: give 8s for recover vram under RUNTIME
Dear Deng,
On 08/08/18 04:13, Emil
a helper function to create and initialize amdgpu bo
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 184 -
1 file changed, 84 insertions(+), 100 deletions(-)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..2cca40d 100
Sapphire Vega 64 Nitro+ is too noisy at idle, frequently switching
between zero-rpm mode and 1200 RPM.
As pwm1_min is currently always 0 (and thus completely useless), I:
- Made it writable so I can adjust min fan speed for "automatic" fan
control
- Changed amdgpu_hwmon_get_pwm1_min to return the
On Wed, Aug 08, 2018 at 06:47:49PM +0800, Christian König wrote:
> Am 08.08.2018 um 11:59 schrieb Huang Rui:
> > I continue to work for bulk moving that based on the proposal by Christian.
> >
> > Background:
> > amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move
> > all of
Dear Emily,
Thank you for your reply.
Am 09.08.2018 um 04:11 schrieb Deng, Emily:
Hi Paul,
Answers as below:
It’d be great if you had an mail user agent (email program) that
supports quoting. Maybe you could configure Outlook(?) that way? That
would tremendously useful for the mailing
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