On 2018年01月02日 22:47, Christian König wrote:
> Try to lock moved BOs if it's successful we can update the
> PTEs directly to the new location.
>
> v2: rebase
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 ++-
> 1 file changed, 14 insertions
On 2018年01月02日 22:47, Christian König wrote:
Update the PDEs after resetting the huge flag.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 60 ++
1 file changed, 18 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd
I still get a use-after-free with linux-4.15-rc6:
[ 16.788943]
==
[ 16.788968] BUG: KASAN: use-after-free in amdgpu_job_free_cb+0x140/0x150
[ 16.788975] Read of size 8 at addr 8803dfe4b3c8 by task kworker/0:2/1355
[ 16.7
Am 03.01.2018 um 09:29 schrieb Chunming Zhou:
On 2018年01月02日 22:47, Christian König wrote:
Update the PDEs after resetting the huge flag.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 60
++
1 file changed, 18 insertions(+),
Am 03.01.2018 um 09:10 schrieb Zhou, David(ChunMing):
On 2018年01月02日 22:47, Christian König wrote:
Try to lock moved BOs if it's successful we can update the
PTEs directly to the new location.
v2: rebase
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 ++
On 2018 Jan 03, Johannes Hirte wrote:
> This should be fixed already with
> https://lists.freedesktop.org/archives/amd-gfx/2017-October/014932.html
> but's still missing upstream.
>
With this patch, the use-after-free in amdgpu_job_free_cb seems to be
gone. But now I get an use-after-free in
drm
Hi Luis,
In general please add information like /proc/iomem and dmesg as
attachment and not mangled inside the mail.
The good news is that your ARM board at least has a memory layout which
should work in theory. So at least one problem rules out.
I don't think that apitrace would be much he
On 2018年01月03日 17:24, Christian König wrote:
Am 03.01.2018 um 09:29 schrieb Chunming Zhou:
On 2018年01月02日 22:47, Christian König wrote:
Update the PDEs after resetting the huge flag.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 60
++--
On 2018年01月03日 17:25, Christian König wrote:
Am 03.01.2018 um 09:10 schrieb Zhou, David(ChunMing):
On 2018年01月02日 22:47, Christian König wrote:
Try to lock moved BOs if it's successful we can update the
PTEs directly to the new location.
v2: rebase
Signed-off-by: Christian König
---
dr
Am 03.01.2018 um 11:43 schrieb Chunming Zhou:
On 2018年01月03日 17:25, Christian König wrote:
Am 03.01.2018 um 09:10 schrieb Zhou, David(ChunMing):
On 2018年01月02日 22:47, Christian König wrote:
Try to lock moved BOs if it's successful we can update the
PTEs directly to the new location.
v2: re
Hi Christian,
Replies follow in between.
Regards,
Luís
On Wed, Jan 3, 2018 at 9:37 AM, Christian König
wrote:
> Hi Luis,
>
> In general please add information like /proc/iomem and dmesg as attachment
> and not mangled inside the mail.
Ok, I'll take that into account next time. Sorry for the in
Hi Christian, David,
David, replying to your question... The issue is indeed reproducible
on x86, I just did it with kodi and the same VP9 video. So it is not
arm specific.
Regards,
Luís
On Wed, Jan 3, 2018 at 11:02 AM, Luís Mendes wrote:
> Hi Christian,
>
> Replies follow in between.
>
> Regar
+else if (reservation_object_trylock(resv))
+clear = false;
this will effect bo in bo list，wont it?
发自坚果 Pro
Koenig, Christian 于 2018年1月3日 下午6:47写道：
Am 03.01.2018 um 11:43 schrieb Chunming Zhou:
>
>
> On 2018年01月03日 17:25, Christian König wrote:
>> Am 03.01.2018
In this case please open a bug report on fdo and describe exactly how to
reproduce it.
Marek should be able to take a look then.
Thanks,
Christian.
Am 03.01.2018 um 12:56 schrieb Luís Mendes:
Hi Christian, David,
David, replying to your question... The issue is indeed reproducible
on x86, I
Am 03.01.2018 um 12:57 schrieb Zhou, David(ChunMing):
+else if (reservation_object_trylock(resv))
+clear = false;
this will effect bo in bo list，wont it?
Ah, now I get what you mean.
Yeah, that should be fixed or otherwise it will completely disable
vm_debug sup
Otherwise we would completely circumvent that debugging feature.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 81
Did you see my reply yesterday? I reviewed it. I also think we need to fix up
cz, rv, and vg10.
From: Tao, Yintian
Sent: Tuesday, January 2, 2018 9:22:23 PM
To: Tao, Yintian; amd-gfx@lists.freedesktop.org; Deucher, Alexander
Subject: RE: [PATCH] drm/amd/powerpla
On 2018-01-02 10:20 PM, Rex Zhu wrote:
> This patch can fix MultiGPU-Display blank
> out with 1 IGPU-4k display and 2 DGPU-two 4K
> displays.
>
> Change-Id: I41208feb6b275d9e8b45e9ef129e19c9739107a4
> Signed-off-by: Rex Zhu
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 9 +++--
> 1
On 2017-12-31 10:17 AM, Alex Deucher wrote:
> On Fri, Dec 29, 2017 at 6:11 AM, Daniel Drake wrote:
>> From: Yue Hin Lau
>>
>> Signed-off-by: Yue Hin Lau
>> Reviewed-by: Eric Bernstein
>> Acked-by: Harry Wentland
>> Signed-off-by: Alex Deucher
>> [dr...@endlessm.com: backport to 4.15]
>> Signe
On 12/23/2017 07:40 AM, Felix Kühling wrote:
> As I understand it, it would require changes in the ROCr Runtime and in
> the firmware (MEC microcode). It also changes the programming model, so
> it may affect certain applications or higher level language runtimes
> that rely on atomic operations.
>
On 2017-12-27 04:04 AM, Michel Dänzer wrote:
> On 2017-12-27 05:43 AM, Dieter Nützel wrote:
>> Hello AMD team,
>>
>> I got this since latest 'amd-staging-drm-next' git update
>> (#b956c586e58a) during boot with Polaris RX580 DC on:
>>
>> [ 3.586342] [drm:dal_bios_parser_init_cmd_tbl [amdgpu]] *E
On Monday, November 27, 2017 11:30:44 AM Daniel Vetter wrote:
> On Fri, Nov 24, 2017 at 06:53:25PM +0100, Michał Mirosław wrote:
> > This series cleans up duplicated code for replacing firmware FB
> > driver with proper DRI driver and adds handover support to
> > Tegra driver.
Please Cc: me on and
I assumed wrongfully that all relevant functions should be implemented.
Apparently this isn't the case. Demote the print to debug level for now.
Signed-off-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/bios/command_table.c| 22 +++---
.../gpu/drm/amd/display/dc/bios/comma
On 2018-01-02 10:57 AM, He, Roger wrote:
> Original Message-
> From: Michel Dänzer [mailto:mic...@daenzer.net]
> Sent: Wednesday, December 27, 2017 4:58 PM
> To: He, Roger ; Koenig, Christian
> ; Grodzovsky, Andrey
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd/amdgpu
I think currently atomic Ops are only used in AQL package which is only
available for ROCm , graphics workload will not use AQL package.
Regards
Shaoyun.liu
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Tom
Stellard
Sent: Wednesday, Janua
On Wed, Jan 3, 2018 at 10:18 AM, Harry Wentland wrote:
> I assumed wrongfully that all relevant functions should be implemented.
> Apparently this isn't the case. Demote the print to debug level for now.
>
> Signed-off-by: Harry Wentland
Acked-by: Alex Deucher
> ---
> .../gpu/drm/amd/display/
Agreed - MEC microcode uses atomics when the queue type is set to AQL (rather
than PM4).
>-Original Message-
>From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Liu, Shaoyun
>Sent: Wednesday, January 03, 2018 11:24 AM
>To: tstel...@redhat.com; Felix Kühling; amd-gf
On 2018-01-03 12:02 PM, Luís Mendes wrote:
>
> What I believe it seems to be the case is that the GPU lock up only
> happens when doing a page flip, since the kernel locks with:
> [ 243.693200] kworker/u4:3D089 2 0x
> [ 243.693232] Workqueue: events_unbound commit_work [
From: Mikita Lipski
Registers added to definition list that are required
for multi display synchronization
Signed-off-by: Mikita Lipski
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../amd/display/dc/dcn10/dcn10_timing_generator.h | 33 ++
From: Carlo Caione
Hi,
on several laptops [0] we are seeing display corruption when using multiple /
external displays. We already opened an issue upstream [1].
The following 4 patches are taken from agd5f/amd-staging-drm-next and they seem
able to solve the issue.
Can those be included in 4.15?
From: Mikita Lipski
This feature synchronizes multiple displays with various timings
to a display with the highest refresh rate
it is enabled if edid caps flag multi_display_sync is set to one
There are limitations on refresh rates allowed
that can be synchronized. That would
prevent from underf
From: "Leo (Sunpeng) Li"
This is a follow-up to the following change:
Yongqiang Sun: Program front end first when set mode.
Due to pipe-splitting features, how we handle stream enabling and
disabling needs to change.
In the case of pipe split disable, two planes need to be combined back
into t
From: Harry Wentland
Previous code threw a warning about misleading indentation
Signed-off-by: Harry Wentland
Reviewed-by: Mikita Lipski
Acked-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On 2017-12-29 08:36 PM, Felix Kuehling wrote:
> Is it possible that the test is broken? A test that allocates memory to
> exhaustion may well trigger the OOM killer. A test can do that by using
> malloc. Why not by using the graphics driver? The OOM killer does what
> it's supposed to do, and kills
On 2018-01-03 12:11 PM, Carlo Caione wrote:
> From: Carlo Caione
>
> Hi,
> on several laptops [0] we are seeing display corruption when using multiple /
> external displays. We already opened an issue upstream [1].
> The following 4 patches are taken from agd5f/amd-staging-drm-next and they
> se
On Wed, Jan 3, 2018 at 5:32 PM, Harry Wentland wrote:
> On 2018-01-03 12:11 PM, Carlo Caione wrote:
>> From: Carlo Caione
>>
>> Hi,
>> on several laptops [0] we are seeing display corruption when using multiple /
>> external displays. We already opened an issue upstream [1].
>> The following 4 pa
Hi Michel, Christian,
Christian, I have followed your suggestion and I have just submitted a
bug to fdo at https://bugs.freedesktop.org/show_bug.cgi?id=104481 -
GPU lockup Polaris 11 - AMD RX 460 and RX 550 on amd64 and on ARMv7
platforms while playing video.
Michel, amdgpu.dc=0 seems to make no
Hi Dave,
Just two small fixes for 4.15:
- backport of a DC change which fixes a greenish tint on some RV hw
- properly handle kzalloc fail in ttm
The following changes since commit 03bfd4e19b935adb8be4f7342f13395fb7f11096:
Merge tag 'drm-intel-fixes-2017-12-22-1' of
git://anongit.freedesktop.
On Tue, Jan 2, 2018 at 10:24 PM, Evan Quan wrote:
> Change-Id: I2683296f7b08cc637ed54b0b4b7db03b8818e658
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27
> --
> 1 file changed, 4 insertions(+), 23 deleti
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: I68bb53691fb2edca66c09391ab5e60357496283c
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c | 4 ++--
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 4 ++--
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: Ib4156edff8e3daaead720956142d8540df3254d8
> Signed-off-by: Evan Quan
Please include a commit message. Something like:
This will be used by powerplay to update the dpm temp range structure used to
interface with hwmon.
With that added
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: Icae6e15c7494d12bf8a194b9f1a352e0dcdef4ed
> Signed-off-by: Evan Quan
Please include a commit message. Something like:
Add a new callback for asic specific backends to specify the temperature ranges.
With that added:
Reviewed-by: Ale
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: I903ebb4d75ec0628e9720b6fee915c907e594613
> Signed-off-by: Evan Quan
Please include a commit message. Something like:
Populate the hwmon temp range as part of thermal controller setup.
With that added:
Reviewed-by: Alex Deucher
>
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: If240a45dd2538e93185802b1fce54fd83de89de0
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/power
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: I569179443c73c793153d5c499dd2f203f89e3ca2
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 26
>
> 1 file changed, 26 insertions(+)
>
> diff
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: I861e3e6d4ec553171cbf369eca4ac9d834478290
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/d
On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
> Change-Id: I861e3e6d4ec553171cbf369eca4ac9d834478290
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 20
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/
On Wed, Jan 3, 2018 at 3:16 PM, Alex Deucher wrote:
> On Tue, Jan 2, 2018 at 10:15 PM, Evan Quan wrote:
>> Change-Id: If240a45dd2538e93185802b1fce54fd83de89de0
>> Signed-off-by: Evan Quan
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 21
>> +
>> 1 file chan
From: Charlene Liu
Signed-off-by: Charlene Liu
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 21 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 21 +
From: Roman Li
Fixing regression introduced by
'Use real BE and FE index to program regs.'
Signed-off-by: Roman Li
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequenc
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequen
From: Yongqiang Sun
No need to use loop find opp, use opp in stream_res.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --
It's unused since the drm_edid_to_eld cleanup
Signed-off-by: Harry Wentland
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/displa
From: Eric Bernstein
Cleanup to remove unused register definition from hw sequencer
header file since implementation moved from hw sequencer to dchubub file.
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 76
From: "Leo (Sunpeng) Li"
Add interfaces in DC for per CRTC CRC configuration and fetching.
Also implement amdgpu_dm functions to hook onto DRM.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Tony Cheng
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 4 +
* Fix for null dereference non-DCN ASICs at boot
* CRC readback support for DCE 10 to DCE 11.2
* Bunch of DCN cleanup
Charlene Liu (1):
drm/amd/display: disablePSR in UpdatePlanes in PassiveLevel
Eric Bernstein (2):
drm/amd/display: clean up DCHUBBUB register definition in hwseq
drm/amd/
From: Eric Bernstein
Update dcn10_init_hw such that initialization of relevant
HW blocks for Maximus FPGA are also initialized (and not skipped).
Signed-off-by: Eric Bernstein
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 +++
From: Krunoslav Kovac
We assume FP16 1.0 frame buffer value maps to 80 nits.
DC changes are to make this configurable.
Signed-off-by: Krunoslav Kovac
Reviewed-by: Anthony Koo
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
drivers/gpu/drm/amd/display/dc/dc.h
From: Yongqiang Sun
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h| 6 --
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 ++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_o
From: "Leo (Sunpeng) Li"
Implement the timing generator hooks for configure_crc and get_crc.
Also implement is_tg_enabled, as configure_crc uses it.
Signed-off-by: Leo (Sunpeng) Li
Reviewed-by: Tony Cheng
Reviewed-by: Harry Wentland
---
.../display/dc/dce110/dce110_timing_generator.c| 12
This fixes the following two warnings:
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c: In function
‘phm_start_thermal_controller’:
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:9: warning:
braces around scalar initializer
struct PP_TemperatureRange range
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Harry
Wentland
Sent: Wednesday, January 3, 2018 3:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry
Subject: [PATCH] drm/amd/powerplay: Fix braces around scalar initializer warning
This fixes the f
Beacuse of PTI, I decided to test 4.15-rc6 on most of my test machines.
And I happened to notice a radeon problem on RV250 era card with no
monitor attached. 4.15-rc1 and earlier kernels did not show these
errors, not kernels between rc1 and rc6 have been tested yet.
The messages in dmes are st
> Beacuse of PTI, I decided to test 4.15-rc6 on most of my test machines.
> And I happened to notice a radeon problem on RV250 era card with no
> monitor attached. 4.15-rc1 and earlier kernels did not show these
> errors, not kernels between rc1 and rc6 have been tested yet.
Sorry, I can not re
Hi Michel, Christian,
Michel, I have tested amd-staging-drm-next at commit "drm/amdgpu/gfx9:
only init the apertures used by KGD (v2)" -
0e4946409d11913523d30bc4830d10b388438c7a and the issues remain, both
on ARMv7 and on x86 amd64.
Christian, in fact if I replay the apitraces obtained on the ARM
On Tue, Jan 2, 2018 at 3:49 PM, Andres Rodriguez wrote:
> We follow the same approach as gfx8. The only changes are register
> access macros.
>
> Tested on vega10. The execution latency results fall within the expected
> ranges from the polaris10 data.
>
> Signed-off-by: Andres Rodriguez
Reviewe
Fix my concern as well.
Reviewed-by: Roger He
Thanks
Roger(Hongbo.He)
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of
Christian K?nig
Sent: Wednesday, January 03, 2018 8:37 PM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: opt
Not typo. It shares the SMU7 structure.
Regards,
Evan
>-Original Message-
>From: Alex Deucher [mailto:alexdeuc...@gmail.com]
>Sent: Thursday, January 04, 2018 4:18 AM
>To: Quan, Evan
>Cc: amd-gfx list ; Deucher, Alexander
>
>Subject: Re: [PATCH 5/7] drm/amd/powerplay: export vega10 specif
On Wed, Jan 3, 2018 at 9:25 PM, Quan, Evan wrote:
> Not typo. It shares the SMU7 structure.
If all of these parts use the same values, can we just add it to some
common place? Also, all of these can be const I think.
Alex
>
> Regards,
> Evan
>>-Original Message-
>>From: Alex Deucher [m
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c: In
function 'phm_start_thermal_controller':
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:231:9:
warning: braces around scalar initializer [enabled by default]
struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, T
Please ignore this patch since i found there was already fix for this.
Regards,
Evan
>-Original Message-
>From: Evan Quan [mailto:evan.q...@amd.com]
>Sent: Thursday, January 04, 2018 10:55 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Quan, Evan
>Subject: [PATCH] drm/amd/powerplay: fix compi
On 2018-01-03 06:29 PM, Alex Deucher wrote:
On Tue, Jan 2, 2018 at 3:49 PM, Andres Rodriguez wrote:
We follow the same approach as gfx8. The only changes are register
access macros.
Tested on vega10. The execution latency results fall within the expected
ranges from the polaris10 data.
Sign
Hi Alex
Thanks a lot. I got it.
Best Regards
Yintian Tao
From: Deucher, Alexander
Sent: Wednesday, January 03, 2018 10:32 PM
To: Tao, Yintian ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/powerplay: fix memory leakage when reload
Did you see my reply yesterday? I reviewed it.
DC component expect PP to give max engine clock and
memory clock through pp_get_display_mode_validation_clocks
on DGPU as well.
This patch can fix MultiGPU-Display blank
out with 1 IGPU-4k display and 2 DGPU-two 4K
displays.
Change-Id: I20454060ebe01955c5653de037dd8c09a576026a
Signed-off-by: Rex
V2: reuse the SMUThermal structure defined in pp_thermal.h
Change-Id: I861e3e6d4ec553171cbf369eca4ac9d834478290
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_
V2: move the SMU7Thermal structure to newly created header file
Change-Id: I569179443c73c793153d5c499dd2f203f89e3ca2
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +
drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h | 6 ++
2 files cha
Created a new header file to place the shared structures.
Please check the coming V2 patches.
Regards,
Evan
>-Original Message-
>From: Alex Deucher [mailto:alexdeuc...@gmail.com]
>Sent: Thursday, January 04, 2018 10:53 AM
>To: Quan, Evan
>Cc: amd-gfx list ; Deucher, Alexander
>
>Subject:
On Wed, Jan 3, 2018 at 11:17 PM, Evan Quan wrote:
> V2: move the SMU7Thermal structure to newly created header file
>
> Change-Id: I569179443c73c793153d5c499dd2f203f89e3ca2
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +
> drivers/g
On Wed, Jan 3, 2018 at 11:17 PM, Evan Quan wrote:
> V2: reuse the SMUThermal structure defined in pp_thermal.h
>
> Change-Id: I861e3e6d4ec553171cbf369eca4ac9d834478290
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 15 +
V2: new header file to hold the common SMU7Thermal structure
Change-Id: If240a45dd2538e93185802b1fce54fd83de89de0
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 16 ++
drivers/gpu/drm/amd/powerplay/inc/pp_thermal.h | 34 ++
2 fil
The amdgpu.ids is only required when building with amdgpu support.
Fix not to add it without amdgpu.
Signed-off-by: Seung-Woo Kim
---
data/Makefile.am |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/data/Makefile.am b/data/Makefile.am
index eba915d..897a7f3 100644
--- a
v2: add table length check.
DC component expect PP to give max engine clock and
memory clock through pp_get_display_mode_validation_clocks
on DGPU as well.
This patch can fix MultiGPU-Display blank
out with 1 IGPU-4k display and 2 DGPU-two 4K
displays.
Change-Id: I20454060ebe01955c5653de037dd8c0
On Thu, Jan 4, 2018 at 1:01 AM, Rex Zhu wrote:
> v2: add table length check.
>
> DC component expect PP to give max engine clock and
> memory clock through pp_get_display_mode_validation_clocks
> on DGPU as well.
>
> This patch can fix MultiGPU-Display blank
> out with 1 IGPU-4k display and 2 DGPU
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